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| author | Cayetano Santos | 2020-03-08 19:59:22 +0100 |
|---|---|---|
| committer | Cayetano Santos | 2020-03-08 19:59:22 +0100 |
| commit | 0ef6472489c417b1a1705b5c573d55372941acc6 (patch) | |
| tree | d532a4c3186c9720c155a2820eec16a4edd4a2ac /.SRCINFO | |
| parent | 1b7ec8a8ebeaa1abe226835a0fe5ccee7eb5f83d (diff) | |
| download | aur-0ef6472489c417b1a1705b5c573d55372941acc6.tar.gz | |
fix provides variable
Diffstat (limited to '.SRCINFO')
| -rw-r--r-- | .SRCINFO | 3 |
1 files changed, 1 insertions, 2 deletions
@@ -11,10 +11,9 @@ pkgbase = python-fusesoc optdepends = iverilog: for simulating verilog designs optdepends = ghdl: for simulating VHDL designs provides = python-fusesoc - conflicts = python-fusesoc-git + conflicts = python-fusesoc options = !emptydirs source = https://github.com/olofk/fusesoc/releases/download/1.9/fusesoc-1.9.tar.gz md5sums = eec2d6fd3c8c68ce00b2eae7edb8e1a7 pkgname = python-fusesoc - |