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authorXiretza2022-10-23 21:04:57 +0200
committerXiretza2022-10-25 17:59:41 +0200
commit3cfcd3828b54ba4498efdd79fb8bcefc171fa932 (patch)
treebe74afe0275ea7a91d8e0634e6768717e1dd1658 /.SRCINFO
parentf847425e32602940127ac66c6e6380ec3b2d1805 (diff)
downloadaur-3cfcd3828b54ba4498efdd79fb8bcefc171fa932.tar.gz
Update to 2022.2
Diffstat (limited to '.SRCINFO')
-rw-r--r--.SRCINFO6
1 files changed, 3 insertions, 3 deletions
diff --git a/.SRCINFO b/.SRCINFO
index 65ea68891146..757915c5b151 100644
--- a/.SRCINFO
+++ b/.SRCINFO
@@ -1,6 +1,6 @@
pkgbase = vivado
pkgdesc = FPGA/CPLD design suite for Xilinx devices
- pkgver = 2022.1
+ pkgver = 2022.2
pkgrel = 1
url = https://www.xilinx.com/products/design-tools/vivado.html
arch = x86_64
@@ -18,9 +18,9 @@ pkgbase = vivado
optdepends = matlab: Model Composer
optdepends = qt4: Model Composer
options = !strip
- source = file:///Xilinx_Unified_2022.1_0420_0327.tar.gz
+ source = file:///Xilinx_Unified_2022.2_1014_8888.tar.gz
source = spoof_homedir.c
- md5sums = 0bf810cf5eaa28a849ab52b9bfdd20a5
+ md5sums = 4b4e84306eb631fe67d3efb469122671
md5sums = 69d14ad64f6ec44e041eaa8ffcb6f87c
pkgname = vivado