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authorVitalyR2023-06-01 15:15:41 +0800
committerVitalyR2023-06-01 15:15:41 +0800
commitbdfdce88b02bfb46278a6d707cdf54c3f40153f9 (patch)
tree631303e16cf6905b868da128171dd5362b0c8994 /.SRCINFO
parent3cfcd3828b54ba4498efdd79fb8bcefc171fa932 (diff)
downloadaur-bdfdce88b02bfb46278a6d707cdf54c3f40153f9.tar.gz
Update to 2023.1
Diffstat (limited to '.SRCINFO')
-rw-r--r--.SRCINFO6
1 files changed, 3 insertions, 3 deletions
diff --git a/.SRCINFO b/.SRCINFO
index 757915c5b151..736fdfdb7a27 100644
--- a/.SRCINFO
+++ b/.SRCINFO
@@ -1,6 +1,6 @@
pkgbase = vivado
pkgdesc = FPGA/CPLD design suite for Xilinx devices
- pkgver = 2022.2
+ pkgver = 2023.1
pkgrel = 1
url = https://www.xilinx.com/products/design-tools/vivado.html
arch = x86_64
@@ -18,9 +18,9 @@ pkgbase = vivado
optdepends = matlab: Model Composer
optdepends = qt4: Model Composer
options = !strip
- source = file:///Xilinx_Unified_2022.2_1014_8888.tar.gz
+ source = file:///Xilinx_Unified_2023.1_0507_1903.tar.gz
source = spoof_homedir.c
- md5sums = 4b4e84306eb631fe67d3efb469122671
+ md5sums = f2011ceba52b109e3551c1d3189a8c9c
md5sums = 69d14ad64f6ec44e041eaa8ffcb6f87c
pkgname = vivado