first commit

1 files changed, 261 insertions, 0 deletions

diff --git a/0002_binutils-texinfo-5.0-gas-doc.patch b/0002_binutils-texinfo-5.0-gas-doc.patch
new file mode 100644
index 000000000000..e20c8b67b9a2
--- /dev/null
+++ b/0002_binutils-texinfo-5.0-gas-doc.patch
@@ -0,0 +1,261 @@
+diff --git c/gas/doc/c-arc.texi i/gas/doc/c-arc.texi
+index 3a136a7..cd6f0d9 100644
+--- c/gas/doc/c-arc.texi
++++ i/gas/doc/c-arc.texi
+@@ -212,7 +212,7 @@ The extension instructions are not macros.  The assembler creates
+ encodings for use of these instructions according to the specification
+ by the user.  The parameters are:
+ 
+-@table @bullet
++@table @code
+ @item @var{name}
+ Name of the extension instruction 
+ 
+diff --git c/gas/doc/c-arm.texi i/gas/doc/c-arm.texi
+index d3cccf4..97c2f92 100644
+--- c/gas/doc/c-arm.texi
++++ i/gas/doc/c-arm.texi
+@@ -376,29 +376,29 @@ ARM and THUMB instructions had their own, separate syntaxes.  The new,
+ @code{unified} syntax, which can be selected via the @code{.syntax}
+ directive, and has the following main features:
+ 
+-@table @bullet
+-@item
++@table @code
++@item 1
+ Immediate operands do not require a @code{#} prefix.
+ 
+-@item
++@item 2
+ The @code{IT} instruction may appear, and if it does it is validated
+ against subsequent conditional affixes.  In ARM mode it does not
+ generate machine code, in THUMB mode it does.
+ 
+-@item
++@item 3
+ For ARM instructions the conditional affixes always appear at the end
+ of the instruction.  For THUMB instructions conditional affixes can be
+ used, but only inside the scope of an @code{IT} instruction.
+ 
+-@item
++@item 4
+ All of the instructions new to the V6T2 architecture (and later) are
+ available.  (Only a few such instructions can be written in the
+ @code{divided} syntax).
+ 
+-@item
++@item 5
+ The @code{.N} and @code{.W} suffixes are recognized and honored.
+ 
+-@item
++@item 6
+ All instructions set the flags if and only if they have an @code{s}
+ affix.
+ @end table
+@@ -433,28 +433,6 @@ Either @samp{#} or @samp{$} can be used to indicate immediate operands.
+ @cindex register names, ARM
+ *TODO* Explain about ARM register naming, and the predefined names.
+ 
+-@node ARM-Neon-Alignment
+-@subsection NEON Alignment Specifiers
+-
+-@cindex alignment for NEON instructions
+-Some NEON load/store instructions allow an optional address
+-alignment qualifier.
+-The ARM documentation specifies that this is indicated by
+-@samp{@@ @var{align}}. However GAS already interprets
+-the @samp{@@} character as a "line comment" start,
+-so @samp{: @var{align}} is used instead.  For example:
+-
+-@smallexample
+-        vld1.8 @{q0@}, [r0, :128]
+-@end smallexample
+-
+-@node ARM Floating Point
+-@section Floating Point
+-
+-@cindex floating point, ARM (@sc{ieee})
+-@cindex ARM floating point (@sc{ieee})
+-The ARM family uses @sc{ieee} floating-point numbers.
+-
+ @node ARM-Relocations
+ @subsection ARM relocation generation
+ 
+@@ -497,6 +475,28 @@ respectively.  For example to load the 32-bit address of foo into r0:
+         MOVT r0, #:upper16:foo
+ @end smallexample
+ 
++@node ARM-Neon-Alignment
++@subsection NEON Alignment Specifiers
++
++@cindex alignment for NEON instructions
++Some NEON load/store instructions allow an optional address
++alignment qualifier.
++The ARM documentation specifies that this is indicated by
++@samp{@@ @var{align}}. However GAS already interprets
++the @samp{@@} character as a "line comment" start,
++so @samp{: @var{align}} is used instead.  For example:
++
++@smallexample
++        vld1.8 @{q0@}, [r0, :128]
++@end smallexample
++
++@node ARM Floating Point
++@section Floating Point
++
++@cindex floating point, ARM (@sc{ieee})
++@cindex ARM floating point (@sc{ieee})
++The ARM family uses @sc{ieee} floating-point numbers.
++
+ @node ARM Directives
+ @section ARM Machine Directives
+ 
+diff --git c/gas/doc/c-cr16.texi i/gas/doc/c-cr16.texi
+index b6cf10f..00ddae2 100644
+--- c/gas/doc/c-cr16.texi
++++ i/gas/doc/c-cr16.texi
+@@ -43,26 +43,33 @@ Operand expression type qualifier is an optional field in the instruction operan
+ CR16 target operand qualifiers and its size (in bits):
+ 
+ @table @samp
+-@item Immediate Operand
+-- s ---- 4 bits
+-@item 
+-- m ---- 16 bits, for movb and movw instructions.
+-@item 
+-- m ---- 20 bits, movd instructions.
+-@item 
+-- l ---- 32 bits
+-
+-@item Absolute Operand
+-- s ---- Illegal specifier for this operand.
+-@item  
+-- m ---- 20 bits, movd instructions.
+-
+-@item Displacement Operand
+-- s ---- 8 bits
+-@item
+-- m ---- 16 bits
+-@item 
+-- l ---- 24 bits
++@item Immediate Operand: s
++4 bits.
++
++@item Immediate Operand: m
++16 bits, for movb and movw instructions.
++
++@item Immediate Operand: m
++20 bits, movd instructions.
++
++@item Immediate Operand: l
++32 bits.
++
++@item Absolute Operand: s
++Illegal specifier for this operand.
++
++@item Absolute Operand: m
++20 bits, movd instructions.
++
++@item Displacement Operand: s
++8 bits.
++
++@item Displacement Operand: m
++16 bits.
++
++@item Displacement Operand: l
++24 bits
++
+ @end table
+ 
+ For example:
+diff --git c/gas/doc/c-mips.texi i/gas/doc/c-mips.texi
+index 715091e..1250c1e 100644
+--- c/gas/doc/c-mips.texi
++++ i/gas/doc/c-mips.texi
+@@ -220,7 +220,7 @@ the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
+ instructions around accesses to the @samp{HI} and @samp{LO} registers.
+ @samp{-no-m4650} turns off this option.
+ 
+-@itemx -m3900
++@item -m3900
+ @itemx -no-m3900
+ @itemx -m4100
+ @itemx -no-m4100
+diff --git c/gas/doc/c-score.texi i/gas/doc/c-score.texi
+index 0820115..a5b570f 100644
+--- c/gas/doc/c-score.texi
++++ i/gas/doc/c-score.texi
+@@ -36,7 +36,7 @@ implicitly with the @code{gp} register. The default value is 8.
+ @item -EB
+ Assemble code for a big-endian cpu
+ 
+-@itemx -EL
++@item -EL
+ Assemble code for a little-endian cpu
+ 
+ @item -FIXDD 
+@@ -48,13 +48,13 @@ Assemble code for no warning message for fix data dependency
+ @item -SCORE5
+ Assemble code for target is SCORE5
+ 
+-@itemx -SCORE5U
++@item -SCORE5U
+ Assemble code for target is SCORE5U
+ 
+-@itemx -SCORE7
++@item -SCORE7
+ Assemble code for target is SCORE7, this is default setting
+ 
+-@itemx -SCORE3
++@item -SCORE3
+ Assemble code for target is SCORE3
+ 
+ @item -march=score7
+diff --git c/gas/doc/c-tic54x.texi i/gas/doc/c-tic54x.texi
+index 4cfb440..9d631a6 100644
+--- c/gas/doc/c-tic54x.texi
++++ i/gas/doc/c-tic54x.texi
+@@ -108,7 +108,7 @@ In this example, x is replaced with SYM2; SYM2 is replaced with SYM1, and SYM1
+ is replaced with x.  At this point, x has already been encountered
+ and the substitution stops.
+ 
+-@smallexample @code
++@smallexample
+  .asg   "x",SYM1 
+  .asg   "SYM1",SYM2
+  .asg   "SYM2",x
+@@ -125,14 +125,14 @@ Substitution may be forced in situations where replacement might be
+ ambiguous by placing colons on either side of the subsym.  The following
+ code: 
+ 
+-@smallexample @code
++@smallexample
+  .eval  "10",x
+ LAB:X:  add     #x, a
+ @end smallexample
+ 
+ When assembled becomes:
+ 
+-@smallexample @code
++@smallexample
+ LAB10  add     #10, a
+ @end smallexample
+ 
+@@ -308,7 +308,7 @@ The @code{LDX} pseudo-op is provided for loading the extended addressing bits
+ of a label or address.  For example, if an address @code{_label} resides
+ in extended program memory, the value of @code{_label} may be loaded as
+ follows:
+-@smallexample @code
++@smallexample
+  ldx     #_label,16,a    ; loads extended bits of _label
+  or      #_label,a       ; loads lower 16 bits of _label
+  bacc    a               ; full address is in accumulator A
+@@ -344,7 +344,7 @@ Assign @var{name} the string @var{string}.  String replacement is
+ performed on @var{string} before assignment.
+ 
+ @cindex @code{eval} directive, TIC54X
+-@itemx .eval @var{string}, @var{name}
++@item .eval @var{string}, @var{name}
+ Evaluate the contents of string @var{string} and assign the result as a
+ string to the subsym @var{name}.  String replacement is performed on
+ @var{string} before assignment.