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authornuvole2024-12-15 21:00:20 +0800
committernuvole2024-12-15 21:01:04 +0800
commitc1ba112dcaafbb6326d85526ca194bba8693dc71 (patch)
treeb0405667b1276b1b5118a4e04160c30cbff3a4d5 /0011-arm64-dts-qcom-sx8280xp-Add-dsi-node-for-SC8280XP.patch
downloadaur-c1ba112dcaafbb6326d85526ca194bba8693dc71.tar.gz
v6.12.4: initial commit
Diffstat (limited to '0011-arm64-dts-qcom-sx8280xp-Add-dsi-node-for-SC8280XP.patch')
-rw-r--r--0011-arm64-dts-qcom-sx8280xp-Add-dsi-node-for-SC8280XP.patch483
1 files changed, 483 insertions, 0 deletions
diff --git a/0011-arm64-dts-qcom-sx8280xp-Add-dsi-node-for-SC8280XP.patch b/0011-arm64-dts-qcom-sx8280xp-Add-dsi-node-for-SC8280XP.patch
new file mode 100644
index 000000000000..5170de4f120c
--- /dev/null
+++ b/0011-arm64-dts-qcom-sx8280xp-Add-dsi-node-for-SC8280XP.patch
@@ -0,0 +1,483 @@
+From dfb69d93e420e44c2a2c6bea7b8e134c0746664c Mon Sep 17 00:00:00 2001
+From: nuvole <mitltlatltl@gmail.com>
+Date: Wed, 3 Jul 2024 11:18:04 +0800
+Subject: [PATCH 11/16] arm64: dts: qcom: sx8280xp: Add dsi node for SC8280XP
+
+Signed-off-by: nuvole <mitltlatltl@gmail.com>
+---
+ arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 424 ++++++++++++++++++++++++-
+ 1 file changed, 416 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+index 8c5b0214f..430766eeb 100644
+--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
++++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+@@ -4253,6 +4253,20 @@ mdss0_intf0_out: endpoint {
+ };
+ };
+
++ port@1 { // refer to drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
++ reg = <1>;
++ mdss0_intf1_out: endpoint {
++ remote-endpoint = <&mdss0_dsi0_in>;
++ };
++ };
++
++ port@2 {
++ reg = <2>;
++ mdss0_intf2_out: endpoint {
++ remote-endpoint = <&mdss0_dsi1_in>;
++ };
++ };
++
+ port@4 {
+ reg = <4>;
+ mdss0_intf4_out: endpoint {
+@@ -4383,6 +4397,196 @@ opp-810000000 {
+ };
+ };
+
++ mdss0_dsi0: dsi@ae94000 {
++ compatible = "qcom,sc8280xp-dsi-ctrl", "qcom,mdss-dsi-ctrl";/* "qcom,sc8280xp-dsi-ctrl" is dummy */
++ reg = <0 0x0ae94000 0 0x400>;
++ reg-names = "dsi_ctrl";
++
++ interrupt-parent = <&mdss0>;
++ interrupts = <4>;
++
++ clocks = <&dispcc0 DISP_CC_MDSS_BYTE0_CLK>,
++ <&dispcc0 DISP_CC_MDSS_BYTE0_INTF_CLK>,
++ <&dispcc0 DISP_CC_MDSS_PCLK0_CLK>,
++ <&dispcc0 DISP_CC_MDSS_ESC0_CLK>,
++ <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
++ <&gcc GCC_DISP_HF_AXI_CLK>;
++ clock-names = "byte",
++ "byte_intf",
++ "pixel",
++ "core",
++ "iface",
++ "bus";
++
++ assigned-clocks = <&dispcc0 DISP_CC_MDSS_BYTE0_CLK_SRC>,
++ <&dispcc0 DISP_CC_MDSS_PCLK0_CLK_SRC>;
++ assigned-clock-parents = <&mdss0_dsi0_phy 0>,
++ <&mdss0_dsi0_phy 1>;
++
++ operating-points-v2 = <&mdss0_dsi0_opp_table>;
++ power-domains = <&rpmhpd SC8280XP_MMCX>;
++
++ phy-names = "dsi";
++
++ phys = <&mdss0_dsi0_phy>;
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ status = "disabled";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ reg = <0>;
++ mdss0_dsi0_in: endpoint {
++ remote-endpoint = <&mdss0_intf1_out>;
++ };
++ };
++
++ port@1 {
++ reg = <1>;
++ mdss0_dsi0_out: endpoint {
++ };
++ };
++ };
++
++ mdss0_dsi0_opp_table: opp-table {
++ compatible = "operating-points-v2";
++
++ opp-187500000 {
++ opp-hz = /bits/ 64 <187500000>;
++ required-opps = <&rpmhpd_opp_low_svs>;
++ };
++
++ opp-300000000 {
++ opp-hz = /bits/ 64 <300000000>;
++ required-opps = <&rpmhpd_opp_svs>;
++ };
++
++ opp-358000000 {
++ opp-hz = /bits/ 64 <358000000>;
++ required-opps = <&rpmhpd_opp_svs_l1>;
++ };
++ };
++ };
++
++ mdss0_dsi0_phy: phy@ae94400 {
++ compatible = "qcom,sc8280xp-dsi-phy-5nm";
++ reg = <0 0x0ae94400 0 0x200>,
++ <0 0x0ae94600 0 0x280>,
++ <0 0x0ae94900 0 0x27c>;// FIXME maybe 0x260?
++ reg-names = "dsi_phy",
++ "dsi_phy_lane",
++ "dsi_pll";
++
++ #clock-cells = <1>;
++ #phy-cells = <0>;
++
++ clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
++ <&rpmhcc RPMH_CXO_CLK>;
++ clock-names = "iface", "ref";
++
++ status = "disabled";
++ };
++
++ mdss0_dsi1: dsi@ae96000 {
++ compatible = "qcom,sc8280xp-dsi-ctrl", "qcom,mdss-dsi-ctrl";
++ reg = <0 0x0ae96000 0 0x400>;
++ reg-names = "dsi_ctrl";
++
++ interrupt-parent = <&mdss0>;
++ interrupts = <5>;
++
++ clocks = <&dispcc0 DISP_CC_MDSS_BYTE1_CLK>,
++ <&dispcc0 DISP_CC_MDSS_BYTE1_INTF_CLK>,
++ <&dispcc0 DISP_CC_MDSS_PCLK1_CLK>,
++ <&dispcc0 DISP_CC_MDSS_ESC1_CLK>,
++ <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
++ <&gcc GCC_DISP_HF_AXI_CLK>;
++ clock-names = "byte",
++ "byte_intf",
++ "pixel",
++ "core",
++ "iface",
++ "bus";
++
++ assigned-clocks = <&dispcc0 DISP_CC_MDSS_BYTE1_CLK_SRC>,
++ <&dispcc0 DISP_CC_MDSS_PCLK1_CLK_SRC>;
++ assigned-clock-parents = <&mdss0_dsi1_phy 0>,
++ <&mdss0_dsi1_phy 1>;
++
++ operating-points-v2 = <&mdss0_dsi1_opp_table>;
++ power-domains = <&rpmhpd SC8280XP_MMCX>;
++
++ phys = <&mdss0_dsi1_phy>;
++ phy-names = "dsi";
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ status = "disabled";
++
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ reg = <0>;
++ mdss0_dsi1_in: endpoint {
++ remote-endpoint = <&mdss0_intf2_out>;
++ };
++ };
++
++ port@1 {
++ reg = <1>;
++ mdss0_dsi1_out: endpoint {
++ };
++ };
++ };
++
++ mdss0_dsi1_opp_table: opp-table {
++ compatible = "operating-points-v2";
++
++ opp-187500000 {
++ opp-hz = /bits/ 64 <187500000>;
++ required-opps = <&rpmhpd_opp_low_svs>;
++ };
++
++ opp-300000000 {
++ opp-hz = /bits/ 64 <300000000>;
++ required-opps = <&rpmhpd_opp_svs>;
++ };
++
++ opp-358000000 {
++ opp-hz = /bits/ 64 <358000000>;
++ required-opps = <&rpmhpd_opp_svs_l1>;
++ };
++ };
++ };
++
++ mdss0_dsi1_phy: phy@ae96400 {
++ compatible = "qcom,sc8280xp-dsi-phy-5nm";
++ reg = <0 0x0ae96400 0 0x200>,
++ <0 0x0ae96600 0 0x280>,
++ <0 0x0ae96900 0 0x27c>;// FIXME maybe 0x260?
++ reg-names = "dsi_phy",
++ "dsi_phy_lane",
++ "dsi_pll";
++
++ #clock-cells = <1>;
++ #phy-cells = <0>;
++
++ clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
++ <&rpmhcc RPMH_CXO_CLK>;
++ clock-names = "iface", "ref";
++
++ status = "disabled";
++ };
++
+ mdss0_dp1: displayport-controller@ae98000 {
+ compatible = "qcom,sc8280xp-dp";
+ reg = <0 0xae98000 0 0x200>,
+@@ -4657,10 +4861,10 @@ dispcc0: clock-controller@af00000 {
+ <&mdss0_dp2_phy 1>,
+ <&mdss0_dp3_phy 0>,
+ <&mdss0_dp3_phy 1>,
+- <0>,
+- <0>,
+- <0>,
+- <0>;
++ <&mdss0_dsi0_phy 0>,// why this order? refer to drivers/clk/qcom/dispcc-sc8280xp.c
++ <&mdss0_dsi0_phy 1>,
++ <&mdss0_dsi1_phy 0>,
++ <&mdss0_dsi1_phy 1>;
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+ #clock-cells = <1>;
+@@ -5563,6 +5767,20 @@ mdss1_intf0_out: endpoint {
+ };
+ };
+
++ port@1 {
++ reg = <1>;
++ mdss1_intf1_out: endpoint {
++ remote-endpoint = <&mdss1_dsi0_in>;
++ };
++ };
++
++ port@2 {
++ reg = <2>;
++ mdss1_intf2_out: endpoint {
++ remote-endpoint = <&mdss1_dsi1_in>;
++ };
++ };
++
+ port@4 {
+ reg = <4>;
+ mdss1_intf4_out: endpoint {
+@@ -5686,6 +5904,196 @@ opp-810000000 {
+ };
+ };
+
++ mdss1_dsi0: dsi@22094000 {
++ compatible = "qcom,sc8280xp-dsi-ctrl", "qcom,mdss-dsi-ctrl";
++ reg = <0 0x22094000 0 0x400>;
++ reg-names = "dsi_ctrl";
++
++ interrupt-parent = <&mdss1>;
++ interrupts = <4>;
++
++ clocks = <&dispcc1 DISP_CC_MDSS_BYTE0_CLK>,
++ <&dispcc1 DISP_CC_MDSS_BYTE0_INTF_CLK>,
++ <&dispcc1 DISP_CC_MDSS_PCLK0_CLK>,
++ <&dispcc1 DISP_CC_MDSS_ESC0_CLK>,
++ <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
++ <&gcc GCC_DISP_HF_AXI_CLK>;
++ clock-names = "byte",
++ "byte_intf",
++ "pixel",
++ "core",
++ "iface",
++ "bus";
++
++ assigned-clocks = <&dispcc1 DISP_CC_MDSS_BYTE0_CLK_SRC>,
++ <&dispcc1 DISP_CC_MDSS_PCLK0_CLK_SRC>;
++ assigned-clock-parents = <&mdss1_dsi1_phy 0>,
++ <&mdss1_dsi0_phy 1>;
++
++ operating-points-v2 = <&mdss1_dsi0_opp_table>;
++ power-domains = <&rpmhpd SC8280XP_MMCX>;
++
++ phy-names = "dsi";
++
++ phys = <&mdss1_dsi0_phy>;
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ status = "disabled";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ reg = <0>;
++ mdss1_dsi0_in: endpoint {
++ remote-endpoint = <&mdss1_intf1_out>;
++ };
++ };
++
++ port@1 {
++ reg = <1>;
++ mdss1_dsi0_out: endpoint {
++ };
++ };
++ };
++
++ mdss1_dsi0_opp_table: opp-table {
++ compatible = "operating-points-v2";
++
++ opp-187500000 {
++ opp-hz = /bits/ 64 <187500000>;
++ required-opps = <&rpmhpd_opp_low_svs>;
++ };
++
++ opp-300000000 {
++ opp-hz = /bits/ 64 <300000000>;
++ required-opps = <&rpmhpd_opp_svs>;
++ };
++
++ opp-358000000 {
++ opp-hz = /bits/ 64 <358000000>;
++ required-opps = <&rpmhpd_opp_svs_l1>;
++ };
++ };
++ };
++
++ mdss1_dsi0_phy: phy@22094400 {
++ compatible = "qcom,sc8280xp-dsi-phy-5nm";
++ reg = <0 0x22094400 0 0x200>,
++ <0 0x22094600 0 0x280>,
++ <0 0x22094900 0 0x260>;
++ reg-names = "dsi_phy",
++ "dsi_phy_lane",
++ "dsi_pll";
++
++ #clock-cells = <1>;
++ #phy-cells = <0>;
++
++ clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
++ <&rpmhcc RPMH_CXO_CLK>;
++ clock-names = "iface", "ref";
++
++ status = "disabled";
++ };
++
++ mdss1_dsi1: dsi@22096000 {
++ compatible = "qcom,sc8280xp-dsi-ctrl", "qcom,mdss-dsi-ctrl";
++ reg = <0 0x22096000 0 0x400>;
++ reg-names = "dsi_ctrl";
++
++ interrupt-parent = <&mdss1>;
++ interrupts = <5>;
++
++ clocks = <&dispcc1 DISP_CC_MDSS_BYTE1_CLK>,
++ <&dispcc1 DISP_CC_MDSS_BYTE1_INTF_CLK>,
++ <&dispcc1 DISP_CC_MDSS_PCLK1_CLK>,
++ <&dispcc1 DISP_CC_MDSS_ESC1_CLK>,
++ <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
++ <&gcc GCC_DISP_HF_AXI_CLK>;
++ clock-names = "byte",
++ "byte_intf",
++ "pixel",
++ "core",
++ "iface",
++ "bus";
++
++ assigned-clocks = <&dispcc1 DISP_CC_MDSS_BYTE1_CLK_SRC>,
++ <&dispcc1 DISP_CC_MDSS_PCLK1_CLK_SRC>;
++ assigned-clock-parents = <&mdss1_dsi1_phy 0>,
++ <&mdss1_dsi1_phy 1>;
++
++ operating-points-v2 = <&mdss1_dsi1_opp_table>;
++ power-domains = <&rpmhpd SC8280XP_MMCX>;
++
++ phys = <&mdss1_dsi1_phy>;
++ phy-names = "dsi";
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ status = "disabled";
++
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ reg = <0>;
++ mdss1_dsi1_in: endpoint {
++ remote-endpoint = <&mdss1_intf2_out>;
++ };
++ };
++
++ port@1 {
++ reg = <1>;
++ mdss1_dsi1_out: endpoint {
++ };
++ };
++ };
++
++ mdss1_dsi1_opp_table: opp-table {
++ compatible = "operating-points-v2";
++
++ opp-187500000 {
++ opp-hz = /bits/ 64 <187500000>;
++ required-opps = <&rpmhpd_opp_low_svs>;
++ };
++
++ opp-300000000 {
++ opp-hz = /bits/ 64 <300000000>;
++ required-opps = <&rpmhpd_opp_svs>;
++ };
++
++ opp-358000000 {
++ opp-hz = /bits/ 64 <358000000>;
++ required-opps = <&rpmhpd_opp_svs_l1>;
++ };
++ };
++ };
++
++ mdss1_dsi1_phy: phy@22096400 {
++ compatible = "qcom,sc8280xp-dsi-phy-5nm";
++ reg = <0 0x22096400 0 0x200>,
++ <0 0x22096600 0 0x280>,
++ <0 0x22096900 0 0x260>;
++ reg-names = "dsi_phy",
++ "dsi_phy_lane",
++ "dsi_pll";
++
++ #clock-cells = <1>;
++ #phy-cells = <0>;
++
++ clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
++ <&rpmhcc RPMH_CXO_CLK>;
++ clock-names = "iface", "ref";
++
++ status = "disabled";
++ };
++
+ mdss1_dp1: displayport-controller@22098000 {
+ compatible = "qcom,sc8280xp-dp";
+ reg = <0 0x22098000 0 0x200>,
+@@ -5954,10 +6362,10 @@ dispcc1: clock-controller@22100000 {
+ <&mdss1_dp2_phy 1>,
+ <&mdss1_dp3_phy 0>,
+ <&mdss1_dp3_phy 1>,
+- <0>,
+- <0>,
+- <0>,
+- <0>;
++ <&mdss1_dsi0_phy 0>,
++ <&mdss1_dsi0_phy 1>,
++ <&mdss1_dsi1_phy 0>,
++ <&mdss1_dsi1_phy 1>;
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+
+ #clock-cells = <1>;
+--
+2.47.1
+