Update to 6.0.2.pf2-1

- New upstream release based on 6.0.2
- Sync kernel config with Arch and Arch32
- Store patches in git

Signed-off-by: Björn Bidar <bjorn.bidar@thaodan.de>

1 files changed, 0 insertions, 92 deletions

diff --git a/0029-mmc-sdhci-of-dwcmshc-add-reset-call-back-for-rockchi.patch b/0029-mmc-sdhci-of-dwcmshc-add-reset-call-back-for-rockchi.patch
deleted file mode 100644
index c41845c29e0e..000000000000
--- a/0029-mmc-sdhci-of-dwcmshc-add-reset-call-back-for-rockchi.patch
+++ /dev/null
@@ -1,92 +0,0 @@
-From d1541cdf5aecb0b85c26624478b154cce920281b Mon Sep 17 00:00:00 2001
-From: Yifeng Zhao <yifeng.zhao@rock-chips.com>
-Date: Wed, 4 May 2022 23:32:39 +0200
-Subject: [PATCH 29/73] mmc: sdhci-of-dwcmshc: add reset call back for rockchip
- Socs
-
-[ Upstream commit 70f832206fe72e9998b46363e8e59e89b0b757bc ]
-
-The reset function build in the SDHCI will not reset the logic
-circuit related to the tuning function, which may cause data
-reading errors. Resetting the complete SDHCI controller through
-the reset controller fixes the issue.
-
-Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
-[rebase, use optional variant of reset getter]
-Acked-by: Adrian Hunter <adrian.hunter@intel.com>
-Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
-Link: https://lore.kernel.org/r/20220504213251.264819-10-sebastian.reichel@collabora.com
-Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/mmc/host/sdhci-of-dwcmshc.c | 26 +++++++++++++++++++++++++-
- 1 file changed, 25 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
-index bac874ab0b33..3a1b5ba36405 100644
---- a/drivers/mmc/host/sdhci-of-dwcmshc.c
-+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
-@@ -15,6 +15,7 @@
- #include <linux/module.h>
- #include <linux/of.h>
- #include <linux/of_device.h>
-+#include <linux/reset.h>
- #include <linux/sizes.h>
- 
- #include "sdhci-pltfm.h"
-@@ -63,6 +64,7 @@
- struct rk3568_priv {
- 	/* Rockchip specified optional clocks */
- 	struct clk_bulk_data rockchip_clks[RK3568_MAX_CLKS];
-+	struct reset_control *reset;
- 	u8 txclk_tapnum;
- };
- 
-@@ -255,6 +257,21 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock
- 	sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
- }
- 
-+static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask)
-+{
-+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
-+	struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
-+	struct rk35xx_priv *priv = dwc_priv->priv;
-+
-+	if (mask & SDHCI_RESET_ALL && priv->reset) {
-+		reset_control_assert(priv->reset);
-+		udelay(1);
-+		reset_control_deassert(priv->reset);
-+	}
-+
-+	sdhci_reset(host, mask);
-+}
-+
- static const struct sdhci_ops sdhci_dwcmshc_ops = {
- 	.set_clock		= sdhci_set_clock,
- 	.set_bus_width		= sdhci_set_bus_width,
-@@ -269,7 +286,7 @@ static const struct sdhci_ops sdhci_dwcmshc_rk3568_ops = {
- 	.set_bus_width		= sdhci_set_bus_width,
- 	.set_uhs_signaling	= dwcmshc_set_uhs_signaling,
- 	.get_max_clock		= sdhci_pltfm_clk_get_max_clock,
--	.reset			= sdhci_reset,
-+	.reset			= rk35xx_sdhci_reset,
- 	.adma_write_desc	= dwcmshc_adma_write_desc,
- };
- 
-@@ -292,6 +309,13 @@ static int dwcmshc_rk3568_init(struct sdhci_host *host, struct dwcmshc_priv *dwc
- 	int err;
- 	struct rk3568_priv *priv = dwc_priv->priv;
- 
-+	priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc));
-+	if (IS_ERR(priv->reset)) {
-+		err = PTR_ERR(priv->reset);
-+		dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err);
-+		return err;
-+	}
-+
- 	priv->rockchip_clks[0].id = "axi";
- 	priv->rockchip_clks[1].id = "block";
- 	priv->rockchip_clks[2].id = "timer";
--- 
-2.37.3
-