diff options
| author | dingjingmaster | 2020-09-24 20:40:56 +0800 |
|---|---|---|
| committer | dingjingmaster | 2020-09-24 20:40:56 +0800 |
| commit | 1872ea3a3b8c1bc9f696c250675064569e438f2b (patch) | |
| tree | 0777f88509464742455290aa77923bd182ad52bf /0303-pinctrl-amd.patch | |
| download | aur-1872ea3a3b8c1bc9f696c250675064569e438f2b.tar.gz | |
yay
Diffstat (limited to '0303-pinctrl-amd.patch')
| -rw-r--r-- | 0303-pinctrl-amd.patch | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/0303-pinctrl-amd.patch b/0303-pinctrl-amd.patch new file mode 100644 index 000000000000..5554afa23792 --- /dev/null +++ b/0303-pinctrl-amd.patch @@ -0,0 +1,29 @@ +diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c +index 1fe62a35bb12..c34e6a950b3f 100644 +--- a/drivers/pinctrl/pinctrl-amd.c ++++ b/drivers/pinctrl/pinctrl-amd.c +@@ -417,22 +417,13 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) + { + int ret = 0; + u32 pin_reg, pin_reg_irq_en, mask; +- unsigned long flags, irq_flags; ++ unsigned long flags; + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct amd_gpio *gpio_dev = gpiochip_get_data(gc); + + raw_spin_lock_irqsave(&gpio_dev->lock, flags); + pin_reg = readl(gpio_dev->base + (d->hwirq)*4); + +- /* Ignore the settings coming from the client and +- * read the values from the ACPI tables +- * while setting the trigger type +- */ +- +- irq_flags = irq_get_trigger_type(d->irq); +- if (irq_flags != IRQ_TYPE_NONE) +- type = irq_flags; +- + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_RISING: + pin_reg &= ~BIT(LEVEL_TRIG_OFF); + |