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| author | Felix Salfelder | 2023-06-10 00:00:00 +0000 |
|---|---|---|
| committer | Felix Salfelder | 2023-06-10 00:00:00 +0000 |
| commit | 9d6284c38d05a90ae6304306df22fc0fe4a1304d (patch) | |
| tree | 3032026c33b8d1cc88c56c0e1b8c2a3e6561b12d | |
| parent | 43c2faabb1df2d6ff71ce4329699971d3cc66f73 (diff) | |
| download | aur-gnucap-modelgen-verilog-git.tar.gz | |
remove hyphen from pkgver
| -rw-r--r-- | .SRCINFO | 2 | ||||
| -rw-r--r-- | PKGBUILD | 2 |
2 files changed, 2 insertions, 2 deletions
@@ -1,7 +1,7 @@ pkgbase = gnucap-modelgen-verilog-git pkgdesc = Verilog-AMS for Gnucap - pkgver = develop-git + pkgver = develop pkgrel = 1 url = http://gnucap.org/ arch = i686 @@ -2,7 +2,7 @@ _pkgname=gnucap-modelgen-verilog pkgname=$_pkgname-git -pkgver=develop-git +pkgver=develop pkgrel=1 pkgdesc="Verilog model generator for Gnucap" arch=('i686' 'x86_64') |