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authoregnappahz2021-06-26 15:17:32 +0200
committeregnappahz2021-06-26 15:17:32 +0200
commitf1083ea7eb36866419b8ea2567814bc0ffddaf72 (patch)
tree8c14c1cc944445281fb49ea887f7ff1891d5ce4b
parent304fbb632acd7c10f388aeee866b9a17503b88d4 (diff)
downloadaur-f1083ea7eb36866419b8ea2567814bc0ffddaf72.tar.gz
reverted doorbell commits for idlebug
-rw-r--r--.SRCINFO4
-rw-r--r--PKGBUILD6
-rw-r--r--idlebug.patch50
3 files changed, 58 insertions, 2 deletions
diff --git a/.SRCINFO b/.SRCINFO
index ef128a7b5a7..aaf39f05621 100644
--- a/.SRCINFO
+++ b/.SRCINFO
@@ -1,6 +1,6 @@
pkgbase = linux-amd-znver2
pkgver = 5.12.v.13
- pkgrel = 1
+ pkgrel = 2
url = https://www.kernel.org/
arch = x86_64
license = GPL2
@@ -19,11 +19,13 @@ pkgbase = linux-amd-znver2
source = linux-amd-znver2.preset
source = linux.install
source = 5010_enable-cpu-optimizations-universal.patch
+ source = idlebug.patch
sha256sums = SKIP
sha256sums = 4b876e8766174d8c0b62faac1709208ee38f82971cbe5bd4590ced7ebc51d8fb
sha256sums = 60c6ba602443e94a9eba3aeee9d194027d69bffaa428c6d055348ebf03681b5c
sha256sums = d590e751ab4cf424b78fd0d57e53d187f07401a68c8b468d17a5f39a337dacf0
sha256sums = 9083b94bf9f547cceeed9fe2f37fb201e42d5b00734a86e4ea528447a59d4b9a
+ sha256sums = c37e1db6b42cdb0e954c250754e707316172633322ddc9c8e05abaecc3c678a3
pkgname = linux-amd-znver2
pkgdesc = Linux kernel aimed at the znver2 AMD Ryzen CPU based hardware
diff --git a/PKGBUILD b/PKGBUILD
index 8bf9d288ed0..6997274af20 100644
--- a/PKGBUILD
+++ b/PKGBUILD
@@ -4,7 +4,7 @@ pkgbase=linux-amd-znver2
_srcname=linux
gitver=v5.12.13
pkgver=5.12.v.13
-pkgrel=1
+pkgrel=2
arch=('x86_64')
url="https://www.kernel.org/"
license=('GPL2')
@@ -20,6 +20,8 @@ source=("git+https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git#ta
'linux.install'
# patch from our gentoo overlords
'5010_enable-cpu-optimizations-universal.patch'
+ # revert for idlebug
+ 'idlebug.patch'
)
sha256sums=('SKIP'
#config.x86_64
@@ -30,6 +32,8 @@ sha256sums=('SKIP'
'd590e751ab4cf424b78fd0d57e53d187f07401a68c8b468d17a5f39a337dacf0'
#gentoopatch
'9083b94bf9f547cceeed9fe2f37fb201e42d5b00734a86e4ea528447a59d4b9a'
+ #idlebug file
+ 'c37e1db6b42cdb0e954c250754e707316172633322ddc9c8e05abaecc3c678a3'
)
_kernelname=${pkgbase#linux}
diff --git a/idlebug.patch b/idlebug.patch
new file mode 100644
index 00000000000..79794718bcf
--- /dev/null
+++ b/idlebug.patch
@@ -0,0 +1,50 @@
+From d71e282a6611b9e1742386a2a4764fb766bc970b Mon Sep 17 00:00:00 2001
+From: egnappahz <egnappah@gmail.com>
+Date: Thu, 24 Jun 2021 12:46:46 +0200
+Subject: [PATCH] Revert for sienna idle bug
+
+Signed-off-by: egnappahz <egnappah@gmail.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +-----
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 +-----
+ 2 files changed, 2 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 72d23651501d..2342c5d216f9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -6769,12 +6769,8 @@ static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
+ if (ring->use_doorbell) {
+ WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
+ (adev->doorbell_index.kiq * 2) << 2);
+- /* If GC has entered CGPG, ringing doorbell > first page doesn't
+- * wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround
+- * this issue.
+- */
+ WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
+- (adev->doorbell.size - 4));
++ (adev->doorbell_index.userqueue_end * 2) << 2);
+ }
+
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 1fdfb7783404..d2c020a91c0b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -3623,12 +3623,8 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
+ if (ring->use_doorbell) {
+ WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
+ (adev->doorbell_index.kiq * 2) << 2);
+- /* If GC has entered CGPG, ringing doorbell > first page doesn't
+- * wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround
+- * this issue.
+- */
+ WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
+- (adev->doorbell.size - 4));
++ (adev->doorbell_index.userqueue_end * 2) << 2);
+ }
+
+ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
+--
+2.32.0
+