diff options
| author | dragonn | 2021-06-27 21:00:11 +0200 |
|---|---|---|
| committer | dragonn | 2021-06-29 16:32:59 +0200 |
| commit | d6d88058ef69ca3e422b034c58843de1cdca2171 (patch) | |
| tree | 5cb86c6e53c0eec2abe6adcdfcd1ad035e6ba2f1 | |
| parent | b8231749cf473fc099b7ac604110df5f988418ca (diff) | |
| download | aur-d6d88058ef69ca3e422b034c58843de1cdca2171.tar.gz | |
fix low memory reserve
23 files changed, 2780 insertions, 80 deletions
@@ -1,7 +1,7 @@ pkgbase = linux-g14 pkgdesc = Linux - pkgver = 5.12.13.arch1 - pkgrel = 1 + pkgver = 5.12.13.arch2 + pkgrel = 4 url = https://lab.retarded.farm/zappel/asus-rog-zephyrus-g14/ arch = x86_64 license = GPL2 @@ -19,13 +19,32 @@ pkgbase = linux-g14 source = archlinux-linux::git+https://github.com/archlinux/linux?signed#tag=v5.12.13-arch1 source = config source = choose-gcc-optimization.sh + source = sys-kernel_arch-sources-g14_files-0001-revert-reserve-x86-low-memory.patch source = sys-kernel_arch-sources-g14_files-0003-flow-x13-sound.patch source = sys-kernel_arch-sources-g14_files-0004-5.8+--more-uarches-for-kernel.patch::https://raw.githubusercontent.com/graysky2/kernel_compiler_patch/master/more-uarches-for-kernel-5.8+.patch source = sys-kernel_arch-sources-g14_files-0005-lru-multi-generational.patch - source = https://gitlab.com/asus-linux/fedora-kernel/-/archive/19ba47dedb21773e0338321928a8580e214409fb/fedora-kernel-19ba47dedb21773e0338321928a8580e214409fb.zip + source = https://gitlab.com/asus-linux/fedora-kernel/-/archive/91f97d88231152006764d3c50cc52ddbb508529f/fedora-kernel-91f97d88231152006764d3c50cc52ddbb508529f.zip source = sys-kernel_arch-sources-g14_files-0012-acpi-1of2-turn-off-unused.patch::https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git/patch/?id=4b9ee772eaa82188b0eb8e05bdd1707c2a992004 - source = sys-kernel_arch-sources-g14_files-0013-acpi-2of2-turn-off-unconditionally.patch::https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git/patch/?id=7e4fdeafa61f2b653fcf9678f09935e55756aed2 source = sys-kernel_arch-sources-g14_files-0014-acpi_unused-v2.patch + source = sys-kernel_arch-sources-g14_files-0015-revert-4cbbe34807938e6e494e535a68d5ff64edac3f20.patch + source = sys-kernel_arch-sources-g14_files-0016-revert-1c0b0efd148d5b24c4932ddb3fa03c8edd6097b3.patch + source = sys-kernel_arch-sources-g14_files-0017-5.14-ACPI-processor-idle-Fix-up-C-state-latency-if-not-ordered.patch + source = sys-kernel_arch-sources-g14_files-0018-PCI-quirks-Quirk-PCI-d3hot-delay-for-AMD-xhci.patch + source = sys-kernel_arch-sources-g14_files-0019-5.14-nvme-pci-look-for-StorageD3Enable-on-companion-ACPI-device.patch + source = sys-kernel_arch-sources-g14_files-0020-5.14-ACPI-Check-StorageD3Enable_DSD-property-in-AHCI-mode.patch + source = sys-kernel_arch-sources-g14_files-0021-5.14-ACPI-Add-quirks-for-AMD-Renoir+Lucienne-CPUs-to-force-the-D3-hint.patch + source = sys-kernel_arch-sources-g14_files-0022-5.14-ACPI-PM-s2idle-Add-missing-LPS0-functions-for-AMD.patch + source = sys-kernel_arch-sources-g14_files-0023-5.14-1of5-ACPI-PM-s2idle-Use-correct-revision-id.patch + source = sys-kernel_arch-sources-g14_files-0024-5.14-2of5-ACPI-PM-s2idle-Refactor-common-code.patch + source = sys-kernel_arch-sources-g14_files-0025-5.14-3of5-ACPI-PM-s2idle-Add-support-for-multiple-func-mask.patch + source = sys-kernel_arch-sources-g14_files-0026-5.14-4of5-ACPI-PM-s2idle-Add-support-for-new-Microsoft-UUID.patch + source = sys-kernel_arch-sources-g14_files-0027-5.14-5of5-ACPI-PM-s2idle-Adjust-behavior-for-field-problems-on-AMD-systems.patch + source = sys-kernel_arch-sources-g14_files-0028-platform-x86-amd-pmc-Fix-command-completion-code.patch + source = sys-kernel_arch-sources-g14_files-0029-platform-x86-amd-pmc-Fix-SMU-firmware-reporting-mechanism.patch + source = sys-kernel_arch-sources-g14_files-0030-platform-x86-amd-pmc-Add-support-for-logging-SMU-metrics.patch + source = sys-kernel_arch-sources-g14_files-0031-platform-x86-amd-pmc-Add-support-for-s0ix-counters.patch + source = sys-kernel_arch-sources-g14_files-0032-platform-x86-amd-pmc-Add-support-for-ACPI-ID-AMDI0006.patch + source = sys-kernel_arch-sources-g14_files-0033-platform-x86-amd-pmc-Add-new-acpi-for-future-PMC.patch validpgpkeys = ABAF11C65A2970B130ABE3C479BE3E4300411886 validpgpkeys = 647F28654894E3BD457199BE38DBBDC86092693E validpgpkeys = A2FF3A36AAA56654109064AB19802F8B0D70FC30 @@ -35,10 +54,28 @@ pkgbase = linux-g14 sha256sums = 4a9e44dfbc7e9574ae86cf53a896b6c67f03b224e90e18982dfb0e4ba02a6c1b sha256sums = fa6cee9527d8e963d3398085d1862edc509a52e4540baec463edb8a9dd95bee0 sha256sums = b9e4b11f6ca413fa7fcd1d810215bf3a36e69eedc4570f4209f7c1957083b2f3 - sha256sums = e0977edd01cc1dd9cc8720d3ee2170bb3ba1e8a37eb77fe1c76c0852d580af4a + sha256sums = f94b12f56e99ebfc87014f9570a987bca7b50400c412ddbbb7035d73c5d8c668 sha256sums = 5af4796400245fec2e84d6e3f847b8896600558aa85f5e9c4706dd50994a9802 - sha256sums = 9cf7519ee1a0544f431c9fe57735aae7b9d150e62abed318837befc3b6af7c5f - sha256sums = 87f133d34d84b8b34b0dad2bfd4cbbd557c6018f413a1852120d650273c628fb + sha256sums = 4c1e9ec4402161ac93bb88595840ea5c5ac0c2cb75d06b01170a3ee4fc1f8907 + sha256sums = e03b26bbfd6d7a3fffa290346f96e6f4376e09ac3a76bc658eaab0cd8b486ddd + sha256sums = 3cff17ff6953eef7c17d066d56e510713f2692efac90c61b748d9d38b318f5c8 + sha256sums = b4a563ef30f86b9af0932c00bb3422b95eedbda1ff40a1a725c22a0ae9ab7084 + sha256sums = dab4db308ede1aa35166f31671572eeccf0e7637b3218ce3ae519c2705934f79 + sha256sums = 9e83c46bed9059ba78df6c17a2f7c80a1cdb6efbdf64ec643f68573ede891b95 + sha256sums = 6c5538dc21a139a4475af6c1acc5d2761923173992568f7c159db971ff3167cd + sha256sums = 84119c2d2beb6d7dc56389f2d1be8052b4fd23022e15edd86ee59130adcd9ab7 + sha256sums = 478e908f89ae413c650116681710aed3e974384a2ed5e97be3755189688e5415 + sha256sums = 1c58e4fd62cb7034e4fe834b55ffd8e183926571d4056b150bab5725f0ac5e29 + sha256sums = 50f6e6a3371eaedd3b649a25c5044e6359853c2e3836a6af683a906abb973fba + sha256sums = 23ada5c29c415c0bb8d14cff213c697c649b438d7427a67a15b0b3f65c66aa6f + sha256sums = 9ea5d38eea3809e85c6f3165f4b410ee53f0fdb813cbbf229e18a87e79c13ad5 + sha256sums = d6113df716cb81f78abc58405648d90f8497e29d79f5fd403eda36af867b50f3 + sha256sums = bc783b22ab5ab75dc28ae10519a9d6da23d80ee291812115555945acd280edc5 + sha256sums = dce87ca35886d075554fe6d8831075237d80526e078431165d2ec0d1a9630c7b + sha256sums = ad9f485bb262bb1156da57698ccab5a6b8d8ca34b6ae8a185dcd014a34c69557 + sha256sums = 3e8c51aff84b6f12e6bc61057982befd82415626fe379e83271ddeb1a9628734 + sha256sums = bd975ab32d6490a4231d6ce4fab0343698b28407799bdaec133671e9fd778eb5 + sha256sums = ae66bbed96b5946b5a20d902bc0282c7dd172650812114b24429f40d5ba225bb pkgname = linux-g14 pkgdesc = The Linux kernel and modules @@ -1,42 +1,62 @@ # Maintainer: Jan Alexander Steffens (heftig) <jan.steffens@gmail.com> pkgbase=linux-g14 -pkgver=5.12.13.arch1 -pkgrel=1 +pkgver=5.12.13.arch2 +_tagver=5.12.13.arch1 +pkgrel=4 pkgdesc='Linux' -_srctag=v${pkgver%.*}-${pkgver##*.} +#_srctag=v${pkgver%.*}-${pkgver##*.} +_srctag=v${_tagver%.*}-${_tagver##*.} url="https://lab.retarded.farm/zappel/asus-rog-zephyrus-g14/" arch=(x86_64) license=(GPL2) makedepends=( - bc kmod libelf pahole cpio tar xz - xmlto - git - "gcc>=11.0" + bc kmod libelf pahole cpio tar xz + xmlto + git + "gcc>=11.0" ) options=('!strip') _srcname=archlinux-linux -_fedora_kernel_commit_id=19ba47dedb21773e0338321928a8580e214409fb +_fedora_kernel_commit_id=91f97d88231152006764d3c50cc52ddbb508529f source=( "$_srcname::git+https://github.com/archlinux/linux?signed#tag=$_srctag" config # the main kernel config file - "choose-gcc-optimization.sh" - #"sys-kernel_arch-sources-g14_files_0001-HID-asus-Filter-keyboard-EC-for-old-ROG-keyboard.patch" - #"sys-kernel_arch-sources-g14_files-0002-acpi_unused.patch" - "sys-kernel_arch-sources-g14_files-0003-flow-x13-sound.patch" + "choose-gcc-optimization.sh" + + #"sys-kernel_arch-sources-g14_files-0000-revert-arch1-to-upstream-arch0.patch" + "sys-kernel_arch-sources-g14_files-0001-revert-reserve-x86-low-memory.patch" + "sys-kernel_arch-sources-g14_files-0003-flow-x13-sound.patch" "sys-kernel_arch-sources-g14_files-0004-5.8+--more-uarches-for-kernel.patch"::"https://raw.githubusercontent.com/graysky2/kernel_compiler_patch/master/more-uarches-for-kernel-5.8+.patch" - "sys-kernel_arch-sources-g14_files-0005-lru-multi-generational.patch" - #"sys-kernel_arch-sources-g14_files-0006-ACPI-PM-s2idle-Add-missing-LPS0-functions.patch" - #"sys-kernel_arch-sources-g14_files-0007-ACPI-processor-idle-Fix-up-C-state-latency.patch" - #"sys-kernel_arch-sources-g14_files-0008-NVMe-set-some-AMD-PCIe-downstream-storage-device-to-D3-for-s2idle.patch" - #"sys-kernel_arch-sources-g14_files-0009-PCI-quirks-Quirk-PCI-d3hot-delay.patch" - #"sys-kernel_arch-sources-g14_files-0010-platform-x86-force-LPS0-functions-for-AMD.patch" - #"sys-kernel_arch-sources-g14_files-0011-USB-pci-quirks-disable-D3cold-on-s2idle-Renoire.patch" - - "https://gitlab.com/asus-linux/fedora-kernel/-/archive/$_fedora_kernel_commit_id/fedora-kernel-$_fedora_kernel_commit_id.zip" - "sys-kernel_arch-sources-g14_files-0012-acpi-1of2-turn-off-unused.patch"::"https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git/patch/?id=4b9ee772eaa82188b0eb8e05bdd1707c2a992004" - "sys-kernel_arch-sources-g14_files-0013-acpi-2of2-turn-off-unconditionally.patch"::"https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git/patch/?id=7e4fdeafa61f2b653fcf9678f09935e55756aed2" - "sys-kernel_arch-sources-g14_files-0014-acpi_unused-v2.patch" + "sys-kernel_arch-sources-g14_files-0005-lru-multi-generational.patch" + + "https://gitlab.com/asus-linux/fedora-kernel/-/archive/$_fedora_kernel_commit_id/fedora-kernel-$_fedora_kernel_commit_id.zip" + "sys-kernel_arch-sources-g14_files-0012-acpi-1of2-turn-off-unused.patch"::"https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git/patch/?id=4b9ee772eaa82188b0eb8e05bdd1707c2a992004" + #the second patch in this sequence (2of2) was rejected upstream as it causes problems for some machines + #"sys-kernel_arch-sources-g14_files-0013-acpi-2of2-turn-off-unconditionally.patch"::"https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git/patch/?id=7e4fdeafa61f2b653fcf9678f09935e55756aed2" + "sys-kernel_arch-sources-g14_files-0014-acpi_unused-v2.patch" + + "sys-kernel_arch-sources-g14_files-0015-revert-4cbbe34807938e6e494e535a68d5ff64edac3f20.patch" + "sys-kernel_arch-sources-g14_files-0016-revert-1c0b0efd148d5b24c4932ddb3fa03c8edd6097b3.patch" + + "sys-kernel_arch-sources-g14_files-0017-5.14-ACPI-processor-idle-Fix-up-C-state-latency-if-not-ordered.patch" + "sys-kernel_arch-sources-g14_files-0018-PCI-quirks-Quirk-PCI-d3hot-delay-for-AMD-xhci.patch" + "sys-kernel_arch-sources-g14_files-0019-5.14-nvme-pci-look-for-StorageD3Enable-on-companion-ACPI-device.patch" + "sys-kernel_arch-sources-g14_files-0020-5.14-ACPI-Check-StorageD3Enable_DSD-property-in-AHCI-mode.patch" + "sys-kernel_arch-sources-g14_files-0021-5.14-ACPI-Add-quirks-for-AMD-Renoir+Lucienne-CPUs-to-force-the-D3-hint.patch" + "sys-kernel_arch-sources-g14_files-0022-5.14-ACPI-PM-s2idle-Add-missing-LPS0-functions-for-AMD.patch" + "sys-kernel_arch-sources-g14_files-0023-5.14-1of5-ACPI-PM-s2idle-Use-correct-revision-id.patch" + "sys-kernel_arch-sources-g14_files-0024-5.14-2of5-ACPI-PM-s2idle-Refactor-common-code.patch" + "sys-kernel_arch-sources-g14_files-0025-5.14-3of5-ACPI-PM-s2idle-Add-support-for-multiple-func-mask.patch" + "sys-kernel_arch-sources-g14_files-0026-5.14-4of5-ACPI-PM-s2idle-Add-support-for-new-Microsoft-UUID.patch" + "sys-kernel_arch-sources-g14_files-0027-5.14-5of5-ACPI-PM-s2idle-Adjust-behavior-for-field-problems-on-AMD-systems.patch" + + "sys-kernel_arch-sources-g14_files-0028-platform-x86-amd-pmc-Fix-command-completion-code.patch" + "sys-kernel_arch-sources-g14_files-0029-platform-x86-amd-pmc-Fix-SMU-firmware-reporting-mechanism.patch" + "sys-kernel_arch-sources-g14_files-0030-platform-x86-amd-pmc-Add-support-for-logging-SMU-metrics.patch" + "sys-kernel_arch-sources-g14_files-0031-platform-x86-amd-pmc-Add-support-for-s0ix-counters.patch" + "sys-kernel_arch-sources-g14_files-0032-platform-x86-amd-pmc-Add-support-for-ACPI-ID-AMDI0006.patch" + "sys-kernel_arch-sources-g14_files-0033-platform-x86-amd-pmc-Add-new-acpi-for-future-PMC.patch" ) validpgpkeys=( @@ -51,10 +71,28 @@ sha256sums=('SKIP' '4a9e44dfbc7e9574ae86cf53a896b6c67f03b224e90e18982dfb0e4ba02a6c1b' 'fa6cee9527d8e963d3398085d1862edc509a52e4540baec463edb8a9dd95bee0' 'b9e4b11f6ca413fa7fcd1d810215bf3a36e69eedc4570f4209f7c1957083b2f3' - 'e0977edd01cc1dd9cc8720d3ee2170bb3ba1e8a37eb77fe1c76c0852d580af4a' + 'f94b12f56e99ebfc87014f9570a987bca7b50400c412ddbbb7035d73c5d8c668' '5af4796400245fec2e84d6e3f847b8896600558aa85f5e9c4706dd50994a9802' - '9cf7519ee1a0544f431c9fe57735aae7b9d150e62abed318837befc3b6af7c5f' - '87f133d34d84b8b34b0dad2bfd4cbbd557c6018f413a1852120d650273c628fb') + '4c1e9ec4402161ac93bb88595840ea5c5ac0c2cb75d06b01170a3ee4fc1f8907' + 'e03b26bbfd6d7a3fffa290346f96e6f4376e09ac3a76bc658eaab0cd8b486ddd' + '3cff17ff6953eef7c17d066d56e510713f2692efac90c61b748d9d38b318f5c8' + 'b4a563ef30f86b9af0932c00bb3422b95eedbda1ff40a1a725c22a0ae9ab7084' + 'dab4db308ede1aa35166f31671572eeccf0e7637b3218ce3ae519c2705934f79' + '9e83c46bed9059ba78df6c17a2f7c80a1cdb6efbdf64ec643f68573ede891b95' + '6c5538dc21a139a4475af6c1acc5d2761923173992568f7c159db971ff3167cd' + '84119c2d2beb6d7dc56389f2d1be8052b4fd23022e15edd86ee59130adcd9ab7' + '478e908f89ae413c650116681710aed3e974384a2ed5e97be3755189688e5415' + '1c58e4fd62cb7034e4fe834b55ffd8e183926571d4056b150bab5725f0ac5e29' + '50f6e6a3371eaedd3b649a25c5044e6359853c2e3836a6af683a906abb973fba' + '23ada5c29c415c0bb8d14cff213c697c649b438d7427a67a15b0b3f65c66aa6f' + '9ea5d38eea3809e85c6f3165f4b410ee53f0fdb813cbbf229e18a87e79c13ad5' + 'd6113df716cb81f78abc58405648d90f8497e29d79f5fd403eda36af867b50f3' + 'bc783b22ab5ab75dc28ae10519a9d6da23d80ee291812115555945acd280edc5' + 'dce87ca35886d075554fe6d8831075237d80526e078431165d2ec0d1a9630c7b' + 'ad9f485bb262bb1156da57698ccab5a6b8d8ca34b6ae8a185dcd014a34c69557' + '3e8c51aff84b6f12e6bc61057982befd82415626fe379e83271ddeb1a9628734' + 'bd975ab32d6490a4231d6ce4fab0343698b28407799bdaec133671e9fd778eb5' + 'ae66bbed96b5946b5a20d902bc0282c7dd172650812114b24429f40d5ba225bb') # notable microarch levels: # @@ -73,28 +111,37 @@ _fedora_kernel_patch_skip_list=( # use plain file names or bash glob syntax, ** don't quote globs ** # multi-select and ranges examples - #00{03,05,08}-drm-amdgpu*.patch - #00{01..12}-drm-amdgpu*.patch + # 00{03,05,08}-drm-amdgpu*.patch + # 00{01..12}-drm-amdgpu*.patch "linux-kernel-test.patch" # test patch, please ignore patch-*-redhat.patch # wildcard match any redhat patch version - 00{01..12}-drm-amdgpu*.patch # upstreamed in 5.12 + # 00{01..12}-drm-amdgpu*.patch # upstreamed in 5.12 # upstreamed "0001-HID-asus-Filter-keyboard-EC-for-old-ROG-keyboard.patch" "0001-ALSA-hda-realtek-GA503-use-same-quirks-as-GA401.patch" - - # patch broken in 5.12.4, updated and included in package sources "0001-Add-jack-toggle-support-for-headphones-on-Asus-ROG-Z.patch" - - # applied a new version above in sources + "0001-HID-asus-filter-G713-G733-key-event-to-prevent-shutd.patch" + + # filter out suspend patches, we'll use upstream directly + "0001-ACPI-processor-idle-Fix-up-C-state-latency-if-not-ordered.patch" + "0002-v5-usb-pci-quirks-disable-D3cold-on-xhci-suspend-for-s2idle-on-AMD-Renoir.diff" + "0003-PCI-quirks-Quirk-PCI-d3hot-delay-for-AMD-xhci.diff" + "0004-nvme-pci_look_for_StorageD3Enable_on_companion_ACPI_device_instead.patch" + "0005-v5-1-2-acpi-PM-Move-check-for-_DSD-StorageD3Enable-property-to-acpi.diff" + "0006-v5-2-2-acpi-PM-Add-quirks-for-AMD-Renoir-Lucienne-CPUs-to-force-the-D3-hint.diff" + "0007-ACPI_PM_s2idle_Add_missing_LPS0_functions_for_AMD.patch" + "0008-2-2-V2-platform-x86-force-LPS0-functions-for-AMD.diff" + + # filter suspend patches from 'rog' branch + "0002-drm-amdgpu-drop-extraneous-hw_status-update.patch" "0013-ACPI-idle-override-and-update-c-state-latency-when-n.patch" - - # applied a new version above in sources "0014-usb-pci-quirks-disable-D3cold-on-AMD-xhci-suspend-fo.patch" - - # applied above - "0001-GV301QH-Flow-X13-Audio.patch" + "0015-PCI-quirks-Quirk-PCI-d3hot-delay-for-AMD-xhci.patch" + "0016-nvme-put-some-AMD-PCIE-downstream-NVME-device-to-sim.patch" + "0017-platform-x86-Add-missing-LPS0-functions-for-AMD.patch" + "0018-platform-x86-force-LPS0-functions-for-AMD.patch" ) export KBUILD_BUILD_HOST=archlinux @@ -108,9 +155,10 @@ _fedora_patch_in_skip_list() { prepare() { cd $_srcname - rm Documentation/vm/multigen_lru.rst || echo 0 + echo "Setting version..." scripts/setlocalversion --save-scmversion + #echo '' >.scmversion # HACK: maybe needed echo "-$pkgrel" > localversion.99-pkgrel echo "${pkgbase#linux}" > localversion.20-pkgname diff --git a/sys-kernel_arch-sources-g14_files-0001-revert-reserve-x86-low-memory.patch b/sys-kernel_arch-sources-g14_files-0001-revert-reserve-x86-low-memory.patch new file mode 100644 index 000000000000..f3eb8cab4d54 --- /dev/null +++ b/sys-kernel_arch-sources-g14_files-0001-revert-reserve-x86-low-memory.patch @@ -0,0 +1,370 @@ +diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt +index 479cc44cc4e2..835f810f2f26 100644 +--- a/Documentation/admin-guide/kernel-parameters.txt ++++ b/Documentation/admin-guide/kernel-parameters.txt +@@ -4623,6 +4623,11 @@ + Reserves a hole at the top of the kernel virtual + address space. + ++ reservelow= [X86] ++ Format: nn[K] ++ Set the amount of memory to reserve for BIOS at ++ the bottom of the address space. ++ + reset_devices [KNL] Force drivers to reset the underlying device + during initialization. + +diff --git a/Makefile b/Makefile +index 30e69fd83264..d2fe36db78ae 100644 +--- a/Makefile ++++ b/Makefile +@@ -2,7 +2,7 @@ + VERSION = 5 + PATCHLEVEL = 12 + SUBLEVEL = 13 +-EXTRAVERSION = -arch1 ++EXTRAVERSION = + NAME = Frozen Wasteland + + # *DOCUMENTATION* +diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig +index fc91be3b1bd1..861b1b794697 100644 +--- a/arch/x86/Kconfig ++++ b/arch/x86/Kconfig +@@ -1688,6 +1688,35 @@ config X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK + Set whether the default state of memory_corruption_check is + on or off. + ++config X86_RESERVE_LOW ++ int "Amount of low memory, in kilobytes, to reserve for the BIOS" ++ default 64 ++ range 4 640 ++ help ++ Specify the amount of low memory to reserve for the BIOS. ++ ++ The first page contains BIOS data structures that the kernel ++ must not use, so that page must always be reserved. ++ ++ By default we reserve the first 64K of physical RAM, as a ++ number of BIOSes are known to corrupt that memory range ++ during events such as suspend/resume or monitor cable ++ insertion, so it must not be used by the kernel. ++ ++ You can set this to 4 if you are absolutely sure that you ++ trust the BIOS to get all its memory reservations and usages ++ right. If you know your BIOS have problems beyond the ++ default 64K area, you can set this to 640 to avoid using the ++ entire low memory range. ++ ++ If you have doubts about the BIOS (e.g. suspend/resume does ++ not work or there's kernel crashes after certain hardware ++ hotplug events) then you might want to enable ++ X86_CHECK_BIOS_CORRUPTION=y to allow the kernel to check ++ typical corruption patterns. ++ ++ Leave this to the default value of 64 if you are unsure. ++ + config MATH_EMULATION + bool + depends on MODIFY_LDT_SYSCALL +diff --git a/arch/x86/include/asm/crash.h b/arch/x86/include/asm/crash.h +index 8b6bd63530dc..f58de66091e5 100644 +--- a/arch/x86/include/asm/crash.h ++++ b/arch/x86/include/asm/crash.h +@@ -9,4 +9,10 @@ int crash_setup_memmap_entries(struct kimage *image, + struct boot_params *params); + void crash_smp_send_stop(void); + ++#ifdef CONFIG_KEXEC_CORE ++void __init crash_reserve_low_1M(void); ++#else ++static inline void __init crash_reserve_low_1M(void) { } ++#endif ++ + #endif /* _ASM_X86_CRASH_H */ +diff --git a/arch/x86/kernel/crash.c b/arch/x86/kernel/crash.c +index e0b8d9662da5..b1deacbeb266 100644 +--- a/arch/x86/kernel/crash.c ++++ b/arch/x86/kernel/crash.c +@@ -70,6 +70,19 @@ static inline void cpu_crash_vmclear_loaded_vmcss(void) + rcu_read_unlock(); + } + ++/* ++ * When the crashkernel option is specified, only use the low ++ * 1M for the real mode trampoline. ++ */ ++void __init crash_reserve_low_1M(void) ++{ ++ if (cmdline_find_option(boot_command_line, "crashkernel", NULL, 0) < 0) ++ return; ++ ++ memblock_reserve(0, 1<<20); ++ pr_info("Reserving the low 1M of memory for crashkernel\n"); ++} ++ + #if defined(CONFIG_SMP) && defined(CONFIG_X86_LOCAL_APIC) + + static void kdump_nmi_callback(int cpu, struct pt_regs *regs) +diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c +index fbda4bbf75c1..e79f21d13a0d 100644 +--- a/arch/x86/kernel/setup.c ++++ b/arch/x86/kernel/setup.c +@@ -634,16 +634,11 @@ static void __init trim_snb_memory(void) + printk(KERN_DEBUG "reserving inaccessible SNB gfx pages\n"); + + /* +- * SandyBridge integrated graphics devices have a bug that prevents +- * them from accessing certain memory ranges, namely anything below +- * 1M and in the pages listed in bad_pages[] above. +- * +- * To avoid these pages being ever accessed by SNB gfx devices reserve +- * bad_pages that have not already been reserved at boot time. +- * All memory below the 1 MB mark is anyway reserved later during +- * setup_arch(), so there is no need to reserve it here. ++ * Reserve all memory below the 1 MB mark that has not ++ * already been reserved. + */ +- ++ memblock_reserve(0, 1<<20); ++ + for (i = 0; i < ARRAY_SIZE(bad_pages); i++) { + if (memblock_reserve(bad_pages[i], PAGE_SIZE)) + printk(KERN_WARNING "failed to reserve 0x%08lx\n", +@@ -651,6 +646,18 @@ static void __init trim_snb_memory(void) + } + } + ++/* ++ * Here we put platform-specific memory range workarounds, i.e. ++ * memory known to be corrupt or otherwise in need to be reserved on ++ * specific platforms. ++ * ++ * If this gets used more widely it could use a real dispatch mechanism. ++ */ ++static void __init trim_platform_memory_ranges(void) ++{ ++ trim_snb_memory(); ++} ++ + static void __init trim_bios_range(void) + { + /* +@@ -695,42 +702,35 @@ static void __init e820_add_kernel_range(void) + e820__range_add(start, size, E820_TYPE_RAM); + } + +-static void __init early_reserve_memory(void) ++static unsigned reserve_low = CONFIG_X86_RESERVE_LOW << 10; ++ ++static int __init parse_reservelow(char *p) + { +- /* +- * Reserve the memory occupied by the kernel between _text and +- * __end_of_kernel_reserve symbols. Any kernel sections after the +- * __end_of_kernel_reserve symbol must be explicitly reserved with a +- * separate memblock_reserve() or they will be discarded. +- */ +- memblock_reserve(__pa_symbol(_text), +- (unsigned long)__end_of_kernel_reserve - (unsigned long)_text); ++ unsigned long long size; + +- /* +- * The first 4Kb of memory is a BIOS owned area, but generally it is +- * not listed as such in the E820 table. +- * +- * Reserve the first 64K of memory since some BIOSes are known to +- * corrupt low memory. After the real mode trampoline is allocated the +- * rest of the memory below 640k is reserved. +- * +- * In addition, make sure page 0 is always reserved because on +- * systems with L1TF its contents can be leaked to user processes. +- */ +- memblock_reserve(0, SZ_64K); ++ if (!p) ++ return -EINVAL; + +- early_reserve_initrd(); ++ size = memparse(p, &p); + +- if (efi_enabled(EFI_BOOT)) +- efi_memblock_x86_reserve_range(); ++ if (size < 4096) ++ size = 4096; + +- memblock_x86_reserve_range_setup_data(); ++ if (size > 640*1024) ++ size = 640*1024; + +- reserve_ibft_region(); +- reserve_bios_regions(); +- trim_snb_memory(); ++ reserve_low = size; ++ ++ return 0; + } + ++early_param("reservelow", parse_reservelow); ++ ++static void __init trim_low_memory_range(void) ++{ ++ memblock_reserve(0, ALIGN(reserve_low, PAGE_SIZE)); ++} ++ + /* + * Dump out kernel offset information on panic. + */ +@@ -765,6 +765,29 @@ dump_kernel_offset(struct notifier_block *self, unsigned long v, void *p) + + void __init setup_arch(char **cmdline_p) + { ++ /* ++ * Reserve the memory occupied by the kernel between _text and ++ * __end_of_kernel_reserve symbols. Any kernel sections after the ++ * __end_of_kernel_reserve symbol must be explicitly reserved with a ++ * separate memblock_reserve() or they will be discarded. ++ */ ++ memblock_reserve(__pa_symbol(_text), ++ (unsigned long)__end_of_kernel_reserve - (unsigned long)_text); ++ ++ /* ++ * Make sure page 0 is always reserved because on systems with ++ * L1TF its contents can be leaked to user processes. ++ */ ++ memblock_reserve(0, PAGE_SIZE); ++ ++ early_reserve_initrd(); ++ ++ /* ++ * At this point everything still needed from the boot loader ++ * or BIOS or kernel text should be early reserved or marked not ++ * RAM in e820. All other memory is free game. ++ */ ++ + #ifdef CONFIG_X86_32 + memcpy(&boot_cpu_data, &new_cpu_data, sizeof(new_cpu_data)); + +@@ -888,18 +911,8 @@ void __init setup_arch(char **cmdline_p) + + parse_early_param(); + +- /* +- * Do some memory reservations *before* memory is added to +- * memblock, so memblock allocations won't overwrite it. +- * Do it after early param, so we could get (unlikely) panic from +- * serial. +- * +- * After this point everything still needed from the boot loader or +- * firmware or kernel text should be early reserved or marked not +- * RAM in e820. All other memory is free game. +- */ +- early_reserve_memory(); +- ++ if (efi_enabled(EFI_BOOT)) ++ efi_memblock_x86_reserve_range(); + #ifdef CONFIG_MEMORY_HOTPLUG + /* + * Memory used by the kernel cannot be hot-removed because Linux +@@ -926,6 +939,9 @@ void __init setup_arch(char **cmdline_p) + + x86_report_nx(); + ++ /* after early param, so could get panic from serial */ ++ memblock_x86_reserve_range_setup_data(); ++ + if (acpi_mps_check()) { + #ifdef CONFIG_X86_LOCAL_APIC + disable_apic = 1; +@@ -1017,6 +1033,8 @@ void __init setup_arch(char **cmdline_p) + */ + find_smp_config(); + ++ reserve_ibft_region(); ++ + early_alloc_pgt_buf(); + + /* +@@ -1037,6 +1055,8 @@ void __init setup_arch(char **cmdline_p) + */ + sev_setup_arch(); + ++ reserve_bios_regions(); ++ + efi_fake_memmap(); + efi_find_mirror(); + efi_esrt_init(); +@@ -1060,21 +1080,11 @@ void __init setup_arch(char **cmdline_p) + (max_pfn_mapped<<PAGE_SHIFT) - 1); + #endif + +- /* +- * Find free memory for the real mode trampoline and place it +- * there. +- * If there is not enough free memory under 1M, on EFI-enabled +- * systems there will be additional attempt to reclaim the memory +- * for the real mode trampoline at efi_free_boot_services(). +- * +- * Unconditionally reserve the entire first 1M of RAM because +- * BIOSes are know to corrupt low memory and several +- * hundred kilobytes are not worth complex detection what memory gets +- * clobbered. Moreover, on machines with SandyBridge graphics or in +- * setups that use crashkernel the entire 1M is anyway reserved. +- */ + reserve_real_mode(); + ++ trim_platform_memory_ranges(); ++ trim_low_memory_range(); ++ + init_mem_mapping(); + + idt_setup_early_pf(); +diff --git a/arch/x86/platform/efi/quirks.c b/arch/x86/platform/efi/quirks.c +index 27561b56a821..67d93a243c35 100644 +--- a/arch/x86/platform/efi/quirks.c ++++ b/arch/x86/platform/efi/quirks.c +@@ -450,18 +450,6 @@ void __init efi_free_boot_services(void) + size -= rm_size; + } + +- /* +- * Don't free memory under 1M for two reasons: +- * - BIOS might clobber it +- * - Crash kernel needs it to be reserved +- */ +- if (start + size < SZ_1M) +- continue; +- if (start < SZ_1M) { +- size -= (SZ_1M - start); +- start = SZ_1M; +- } +- + memblock_free_late(start, size); + } + +diff --git a/arch/x86/realmode/init.c b/arch/x86/realmode/init.c +index ea42630d4e2e..22fda7d99159 100644 +--- a/arch/x86/realmode/init.c ++++ b/arch/x86/realmode/init.c +@@ -29,16 +29,14 @@ void __init reserve_real_mode(void) + + /* Has to be under 1M so we can execute real-mode AP code. */ + mem = memblock_find_in_range(0, 1<<20, size, PAGE_SIZE); +- if (!mem) ++ if (!mem) { + pr_info("No sub-1M memory is available for the trampoline\n"); +- else +- set_real_mode_mem(mem); ++ return; ++ } + +- /* +- * Unconditionally reserve the entire fisrt 1M, see comment in +- * setup_arch() +- */ +- memblock_reserve(0, SZ_1M); ++ memblock_reserve(mem, size); ++ set_real_mode_mem(mem); ++ crash_reserve_low_1M(); + } + + static void sme_sev_setup_real_mode(struct trampoline_header *th) diff --git a/sys-kernel_arch-sources-g14_files-0014-acpi_unused-v2.patch b/sys-kernel_arch-sources-g14_files-0014-acpi_unused-v2.patch index d13a860eacf6..c2ade498368f 100644 --- a/sys-kernel_arch-sources-g14_files-0014-acpi_unused-v2.patch +++ b/sys-kernel_arch-sources-g14_files-0014-acpi_unused-v2.patch @@ -1,8 +1,45 @@ -diff --git a/drivers/acpi/internal.h b/drivers/acpi/internal.h -index f973bbe90e5ee..e21611c9a1703 100644 ---- a/drivers/acpi/internal.h -+++ b/drivers/acpi/internal.h -@@ -134,7 +134,7 @@ int acpi_power_init(void); +This is a backported version of the following patch from 5.13-rc4 + +From 9b7ff25d129df7c4f61e08382993e1988d56f6a7 Mon Sep 17 00:00:00 2001 +From: "Rafael J. Wysocki" <rafael.j.wysocki@intel.com> +Date: Fri, 21 May 2021 15:13:11 +0200 +Subject: ACPI: power: Refine turning off unused power resources + +Commit 7e4fdeafa61f ("ACPI: power: Turn off unused power resources +unconditionally") dropped the power resource state check from +acpi_turn_off_unused_power_resources(), because according to the +ACPI specification (e.g. ACPI 6.4, Section 7.2.2) the OS "may run +the _OFF method repeatedly, even if the resource is already off". + +However, it turns out that some systems do not follow the +specification in this particular respect and that commit introduced +boot issues on them, so refine acpi_turn_off_unused_power_resources() +to only turn off power resources without any users after device +enumeration and restore its previous behavior in the system-wide +resume path. + +Fixes: 7e4fdeafa61f ("ACPI: power: Turn off unused power resources unconditionally") +Link: https://uefi.org/specs/ACPI/6.4/07_Power_and_Performance_Mgmt/declaring-a-power-resource-object.html#off +BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=213019 +Reported-by: Zhang Rui <rui.zhang@intel.com> +Tested-by: Zhang Rui <rui.zhang@intel.com> +Reported-by: Dave Olsthoorn <dave@bewaar.me> +Tested-by: Dave Olsthoorn <dave@bewaar.me> +Reported-by: Shujun Wang <wsj20369@163.com> +Tested-by: Shujun Wang <wsj20369@163.com> +Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> +--- + drivers/acpi/internal.h | 4 ++-- + drivers/acpi/power.c | 59 ++++++++++++++++++++++++++++++++++++++----------- + drivers/acpi/scan.c | 2 +- + drivers/acpi/sleep.c | 2 +- + 4 files changed, 50 insertions(+), 17 deletions(-) + + + +--- linux-5.12/drivers/acpi/internal.h.orig 2021-06-11 13:58:34.918396821 -0700 ++++ linux-5.12/drivers/acpi/internal.h 2021-06-11 13:59:36.571792727 -0700 +@@ -135,7 +135,7 @@ void acpi_power_resources_list_free(struct list_head *list); int acpi_extract_power_resources(union acpi_object *package, unsigned int start, struct list_head *list); @@ -11,7 +48,7 @@ index f973bbe90e5ee..e21611c9a1703 100644 void acpi_power_add_remove_device(struct acpi_device *adev, bool add); int acpi_power_wakeup_list_init(struct list_head *list, int *system_level); int acpi_device_sleep_wake(struct acpi_device *dev, -@@ -142,7 +142,7 @@ int acpi_device_sleep_wake(struct acpi_device *dev, +@@ -143,7 +143,7 @@ int acpi_power_get_inferred_state(struct acpi_device *device, int *state); int acpi_power_on_resources(struct acpi_device *device, int state); int acpi_power_transition(struct acpi_device *device, int state); @@ -20,11 +57,9 @@ index f973bbe90e5ee..e21611c9a1703 100644 /* -------------------------------------------------------------------------- Device Power Management -diff --git a/drivers/acpi/power.c b/drivers/acpi/power.c -index 56102eaaa2da8..97c9a94a1a308 100644 ---- a/drivers/acpi/power.c -+++ b/drivers/acpi/power.c -@@ -52,6 +52,7 @@ struct acpi_power_resource { +--- linux-5.12/drivers/acpi/power.c.orig 2021-06-11 13:58:34.918396821 -0700 ++++ linux-5.12/drivers/acpi/power.c 2021-06-11 14:00:09.121484875 -0700 +@@ -52,6 +52,7 @@ u32 system_level; u32 order; unsigned int ref_count; @@ -32,7 +67,7 @@ index 56102eaaa2da8..97c9a94a1a308 100644 bool wakeup_enabled; struct mutex resource_lock; struct list_head dependents; -@@ -147,6 +148,7 @@ int acpi_extract_power_resources(union acpi_object *package, unsigned int start, +@@ -147,6 +148,7 @@ for (i = start; i < package->package.count; i++) { union acpi_object *element = &package->package.elements[i]; @@ -40,7 +75,7 @@ index 56102eaaa2da8..97c9a94a1a308 100644 acpi_handle rhandle; if (element->type != ACPI_TYPE_LOCAL_REFERENCE) { -@@ -163,13 +165,16 @@ int acpi_extract_power_resources(union acpi_object *package, unsigned int start, +@@ -163,13 +165,16 @@ if (acpi_power_resource_is_dup(package, start, i)) continue; @@ -60,7 +95,7 @@ index 56102eaaa2da8..97c9a94a1a308 100644 } if (err) acpi_power_resources_list_free(list); -@@ -907,7 +912,7 @@ static void acpi_power_add_resource_to_list(struct acpi_power_resource *resource +@@ -907,7 +912,7 @@ mutex_unlock(&power_resource_list_lock); } @@ -69,7 +104,7 @@ index 56102eaaa2da8..97c9a94a1a308 100644 { struct acpi_power_resource *resource; struct acpi_device *device = NULL; -@@ -918,11 +923,11 @@ int acpi_add_power_resource(acpi_handle handle) +@@ -918,11 +923,11 @@ acpi_bus_get_device(handle, &device); if (device) @@ -82,8 +117,8 @@ index 56102eaaa2da8..97c9a94a1a308 100644 + return NULL; device = &resource->device; - acpi_init_device_object(device, handle, ACPI_BUS_TYPE_POWER); -@@ -959,11 +964,11 @@ int acpi_add_power_resource(acpi_handle handle) + acpi_init_device_object(device, handle, ACPI_BUS_TYPE_POWER, +@@ -960,11 +965,11 @@ acpi_power_add_resource_to_list(resource); acpi_device_add_finalize(device); @@ -97,7 +132,7 @@ index 56102eaaa2da8..97c9a94a1a308 100644 } #ifdef CONFIG_ACPI_SLEEP -@@ -997,7 +1002,38 @@ void acpi_resume_power_resources(void) +@@ -998,7 +1003,38 @@ } #endif @@ -137,11 +172,12 @@ index 56102eaaa2da8..97c9a94a1a308 100644 { struct acpi_power_resource *resource; -@@ -1006,10 +1042,7 @@ void acpi_turn_off_unused_power_resources(void) - list_for_each_entry_reverse(resource, &acpi_power_resource_list, list_node) { - mutex_lock(&resource->resource_lock); +@@ -1015,11 +1051,7 @@ + continue; + } -- if (!resource->ref_count) { +- if (state == ACPI_POWER_RESOURCE_STATE_ON +- && !resource->ref_count) { - dev_info(&resource->device.dev, "Turning OFF\n"); - __acpi_power_off(resource); - } @@ -149,11 +185,9 @@ index 56102eaaa2da8..97c9a94a1a308 100644 mutex_unlock(&resource->resource_lock); } -diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c -index 453eff8ec8c33..e10d38ac7cf28 100644 ---- a/drivers/acpi/scan.c -+++ b/drivers/acpi/scan.c -@@ -2360,7 +2360,7 @@ int __init acpi_scan_init(void) +--- linux-5.12/drivers/acpi/scan.c.orig 2021-06-11 13:58:34.918396821 -0700 ++++ linux-5.12/drivers/acpi/scan.c 2021-06-11 13:59:36.573792709 -0700 +@@ -2394,7 +2394,7 @@ } } @@ -162,11 +196,9 @@ index 453eff8ec8c33..e10d38ac7cf28 100644 acpi_scan_initialized = true; -diff --git a/drivers/acpi/sleep.c b/drivers/acpi/sleep.c -index 09fd13757b658..df386571da98b 100644 ---- a/drivers/acpi/sleep.c -+++ b/drivers/acpi/sleep.c -@@ -504,7 +504,7 @@ static void acpi_pm_start(u32 acpi_state) +--- linux-5.12/drivers/acpi/sleep.c 2021-06-11 14:05:25.798799399 -0700 ++++ linux-5.12/drivers/acpi/sleep.c.new 2021-06-11 14:04:41.767145304 -0700 +@@ -504,7 +504,7 @@ */ static void acpi_pm_end(void) { @@ -174,4 +206,4 @@ index 09fd13757b658..df386571da98b 100644 + acpi_turn_off_unused_power_resources(false); acpi_scan_lock_release(); /* - * This is necessary in case acpi_pm_finish() is not called during a + * This is necessary in case acpi_pm_finish() is not called during a
\ No newline at end of file diff --git a/sys-kernel_arch-sources-g14_files-0015-revert-4cbbe34807938e6e494e535a68d5ff64edac3f20.patch b/sys-kernel_arch-sources-g14_files-0015-revert-4cbbe34807938e6e494e535a68d5ff64edac3f20.patch new file mode 100644 index 000000000000..2dd5dd8a056b --- /dev/null +++ b/sys-kernel_arch-sources-g14_files-0015-revert-4cbbe34807938e6e494e535a68d5ff64edac3f20.patch @@ -0,0 +1,40 @@ +From ee5468b9f1d3bf48082eed351dace14598e8ca39 Mon Sep 17 00:00:00 2001 +From: Yifan Zhang <yifan1.zhang@amd.com> +Date: Sat, 19 Jun 2021 11:40:54 +0800 +Subject: [PATCH] Revert "drm/amdgpu/gfx9: fix the doorbell missing when in + CGPG issue." + +This reverts commit 4cbbe34807938e6e494e535a68d5ff64edac3f20. + +Reason for revert: side effect of enlarging CP_MEC_DOORBELL_RANGE may +cause some APUs fail to enter gfxoff in certain user cases. + +Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Cc: stable@vger.kernel.org +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 +----- + 1 file changed, 1 insertion(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index c09225d065c2..516467e962b7 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -3673,12 +3673,8 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) + if (ring->use_doorbell) { + WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, + (adev->doorbell_index.kiq * 2) << 2); +- /* If GC has entered CGPG, ringing doorbell > first page doesn't +- * wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround +- * this issue. +- */ + WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, +- (adev->doorbell.size - 4)); ++ (adev->doorbell_index.userqueue_end * 2) << 2); + } + + WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, +-- +GitLab + diff --git a/sys-kernel_arch-sources-g14_files-0016-revert-1c0b0efd148d5b24c4932ddb3fa03c8edd6097b3.patch b/sys-kernel_arch-sources-g14_files-0016-revert-1c0b0efd148d5b24c4932ddb3fa03c8edd6097b3.patch new file mode 100644 index 000000000000..af3eaf22a1b6 --- /dev/null +++ b/sys-kernel_arch-sources-g14_files-0016-revert-1c0b0efd148d5b24c4932ddb3fa03c8edd6097b3.patch @@ -0,0 +1,40 @@ +From baacf52a473b24e10322b67757ddb92ab8d86717 Mon Sep 17 00:00:00 2001 +From: Yifan Zhang <yifan1.zhang@amd.com> +Date: Sat, 19 Jun 2021 11:39:43 +0800 +Subject: [PATCH] Revert "drm/amdgpu/gfx10: enlarge CP_MEC_DOORBELL_RANGE_UPPER + to cover full doorbell." + +This reverts commit 1c0b0efd148d5b24c4932ddb3fa03c8edd6097b3. + +Reason for revert: Side effect of enlarging CP_MEC_DOORBELL_RANGE may +cause some APUs fail to enter gfxoff in certain user cases. + +Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Cc: stable@vger.kernel.org +--- + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +----- + 1 file changed, 1 insertion(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +index 327b1f8213a8..0597aeb5f0e8 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +@@ -6871,12 +6871,8 @@ static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) + if (ring->use_doorbell) { + WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, + (adev->doorbell_index.kiq * 2) << 2); +- /* If GC has entered CGPG, ringing doorbell > first page doesn't +- * wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround +- * this issue. +- */ + WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, +- (adev->doorbell.size - 4)); ++ (adev->doorbell_index.userqueue_end * 2) << 2); + } + + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, +-- +GitLab + diff --git a/sys-kernel_arch-sources-g14_files-0017-5.14-ACPI-processor-idle-Fix-up-C-state-latency-if-not-ordered.patch b/sys-kernel_arch-sources-g14_files-0017-5.14-ACPI-processor-idle-Fix-up-C-state-latency-if-not-ordered.patch new file mode 100644 index 000000000000..cde53bfc9175 --- /dev/null +++ b/sys-kernel_arch-sources-g14_files-0017-5.14-ACPI-processor-idle-Fix-up-C-state-latency-if-not-ordered.patch @@ -0,0 +1,108 @@ +From a3c5cb660f9b75c581ed0b0616709e89a77f098a Mon Sep 17 00:00:00 2001 +From: Mario Limonciello <mario.limonciello@amd.com> +Date: Wed, 12 May 2021 17:15:14 -0500 +Subject: [PATCH] ACPI: processor idle: Fix up C-state latency if not ordered + +Generally, the C-state latency is provided by the _CST method or +FADT, but some OEM platforms using AMD Picasso, Renoir, Van Gogh, +and Cezanne set the C2 latency greater than C3's which causes the +C2 state to be skipped. + +That will block the core entering PC6, which prevents S0ix working +properly on Linux systems. + +In other operating systems, the latency values are not validated and +this does not cause problems by skipping states. + +To avoid this issue on Linux, detect when latencies are not an +arithmetic progression and sort them. + +Link: https://gitlab.freedesktop.org/agd5f/linux/-/commit/026d186e4592c1ee9c1cb44295912d0294508725 +Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1230#note_712174 +Suggested-by: Prike Liang <Prike.Liang@amd.com> +Suggested-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> +[ rjw: Subject and changelog edits ] +Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> +--- + drivers/acpi/processor_idle.c | 40 +++++++++++++++++++++++++++++++++++ + 1 file changed, 40 insertions(+) + +diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c +index 4e2d76b8b697..6790df5a2462 100644 +--- a/drivers/acpi/processor_idle.c ++++ b/drivers/acpi/processor_idle.c +@@ -16,6 +16,7 @@ + #include <linux/acpi.h> + #include <linux/dmi.h> + #include <linux/sched.h> /* need_resched() */ ++#include <linux/sort.h> + #include <linux/tick.h> + #include <linux/cpuidle.h> + #include <linux/cpu.h> +@@ -388,10 +389,37 @@ static void acpi_processor_power_verify_c3(struct acpi_processor *pr, + return; + } + ++static int acpi_cst_latency_cmp(const void *a, const void *b) ++{ ++ const struct acpi_processor_cx *x = a, *y = b; ++ ++ if (!(x->valid && y->valid)) ++ return 0; ++ if (x->latency > y->latency) ++ return 1; ++ if (x->latency < y->latency) ++ return -1; ++ return 0; ++} ++static void acpi_cst_latency_swap(void *a, void *b, int n) ++{ ++ struct acpi_processor_cx *x = a, *y = b; ++ u32 tmp; ++ ++ if (!(x->valid && y->valid)) ++ return; ++ tmp = x->latency; ++ x->latency = y->latency; ++ y->latency = tmp; ++} ++ + static int acpi_processor_power_verify(struct acpi_processor *pr) + { + unsigned int i; + unsigned int working = 0; ++ unsigned int last_latency = 0; ++ unsigned int last_type = 0; ++ bool buggy_latency = false; + + pr->power.timer_broadcast_on_state = INT_MAX; + +@@ -415,12 +443,24 @@ static int acpi_processor_power_verify(struct acpi_processor *pr) + } + if (!cx->valid) + continue; ++ if (cx->type >= last_type && cx->latency < last_latency) ++ buggy_latency = true; ++ last_latency = cx->latency; ++ last_type = cx->type; + + lapic_timer_check_state(i, pr, cx); + tsc_check_state(cx->type); + working++; + } + ++ if (buggy_latency) { ++ pr_notice("FW issue: working around C-state latencies out of order\n"); ++ sort(&pr->power.states[1], max_cstate, ++ sizeof(struct acpi_processor_cx), ++ acpi_cst_latency_cmp, ++ acpi_cst_latency_swap); ++ } ++ + lapic_timer_propagate_broadcast(pr); + + return (working); +-- +GitLab + diff --git a/sys-kernel_arch-sources-g14_files-0018-PCI-quirks-Quirk-PCI-d3hot-delay-for-AMD-xhci.patch b/sys-kernel_arch-sources-g14_files-0018-PCI-quirks-Quirk-PCI-d3hot-delay-for-AMD-xhci.patch new file mode 100644 index 000000000000..a6797595b45a --- /dev/null +++ b/sys-kernel_arch-sources-g14_files-0018-PCI-quirks-Quirk-PCI-d3hot-delay-for-AMD-xhci.patch @@ -0,0 +1,30 @@ +From 6e4c0295938e21c52d86502da5c454204617f9a8 Mon Sep 17 00:00:00 2001 +From: Marcin Bachry <hegel666@gmail.com> +Date: Tue, 16 Mar 2021 15:28:51 -0400 +Subject: [PATCH] PCI: quirks: Quirk PCI d3hot delay for AMD xhci + +Renoir needs a similar delay. + +Signed-off-by: Marcin Bachry <hegel666@gmail.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/pci/quirks.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c +index 98851d00dc4d..8c929b7d335e 100644 +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -1904,6 +1904,9 @@ static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev) + } + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot); + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot); ++/* Renoir XHCI requires longer delay when transitioning from D0 to ++ * D3hot */ ++DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot); + + #ifdef CONFIG_X86_IO_APIC + static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) +-- +GitLab + diff --git a/sys-kernel_arch-sources-g14_files-0019-5.14-nvme-pci-look-for-StorageD3Enable-on-companion-ACPI-device.patch b/sys-kernel_arch-sources-g14_files-0019-5.14-nvme-pci-look-for-StorageD3Enable-on-companion-ACPI-device.patch new file mode 100644 index 000000000000..18f4baf9eb2c --- /dev/null +++ b/sys-kernel_arch-sources-g14_files-0019-5.14-nvme-pci-look-for-StorageD3Enable-on-companion-ACPI-device.patch @@ -0,0 +1,74 @@ +From 137bd7494abeceab04bf62eeec4647db5048353a Mon Sep 17 00:00:00 2001 +From: Mario Limonciello <mario.limonciello@amd.com> +Date: Fri, 28 May 2021 11:02:34 -0500 +Subject: [PATCH] nvme-pci: look for StorageD3Enable on companion ACPI device + instead + +The documentation around the StorageD3Enable property hints that it +should be made on the PCI device. This is where newer AMD systems set +the property and it's required for S0i3 support. + +So rather than look for nodes of the root port only present on Intel +systems, switch to the companion ACPI device for all systems. +David Box from Intel indicated this should work on Intel as well. + +Link: https://lore.kernel.org/linux-nvme/YK6gmAWqaRmvpJXb@google.com/T/#m900552229fa455867ee29c33b854845fce80ba70 +Link: https://docs.microsoft.com/en-us/windows-hardware/design/component-guidelines/power-management-for-storage-hardware-devices-intro +Fixes: df4f9bc4fb9c ("nvme-pci: add support for ACPI StorageD3Enable property") +Suggested-by: Liang Prike <Prike.Liang@amd.com> +Acked-by: Raul E Rangel <rrangel@chromium.org> +Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> +Reviewed-by: David E. Box <david.e.box@linux.intel.com> +Signed-off-by: Christoph Hellwig <hch@lst.de> +--- + drivers/nvme/host/pci.c | 24 +----------------------- + 1 file changed, 1 insertion(+), 23 deletions(-) + +diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c +index c92a15c3fbc5..60c1c83e03fa 100644 +--- a/drivers/nvme/host/pci.c ++++ b/drivers/nvme/host/pci.c +@@ -2834,10 +2834,7 @@ static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) + #ifdef CONFIG_ACPI + static bool nvme_acpi_storage_d3(struct pci_dev *dev) + { +- struct acpi_device *adev; +- struct pci_dev *root; +- acpi_handle handle; +- acpi_status status; ++ struct acpi_device *adev = ACPI_COMPANION(&dev->dev); + u8 val; + + /* +@@ -2845,28 +2842,9 @@ static bool nvme_acpi_storage_d3(struct pci_dev *dev) + * must use D3 to support deep platform power savings during + * suspend-to-idle. + */ +- root = pcie_find_root_port(dev); +- if (!root) +- return false; + +- adev = ACPI_COMPANION(&root->dev); + if (!adev) + return false; +- +- /* +- * The property is defined in the PXSX device for South complex ports +- * and in the PEGP device for North complex ports. +- */ +- status = acpi_get_handle(adev->handle, "PXSX", &handle); +- if (ACPI_FAILURE(status)) { +- status = acpi_get_handle(adev->handle, "PEGP", &handle); +- if (ACPI_FAILURE(status)) +- return false; +- } +- +- if (acpi_bus_get_device(handle, &adev)) +- return false; +- + if (fwnode_property_read_u8(acpi_fwnode_handle(adev), "StorageD3Enable", + &val)) + return false; +-- +GitLab + diff --git a/sys-kernel_arch-sources-g14_files-0020-5.14-ACPI-Check-StorageD3Enable_DSD-property-in-AHCI-mode.patch b/sys-kernel_arch-sources-g14_files-0020-5.14-ACPI-Check-StorageD3Enable_DSD-property-in-AHCI-mode.patch new file mode 100644 index 000000000000..1526dad95c09 --- /dev/null +++ b/sys-kernel_arch-sources-g14_files-0020-5.14-ACPI-Check-StorageD3Enable_DSD-property-in-AHCI-mode.patch @@ -0,0 +1,136 @@ +From 183b978ab6434645aca18091e7c1458bad7590dc Mon Sep 17 00:00:00 2001 +From: Mario Limonciello <mario.limonciello@amd.com> +Date: Wed, 9 Jun 2021 13:40:17 -0500 +Subject: [PATCH] ACPI: Check StorageD3Enable _DSD property in ACPI code + +Although first implemented for NVME, this check may be usable by +other drivers as well. Microsoft's specification explicitly mentions +that is may be usable by SATA and AHCI devices. Google also indicates +that they have used this with SDHCI in a downstream kernel tree that +a user can plug a storage device into. + +Link: https://docs.microsoft.com/en-us/windows-hardware/design/component-guidelines/power-management-for-storage-hardware-devices-intro +Suggested-by: Keith Busch <kbusch@kernel.org> +CC: Shyam-sundar S-k <Shyam-sundar.S-k@amd.com> +CC: Alexander Deucher <Alexander.Deucher@amd.com> +CC: Rafael J. Wysocki <rjw@rjwysocki.net> +CC: Prike Liang <prike.liang@amd.com> +Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> +Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> +Signed-off-by: Christoph Hellwig <hch@lst.de> +--- + drivers/acpi/device_pm.c | 29 +++++++++++++++++++++++++++++ + drivers/nvme/host/pci.c | 28 +--------------------------- + include/linux/acpi.h | 5 +++++ + 3 files changed, 35 insertions(+), 27 deletions(-) + +diff --git a/drivers/acpi/device_pm.c b/drivers/acpi/device_pm.c +index 58876248b192..1e278785c7db 100644 +--- a/drivers/acpi/device_pm.c ++++ b/drivers/acpi/device_pm.c +@@ -1337,4 +1337,33 @@ int acpi_dev_pm_attach(struct device *dev, bool power_on) + return 1; + } + EXPORT_SYMBOL_GPL(acpi_dev_pm_attach); ++ ++/** ++ * acpi_storage_d3 - Check if D3 should be used in the suspend path ++ * @dev: Device to check ++ * ++ * Return %true if the platform firmware wants @dev to be programmed ++ * into D3hot or D3cold (if supported) in the suspend path, or %false ++ * when there is no specific preference. On some platforms, if this ++ * hint is ignored, @dev may remain unresponsive after suspending the ++ * platform as a whole. ++ * ++ * Although the property has storage in the name it actually is ++ * applied to the PCIe slot and plugging in a non-storage device the ++ * same platform restrictions will likely apply. ++ */ ++bool acpi_storage_d3(struct device *dev) ++{ ++ struct acpi_device *adev = ACPI_COMPANION(dev); ++ u8 val; ++ ++ if (!adev) ++ return false; ++ if (fwnode_property_read_u8(acpi_fwnode_handle(adev), "StorageD3Enable", ++ &val)) ++ return false; ++ return val == 1; ++} ++EXPORT_SYMBOL_GPL(acpi_storage_d3); ++ + #endif /* CONFIG_PM */ +diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c +index 60c1c83e03fa..8593161d4da0 100644 +--- a/drivers/nvme/host/pci.c ++++ b/drivers/nvme/host/pci.c +@@ -2831,32 +2831,6 @@ static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) + return 0; + } + +-#ifdef CONFIG_ACPI +-static bool nvme_acpi_storage_d3(struct pci_dev *dev) +-{ +- struct acpi_device *adev = ACPI_COMPANION(&dev->dev); +- u8 val; +- +- /* +- * Look for _DSD property specifying that the storage device on the port +- * must use D3 to support deep platform power savings during +- * suspend-to-idle. +- */ +- +- if (!adev) +- return false; +- if (fwnode_property_read_u8(acpi_fwnode_handle(adev), "StorageD3Enable", +- &val)) +- return false; +- return val == 1; +-} +-#else +-static inline bool nvme_acpi_storage_d3(struct pci_dev *dev) +-{ +- return false; +-} +-#endif /* CONFIG_ACPI */ +- + static void nvme_async_probe(void *data, async_cookie_t cookie) + { + struct nvme_dev *dev = data; +@@ -2906,7 +2880,7 @@ static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) + + quirks |= check_vendor_combination_bug(pdev); + +- if (!noacpi && nvme_acpi_storage_d3(pdev)) { ++ if (!noacpi && acpi_storage_d3(&pdev->dev)) { + /* + * Some systems use a bios work around to ask for D3 on + * platforms that support kernel managed suspend. +diff --git a/include/linux/acpi.h b/include/linux/acpi.h +index 3bdcfc4401b7..4dfe15c2933d 100644 +--- a/include/linux/acpi.h ++++ b/include/linux/acpi.h +@@ -999,6 +999,7 @@ int acpi_dev_resume(struct device *dev); + int acpi_subsys_runtime_suspend(struct device *dev); + int acpi_subsys_runtime_resume(struct device *dev); + int acpi_dev_pm_attach(struct device *dev, bool power_on); ++bool acpi_storage_d3(struct device *dev); + #else + static inline int acpi_subsys_runtime_suspend(struct device *dev) { return 0; } + static inline int acpi_subsys_runtime_resume(struct device *dev) { return 0; } +@@ -1006,6 +1007,10 @@ static inline int acpi_dev_pm_attach(struct device *dev, bool power_on) + { + return 0; + } ++static inline bool acpi_storage_d3(struct device *dev) ++{ ++ return false; ++} + #endif + + #if defined(CONFIG_ACPI) && defined(CONFIG_PM_SLEEP) +-- +GitLab + diff --git a/sys-kernel_arch-sources-g14_files-0021-5.14-ACPI-Add-quirks-for-AMD-Renoir+Lucienne-CPUs-to-force-the-D3-hint.patch b/sys-kernel_arch-sources-g14_files-0021-5.14-ACPI-Add-quirks-for-AMD-Renoir+Lucienne-CPUs-to-force-the-D3-hint.patch new file mode 100644 index 000000000000..14ef4d23ad19 --- /dev/null +++ b/sys-kernel_arch-sources-g14_files-0021-5.14-ACPI-Add-quirks-for-AMD-Renoir+Lucienne-CPUs-to-force-the-D3-hint.patch @@ -0,0 +1,122 @@ +From d406ff9472c867a9777d1ae8ba7cb7a66a9a0b51 Mon Sep 17 00:00:00 2001 +From: Mario Limonciello <mario.limonciello@amd.com> +Date: Wed, 9 Jun 2021 13:40:18 -0500 +Subject: [PATCH] ACPI: Add quirks for AMD Renoir/Lucienne CPUs to force the D3 + hint + +AMD systems from Renoir and Lucienne require that the NVME controller +is put into D3 over a Modern Standby / suspend-to-idle +cycle. This is "typically" accomplished using the `StorageD3Enable` +property in the _DSD, but this property was introduced after many +of these systems launched and most OEM systems don't have it in +their BIOS. + +On AMD Renoir without these drives going into D3 over suspend-to-idle +the resume will fail with the NVME controller being reset and a trace +like this in the kernel logs: +``` +[ 83.556118] nvme nvme0: I/O 161 QID 2 timeout, aborting +[ 83.556178] nvme nvme0: I/O 162 QID 2 timeout, aborting +[ 83.556187] nvme nvme0: I/O 163 QID 2 timeout, aborting +[ 83.556196] nvme nvme0: I/O 164 QID 2 timeout, aborting +[ 95.332114] nvme nvme0: I/O 25 QID 0 timeout, reset controller +[ 95.332843] nvme nvme0: Abort status: 0x371 +[ 95.332852] nvme nvme0: Abort status: 0x371 +[ 95.332856] nvme nvme0: Abort status: 0x371 +[ 95.332859] nvme nvme0: Abort status: 0x371 +[ 95.332909] PM: dpm_run_callback(): pci_pm_resume+0x0/0xe0 returns -16 +[ 95.332936] nvme 0000:03:00.0: PM: failed to resume async: error -16 +``` + +The Microsoft documentation for StorageD3Enable mentioned that Windows has +a hardcoded allowlist for D3 support, which was used for these platforms. +Introduce quirks to hardcode them for Linux as well. + +As this property is now "standardized", OEM systems using AMD Cezanne and +newer APU's have adopted this property, and quirks like this should not be +necessary. + +CC: Shyam-sundar S-k <Shyam-sundar.S-k@amd.com> +CC: Alexander Deucher <Alexander.Deucher@amd.com> +CC: Prike Liang <prike.liang@amd.com> +Link: https://docs.microsoft.com/en-us/windows-hardware/design/component-guidelines/power-management-for-storage-hardware-devices-intro +Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> +Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> +Tested-by: Julian Sikorski <belegdol@gmail.com> +Signed-off-by: Christoph Hellwig <hch@lst.de> +--- + drivers/acpi/device_pm.c | 3 +++ + drivers/acpi/internal.h | 9 +++++++++ + drivers/acpi/x86/utils.c | 25 +++++++++++++++++++++++++ + 3 files changed, 37 insertions(+) + +diff --git a/drivers/acpi/device_pm.c b/drivers/acpi/device_pm.c +index 1e278785c7db..28f629a3d95c 100644 +--- a/drivers/acpi/device_pm.c ++++ b/drivers/acpi/device_pm.c +@@ -1357,6 +1357,9 @@ bool acpi_storage_d3(struct device *dev) + struct acpi_device *adev = ACPI_COMPANION(dev); + u8 val; + ++ if (force_storage_d3()) ++ return true; ++ + if (!adev) + return false; + if (fwnode_property_read_u8(acpi_fwnode_handle(adev), "StorageD3Enable", +diff --git a/drivers/acpi/internal.h b/drivers/acpi/internal.h +index cb8f70842249..96471be3f0c8 100644 +--- a/drivers/acpi/internal.h ++++ b/drivers/acpi/internal.h +@@ -236,6 +236,15 @@ static inline int suspend_nvs_save(void) { return 0; } + static inline void suspend_nvs_restore(void) {} + #endif + ++#ifdef CONFIG_X86 ++bool force_storage_d3(void); ++#else ++static inline bool force_storage_d3(void) ++{ ++ return false; ++} ++#endif ++ + /*-------------------------------------------------------------------------- + Device properties + -------------------------------------------------------------------------- */ +diff --git a/drivers/acpi/x86/utils.c b/drivers/acpi/x86/utils.c +index bdc1ba00aee9..f22f23933063 100644 +--- a/drivers/acpi/x86/utils.c ++++ b/drivers/acpi/x86/utils.c +@@ -135,3 +135,28 @@ bool acpi_device_always_present(struct acpi_device *adev) + + return ret; + } ++ ++/* ++ * AMD systems from Renoir and Lucienne *require* that the NVME controller ++ * is put into D3 over a Modern Standby / suspend-to-idle cycle. ++ * ++ * This is "typically" accomplished using the `StorageD3Enable` ++ * property in the _DSD that is checked via the `acpi_storage_d3` function ++ * but this property was introduced after many of these systems launched ++ * and most OEM systems don't have it in their BIOS. ++ * ++ * The Microsoft documentation for StorageD3Enable mentioned that Windows has ++ * a hardcoded allowlist for D3 support, which was used for these platforms. ++ * ++ * This allows quirking on Linux in a similar fashion. ++ */ ++static const struct x86_cpu_id storage_d3_cpu_ids[] = { ++ X86_MATCH_VENDOR_FAM_MODEL(AMD, 23, 96, NULL), /* Renoir */ ++ X86_MATCH_VENDOR_FAM_MODEL(AMD, 23, 104, NULL), /* Lucienne */ ++ {} ++}; ++ ++bool force_storage_d3(void) ++{ ++ return x86_match_cpu(storage_d3_cpu_ids); ++} +-- +GitLab + diff --git a/sys-kernel_arch-sources-g14_files-0022-5.14-ACPI-PM-s2idle-Add-missing-LPS0-functions-for-AMD.patch b/sys-kernel_arch-sources-g14_files-0022-5.14-ACPI-PM-s2idle-Add-missing-LPS0-functions-for-AMD.patch new file mode 100644 index 000000000000..b4616cbe47ce --- /dev/null +++ b/sys-kernel_arch-sources-g14_files-0022-5.14-ACPI-PM-s2idle-Add-missing-LPS0-functions-for-AMD.patch @@ -0,0 +1,51 @@ +From 0873305b912e5039e4d9bf2f81de3bc9cf9eae07 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Wed, 5 May 2021 09:20:32 -0400 +Subject: [PATCH] ACPI: PM: s2idle: Add missing LPS0 functions for AMD + +These are supposedly not required for AMD platforms, +but at least some HP laptops seem to require it to +properly turn off the keyboard backlight. + +Based on a patch from Marcin Bachry <hegel666@gmail.com>. + +Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1230 +Reviewed-by: Hans de Goede <hdegoede@redhat.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> +--- + drivers/acpi/x86/s2idle.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/acpi/x86/s2idle.c b/drivers/acpi/x86/s2idle.c +index 2b69536cdccb..2d7ddb8a8cb6 100644 +--- a/drivers/acpi/x86/s2idle.c ++++ b/drivers/acpi/x86/s2idle.c +@@ -42,6 +42,8 @@ static const struct acpi_device_id lps0_device_ids[] = { + + /* AMD */ + #define ACPI_LPS0_DSM_UUID_AMD "e3f32452-febc-43ce-9039-932122d37721" ++#define ACPI_LPS0_ENTRY_AMD 2 ++#define ACPI_LPS0_EXIT_AMD 3 + #define ACPI_LPS0_SCREEN_OFF_AMD 4 + #define ACPI_LPS0_SCREEN_ON_AMD 5 + +@@ -408,6 +410,7 @@ int acpi_s2idle_prepare_late(void) + + if (acpi_s2idle_vendor_amd()) { + acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_OFF_AMD); ++ acpi_sleep_run_lps0_dsm(ACPI_LPS0_ENTRY_AMD); + } else { + acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_OFF); + acpi_sleep_run_lps0_dsm(ACPI_LPS0_ENTRY); +@@ -422,6 +425,7 @@ void acpi_s2idle_restore_early(void) + return; + + if (acpi_s2idle_vendor_amd()) { ++ acpi_sleep_run_lps0_dsm(ACPI_LPS0_EXIT_AMD); + acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_ON_AMD); + } else { + acpi_sleep_run_lps0_dsm(ACPI_LPS0_EXIT); +-- +GitLab + diff --git a/sys-kernel_arch-sources-g14_files-0023-5.14-1of5-ACPI-PM-s2idle-Use-correct-revision-id.patch b/sys-kernel_arch-sources-g14_files-0023-5.14-1of5-ACPI-PM-s2idle-Use-correct-revision-id.patch new file mode 100644 index 000000000000..907e56346d17 --- /dev/null +++ b/sys-kernel_arch-sources-g14_files-0023-5.14-1of5-ACPI-PM-s2idle-Use-correct-revision-id.patch @@ -0,0 +1,144 @@ +From mboxrd@z Thu Jan 1 00:00:00 1970 +Return-Path: <linux-acpi-owner@kernel.org> +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, + DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, + INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, + SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 43C40C2B9F4 + for <linux-acpi@archiver.kernel.org>; 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With this change, +device constraint list is populated properly. + +Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> +--- + drivers/acpi/x86/s2idle.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/acpi/x86/s2idle.c b/drivers/acpi/x86/s2idle.c +index 2d7ddb8a8cb6..da27c1c45c9f 100644 +--- a/drivers/acpi/x86/s2idle.c ++++ b/drivers/acpi/x86/s2idle.c +@@ -96,7 +96,7 @@ static void lpi_device_get_constraints_amd(void) + int i, j, k; + + out_obj = acpi_evaluate_dsm_typed(lps0_device_handle, &lps0_dsm_guid, +- 1, ACPI_LPS0_GET_DEVICE_CONSTRAINTS, ++ rev_id, ACPI_LPS0_GET_DEVICE_CONSTRAINTS, + NULL, ACPI_TYPE_PACKAGE); + + if (!out_obj) +-- +2.25.1 + + diff --git a/sys-kernel_arch-sources-g14_files-0024-5.14-2of5-ACPI-PM-s2idle-Refactor-common-code.patch b/sys-kernel_arch-sources-g14_files-0024-5.14-2of5-ACPI-PM-s2idle-Refactor-common-code.patch new file mode 100644 index 000000000000..3b10381a8b49 --- /dev/null +++ b/sys-kernel_arch-sources-g14_files-0024-5.14-2of5-ACPI-PM-s2idle-Refactor-common-code.patch @@ -0,0 +1,258 @@ +From mboxrd@z Thu Jan 1 00:00:00 1970 +Return-Path: <linux-acpi-owner@kernel.org> +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, + DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, + INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, + SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id BC568C48BE5 + for <linux-acpi@archiver.kernel.org>; Thu, 17 Jun 2021 16:42:40 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 94916613E2 + for <linux-acpi@archiver.kernel.org>; Thu, 17 Jun 2021 16:42:40 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S230381AbhFQQoq (ORCPT <rfc822;linux-acpi@archiver.kernel.org>); + Thu, 17 Jun 2021 12:44:46 -0400 +Received: from mail-co1nam11on2044.outbound.protection.outlook.com ([40.107.220.44]:6999 + "EHLO NAM11-CO1-obe.outbound.protection.outlook.com" + rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP + id S230387AbhFQQop (ORCPT <rfc822;linux-acpi@vger.kernel.org>); + Thu, 17 Jun 2021 12:44:45 -0400 +ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; + b=V6eXBGcszCWpoAH9tz4DELRomjgGmHAhZ7r+RbHTG44A6eAsLKUudbNWJ9jYGGlXNwEIKDHu/kIPxRguN1zOn2StNISwkef2STFZF4aIPcEwN8cWt6YPE3VoJyn/RUvtC4ZaFZcFpqCJEYHuhIlgaqRKiVIM6vJUXfJ4NiyvkAXLA/Y4AFq8H61RBPOBK1dTU0ITTNUSFjkUbQNAr+hxEZedhqe9vdVzq8P2c+jXGWmsRaHNX0PZS44hYmCBLeeDWkr4I8mpKuKLks+V/Qtk3+G5b3emRWkya6agMVOl5z+MbfLJA67V1z1AkbNWOw6qbZ7wrhGw6xwfC7juRUHdyw== +ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; + s=arcselector9901; + h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; + bh=Znl4jP9p6Dn7HKGtw+UAuzNdgwbq0RqWRqxn7vO/mX0=; + b=JuMruFf+J8EsWrr/1MpNtbZ5ri5w+9NsCx2+XXsPT5nOdT88r/bFiVANKnh8fTAOPS9DpDhDS7mc/AEZxto3xwLxbND0YqKFlK96iBpSVX9smVcHGx/9iR6Z92/y2Ymstx+mS6l8TXPdHODu98kffLZq3HIusNg8QxoscjBoTvbbyX1F+kvFhUob7AZIIujFYhAWGRiBX1Doet299G9pQGavQomTPmojfu0M+SLye6Xzr1gmfVY/A5FXphuicsgjonongj4VmDxsoj8mLA5F1Xk2haMV60/eoWSBqdrHn06RfblBkF68OEdouTPJcb6bBJVDUCEMWjPhIB0LPktyiw== +ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass + smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass + header.d=amd.com; arc=none +DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; + h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; + bh=Znl4jP9p6Dn7HKGtw+UAuzNdgwbq0RqWRqxn7vO/mX0=; + b=q5hz7YVwWEWssjYP7+1Yhxr3WMyqlmJ8S4vvch5i1mF9sM5zoKjsWCSCIg07ROY7TsmcAlRx7/bG9AR11+ZaTKVvdbfqZV0YQEDmamghhkYDa0V2ty3a7RncTyec7bkMf7PHKk7usUML4HSjErzGU1Y2B1MYayi4ipBPYcMH5R0= +Authentication-Results: rjwysocki.net; dkim=none (message not signed) + header.d=none;rjwysocki.net; dmarc=none action=none header.from=amd.com; +Received: from SA0PR12MB4510.namprd12.prod.outlook.com (2603:10b6:806:94::8) + by SN6PR12MB4671.namprd12.prod.outlook.com (2603:10b6:805:e::22) with + Microsoft SMTP Server (version=TLS1_2, + cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.21; Thu, 17 Jun + 2021 16:42:36 +0000 +Received: from SA0PR12MB4510.namprd12.prod.outlook.com + ([fe80::9c16:2794:cd04:2be0]) by SA0PR12MB4510.namprd12.prod.outlook.com + ([fe80::9c16:2794:cd04:2be0%6]) with mapi id 15.20.4242.021; Thu, 17 Jun 2021 + 16:42:36 +0000 +From: Mario Limonciello <mario.limonciello@amd.com> +To: "Rafael J . Wysocki" <rjw@rjwysocki.net>, + Len Brown <lenb@kernel.org>, linux-acpi@vger.kernel.org +Cc: Julian Sikorski <belegdol@gmail.com>, teohhanhui@gmail.com, + Shyam-sundar.S-k@amd.com, + Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>, + Mario Limonciello <mario.limonciello@amd.com> +Subject: [PATCH 2/5] ACPI: PM: s2idle: Refactor common code +Date: Thu, 17 Jun 2021 11:42:09 -0500 +Message-Id: <20210617164212.584-2-mario.limonciello@amd.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210617164212.584-1-mario.limonciello@amd.com> +References: <20210617164212.584-1-mario.limonciello@amd.com> +Content-Transfer-Encoding: 8bit +Content-Type: text/plain +X-Originating-IP: [76.251.167.31] +X-ClientProxiedBy: SN6PR05CA0006.namprd05.prod.outlook.com + (2603:10b6:805:de::19) To SA0PR12MB4510.namprd12.prod.outlook.com + (2603:10b6:806:94::8) +MIME-Version: 1.0 +X-MS-Exchange-MessageSentRepresentingType: 1 +Received: from AUS-LX-MLIMONCI.amd.com (76.251.167.31) by SN6PR05CA0006.namprd05.prod.outlook.com (2603:10b6:805:de::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4264.7 via Frontend Transport; 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+ static guid_t lps0_dsm_guid; +-static char lps0_dsm_func_mask; ++static int lps0_dsm_func_mask; + + /* Device constraint entry structure */ + struct lpi_device_info { +@@ -70,15 +70,7 @@ struct lpi_constraints { + int min_dstate; + }; + +-/* AMD */ +-/* Device constraint entry structure */ +-struct lpi_device_info_amd { +- int revision; +- int count; +- union acpi_object *package; +-}; +- +-/* Constraint package structure */ ++/* AMD Constraint package structure */ + struct lpi_device_constraint_amd { + char *name; + int enabled; +@@ -99,12 +91,12 @@ static void lpi_device_get_constraints_amd(void) + rev_id, ACPI_LPS0_GET_DEVICE_CONSTRAINTS, + NULL, ACPI_TYPE_PACKAGE); + +- if (!out_obj) +- return; +- + acpi_handle_debug(lps0_device_handle, "_DSM function 1 eval %s\n", + out_obj ? "successful" : "failed"); + ++ if (!out_obj) ++ return; ++ + for (i = 0; i < out_obj->package.count; i++) { + union acpi_object *package = &out_obj->package.elements[i]; + +@@ -336,11 +328,33 @@ static bool acpi_s2idle_vendor_amd(void) + return boot_cpu_data.x86_vendor == X86_VENDOR_AMD; + } + ++static int validate_dsm(acpi_handle handle, const char *uuid, int rev, guid_t *dsm_guid) ++{ ++ union acpi_object *obj; ++ int ret = -EINVAL; ++ ++ guid_parse(uuid, dsm_guid); ++ obj = acpi_evaluate_dsm(handle, dsm_guid, rev, 0, NULL); ++ ++ /* Check if the _DSM is present and as expected. */ ++ if (!obj || obj->type != ACPI_TYPE_BUFFER || obj->buffer.length == 0 || ++ obj->buffer.length > sizeof(u32)) { ++ acpi_handle_debug(handle, ++ "_DSM UUID %s rev %d function 0 evaluation failed\n", uuid, rev); ++ goto out; ++ } ++ ++ ret = *(int *)obj->buffer.pointer; ++ acpi_handle_debug(handle, "_DSM UUID %s rev %d function mask: 0x%x\n", uuid, rev, ret); ++ ++out: ++ ACPI_FREE(obj); ++ return ret; ++} ++ + static int lps0_device_attach(struct acpi_device *adev, + const struct acpi_device_id *not_used) + { +- union acpi_object *out_obj; +- + if (lps0_device_handle) + return 0; + +@@ -348,28 +362,17 @@ static int lps0_device_attach(struct acpi_device *adev, + return 0; + + if (acpi_s2idle_vendor_amd()) { +- guid_parse(ACPI_LPS0_DSM_UUID_AMD, &lps0_dsm_guid); +- out_obj = acpi_evaluate_dsm(adev->handle, &lps0_dsm_guid, 0, 0, NULL); + rev_id = 0; ++ lps0_dsm_func_mask = validate_dsm(adev->handle, ++ ACPI_LPS0_DSM_UUID_AMD, rev_id, &lps0_dsm_guid); + } else { +- guid_parse(ACPI_LPS0_DSM_UUID, &lps0_dsm_guid); +- out_obj = acpi_evaluate_dsm(adev->handle, &lps0_dsm_guid, 1, 0, NULL); + rev_id = 1; ++ lps0_dsm_func_mask = validate_dsm(adev->handle, ++ ACPI_LPS0_DSM_UUID, rev_id, &lps0_dsm_guid); + } + +- /* Check if the _DSM is present and as expected. */ +- if (!out_obj || out_obj->type != ACPI_TYPE_BUFFER) { +- acpi_handle_debug(adev->handle, +- "_DSM function 0 evaluation failed\n"); +- return 0; +- } +- +- lps0_dsm_func_mask = *(char *)out_obj->buffer.pointer; +- +- ACPI_FREE(out_obj); +- +- acpi_handle_debug(adev->handle, "_DSM function mask: 0x%x\n", +- lps0_dsm_func_mask); ++ if (lps0_dsm_func_mask < 0) ++ return 0;//function eval failed + + lps0_device_handle = adev->handle; + +-- +2.25.1 + + diff --git a/sys-kernel_arch-sources-g14_files-0025-5.14-3of5-ACPI-PM-s2idle-Add-support-for-multiple-func-mask.patch b/sys-kernel_arch-sources-g14_files-0025-5.14-3of5-ACPI-PM-s2idle-Add-support-for-multiple-func-mask.patch new file mode 100644 index 000000000000..9476b6f0ebd7 --- /dev/null +++ b/sys-kernel_arch-sources-g14_files-0025-5.14-3of5-ACPI-PM-s2idle-Add-support-for-multiple-func-mask.patch @@ -0,0 +1,196 @@ +From mboxrd@z Thu Jan 1 00:00:00 1970 +Return-Path: <linux-acpi-owner@kernel.org> +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, + DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, + INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, + SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 1641FC2B9F4 + for <linux-acpi@archiver.kernel.org>; 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Wysocki" <rjw@rjwysocki.net>, + Len Brown <lenb@kernel.org>, linux-acpi@vger.kernel.org +Cc: Julian Sikorski <belegdol@gmail.com>, teohhanhui@gmail.com, + Shyam-sundar.S-k@amd.com, + Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> +Subject: [PATCH 3/5] ACPI: PM: s2idle: Add support for multiple func mask +Date: Thu, 17 Jun 2021 11:42:10 -0500 +Message-Id: <20210617164212.584-3-mario.limonciello@amd.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210617164212.584-1-mario.limonciello@amd.com> +References: <20210617164212.584-1-mario.limonciello@amd.com> +Content-Transfer-Encoding: 8bit +Content-Type: text/plain +X-Originating-IP: [76.251.167.31] +X-ClientProxiedBy: SN6PR05CA0006.namprd05.prod.outlook.com + (2603:10b6:805:de::19) To SA0PR12MB4510.namprd12.prod.outlook.com + (2603:10b6:806:94::8) +MIME-Version: 1.0 +X-MS-Exchange-MessageSentRepresentingType: 1 +Received: from AUS-LX-MLIMONCI.amd.com (76.251.167.31) by SN6PR05CA0006.namprd05.prod.outlook.com (2603:10b6:805:de::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4264.7 via Frontend Transport; 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+ +- if (!(lps0_dsm_func_mask & (1 << func))) ++ if (!(func_mask & (1 << func))) + return; + +- out_obj = acpi_evaluate_dsm(lps0_device_handle, &lps0_dsm_guid, rev_id, func, NULL); ++ out_obj = acpi_evaluate_dsm(lps0_device_handle, &dsm_guid, ++ rev_id, func, NULL); + ACPI_FREE(out_obj); + + acpi_handle_debug(lps0_device_handle, "_DSM function %u evaluation %s\n", +@@ -412,11 +413,15 @@ int acpi_s2idle_prepare_late(void) + lpi_check_constraints(); + + if (acpi_s2idle_vendor_amd()) { +- acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_OFF_AMD); +- acpi_sleep_run_lps0_dsm(ACPI_LPS0_ENTRY_AMD); ++ acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_OFF_AMD, ++ lps0_dsm_func_mask, lps0_dsm_guid); ++ acpi_sleep_run_lps0_dsm(ACPI_LPS0_ENTRY_AMD, ++ lps0_dsm_func_mask, lps0_dsm_guid); + } else { +- acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_OFF); +- acpi_sleep_run_lps0_dsm(ACPI_LPS0_ENTRY); ++ acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_OFF, ++ lps0_dsm_func_mask, lps0_dsm_guid); ++ acpi_sleep_run_lps0_dsm(ACPI_LPS0_ENTRY, ++ lps0_dsm_func_mask, lps0_dsm_guid); + } + + return 0; +@@ -428,11 +433,15 @@ void acpi_s2idle_restore_early(void) + return; + + if (acpi_s2idle_vendor_amd()) { +- acpi_sleep_run_lps0_dsm(ACPI_LPS0_EXIT_AMD); +- acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_ON_AMD); ++ acpi_sleep_run_lps0_dsm(ACPI_LPS0_EXIT_AMD, ++ lps0_dsm_func_mask, lps0_dsm_guid); ++ acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_ON_AMD, ++ lps0_dsm_func_mask, lps0_dsm_guid); + } else { +- acpi_sleep_run_lps0_dsm(ACPI_LPS0_EXIT); +- acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_ON); ++ acpi_sleep_run_lps0_dsm(ACPI_LPS0_EXIT, ++ lps0_dsm_func_mask, lps0_dsm_guid); ++ acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_ON, ++ lps0_dsm_func_mask, lps0_dsm_guid); + } + } + +-- +2.25.1 + + diff --git a/sys-kernel_arch-sources-g14_files-0026-5.14-4of5-ACPI-PM-s2idle-Add-support-for-new-Microsoft-UUID.patch b/sys-kernel_arch-sources-g14_files-0026-5.14-4of5-ACPI-PM-s2idle-Add-support-for-new-Microsoft-UUID.patch new file mode 100644 index 000000000000..cfbbc8a25587 --- /dev/null +++ b/sys-kernel_arch-sources-g14_files-0026-5.14-4of5-ACPI-PM-s2idle-Add-support-for-new-Microsoft-UUID.patch @@ -0,0 +1,223 @@ +From mboxrd@z Thu Jan 1 00:00:00 1970 +Return-Path: <linux-acpi-owner@kernel.org> +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, + DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, + INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, + SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 75183C49361 + for <linux-acpi@archiver.kernel.org>; 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Wysocki" <rjw@rjwysocki.net>, + Len Brown <lenb@kernel.org>, linux-acpi@vger.kernel.org +Cc: Julian Sikorski <belegdol@gmail.com>, teohhanhui@gmail.com, + Shyam-sundar.S-k@amd.com, + Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>, + Mario Limonciello <mario.limonciello@amd.com> +Subject: [PATCH 4/5] ACPI: PM: s2idle: Add support for new Microsoft UUID +Date: Thu, 17 Jun 2021 11:42:11 -0500 +Message-Id: <20210617164212.584-4-mario.limonciello@amd.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210617164212.584-1-mario.limonciello@amd.com> +References: <20210617164212.584-1-mario.limonciello@amd.com> +Content-Transfer-Encoding: 8bit +Content-Type: text/plain +X-Originating-IP: [76.251.167.31] +X-ClientProxiedBy: SN6PR05CA0006.namprd05.prod.outlook.com + (2603:10b6:805:de::19) To SA0PR12MB4510.namprd12.prod.outlook.com + (2603:10b6:806:94::8) +MIME-Version: 1.0 +X-MS-Exchange-MessageSentRepresentingType: 1 +Received: from AUS-LX-MLIMONCI.amd.com (76.251.167.31) by SN6PR05CA0006.namprd05.prod.outlook.com (2603:10b6:805:de::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4264.7 via Frontend Transport; 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+ ++/* Microsoft platform agnostic UUID */ ++#define ACPI_LPS0_DSM_UUID_MICROSOFT "11e00d56-ce64-47ce-837b-1f898f9aa461" ++ + #define ACPI_LPS0_DSM_UUID "c4eb40a0-6cd2-11e2-bcfd-0800200c9a66" + + #define ACPI_LPS0_GET_DEVICE_CONSTRAINTS 1 +@@ -39,6 +42,8 @@ static const struct acpi_device_id lps0_device_ids[] = { + #define ACPI_LPS0_SCREEN_ON 4 + #define ACPI_LPS0_ENTRY 5 + #define ACPI_LPS0_EXIT 6 ++#define ACPI_LPS0_MS_ENTRY 7 ++#define ACPI_LPS0_MS_EXIT 8 + + /* AMD */ + #define ACPI_LPS0_DSM_UUID_AMD "e3f32452-febc-43ce-9039-932122d37721" +@@ -51,6 +56,9 @@ static acpi_handle lps0_device_handle; + static guid_t lps0_dsm_guid; + static int lps0_dsm_func_mask; + ++static guid_t lps0_dsm_guid_microsoft; ++static int lps0_dsm_func_mask_microsoft; ++ + /* Device constraint entry structure */ + struct lpi_device_info { + char *name; +@@ -366,14 +374,18 @@ static int lps0_device_attach(struct acpi_device *adev, + rev_id = 0; + lps0_dsm_func_mask = validate_dsm(adev->handle, + ACPI_LPS0_DSM_UUID_AMD, rev_id, &lps0_dsm_guid); ++ lps0_dsm_func_mask_microsoft = validate_dsm(adev->handle, ++ ACPI_LPS0_DSM_UUID_MICROSOFT, rev_id, ++ &lps0_dsm_guid_microsoft); + } else { + rev_id = 1; + lps0_dsm_func_mask = validate_dsm(adev->handle, + ACPI_LPS0_DSM_UUID, rev_id, &lps0_dsm_guid); ++ lps0_dsm_func_mask_microsoft = -EINVAL; + } + +- if (lps0_dsm_func_mask < 0) +- return 0;//function eval failed ++ if (lps0_dsm_func_mask < 0 && lps0_dsm_func_mask_microsoft < 0) ++ return 0; //function evaluation failed + + lps0_device_handle = adev->handle; + +@@ -412,7 +424,14 @@ int acpi_s2idle_prepare_late(void) + if (pm_debug_messages_on) + lpi_check_constraints(); + +- if (acpi_s2idle_vendor_amd()) { ++ if (lps0_dsm_func_mask_microsoft > 0) { ++ acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_OFF, ++ lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft); ++ acpi_sleep_run_lps0_dsm(ACPI_LPS0_MS_EXIT, ++ lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft); ++ acpi_sleep_run_lps0_dsm(ACPI_LPS0_ENTRY, ++ lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft); ++ } else if (acpi_s2idle_vendor_amd()) { + acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_OFF_AMD, + lps0_dsm_func_mask, lps0_dsm_guid); + acpi_sleep_run_lps0_dsm(ACPI_LPS0_ENTRY_AMD, +@@ -432,7 +451,14 @@ void acpi_s2idle_restore_early(void) + if (!lps0_device_handle || sleep_no_lps0) + return; + +- if (acpi_s2idle_vendor_amd()) { ++ if (lps0_dsm_func_mask_microsoft > 0) { ++ acpi_sleep_run_lps0_dsm(ACPI_LPS0_EXIT, ++ lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft); ++ acpi_sleep_run_lps0_dsm(ACPI_LPS0_MS_ENTRY, ++ lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft); ++ acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_ON, ++ lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft); ++ } else if (acpi_s2idle_vendor_amd()) { + acpi_sleep_run_lps0_dsm(ACPI_LPS0_EXIT_AMD, + lps0_dsm_func_mask, lps0_dsm_guid); + acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_ON_AMD, +-- +2.25.1 + + diff --git a/sys-kernel_arch-sources-g14_files-0027-5.14-5of5-ACPI-PM-s2idle-Adjust-behavior-for-field-problems-on-AMD-systems.patch b/sys-kernel_arch-sources-g14_files-0027-5.14-5of5-ACPI-PM-s2idle-Adjust-behavior-for-field-problems-on-AMD-systems.patch new file mode 100644 index 000000000000..4d3ae9343976 --- /dev/null +++ b/sys-kernel_arch-sources-g14_files-0027-5.14-5of5-ACPI-PM-s2idle-Adjust-behavior-for-field-problems-on-AMD-systems.patch @@ -0,0 +1,168 @@ +From mboxrd@z Thu Jan 1 00:00:00 1970 +Return-Path: <linux-acpi-owner@kernel.org> +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, + DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, + INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, + SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id E7289C48BE5 + for <linux-acpi@archiver.kernel.org>; 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Wysocki" <rjw@rjwysocki.net>, + Len Brown <lenb@kernel.org>, linux-acpi@vger.kernel.org +Cc: Julian Sikorski <belegdol@gmail.com>, teohhanhui@gmail.com, + Shyam-sundar.S-k@amd.com, + Mario Limonciello <mario.limonciello@amd.com> +Subject: [PATCH 5/5] ACPI: PM: Adjust behavior for field problems on AMD systems +Date: Thu, 17 Jun 2021 11:42:12 -0500 +Message-Id: <20210617164212.584-5-mario.limonciello@amd.com> +X-Mailer: git-send-email 2.25.1 +In-Reply-To: <20210617164212.584-1-mario.limonciello@amd.com> +References: <20210617164212.584-1-mario.limonciello@amd.com> +Content-Transfer-Encoding: 8bit +Content-Type: text/plain +X-Originating-IP: [76.251.167.31] +X-ClientProxiedBy: SN6PR05CA0006.namprd05.prod.outlook.com + (2603:10b6:805:de::19) To SA0PR12MB4510.namprd12.prod.outlook.com + (2603:10b6:806:94::8) +MIME-Version: 1.0 +X-MS-Exchange-MessageSentRepresentingType: 1 +Received: from AUS-LX-MLIMONCI.amd.com (76.251.167.31) by SN6PR05CA0006.namprd05.prod.outlook.com (2603:10b6:805:de::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4264.7 via Frontend Transport; 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This means that they will call entrance +but not exit for matching functions. + +Other AMD systems with this HID should use the Microsoft generic UUID. + +AMD systems with uPEP HID AMDI006 should be using the Microsoft method. + +Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> +--- + drivers/acpi/x86/s2idle.c | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +diff --git a/drivers/acpi/x86/s2idle.c b/drivers/acpi/x86/s2idle.c +index 3f2a90648ec9..816bf2c34b7a 100644 +--- a/drivers/acpi/x86/s2idle.c ++++ b/drivers/acpi/x86/s2idle.c +@@ -371,12 +371,27 @@ static int lps0_device_attach(struct acpi_device *adev, + return 0; + + if (acpi_s2idle_vendor_amd()) { ++ /* AMD0004, AMDI0005: ++ * - Should use rev_id 0x0 ++ * - function mask > 0x3: Should use AMD method, but has off by one bug ++ * - function mask = 0x3: Should use Microsoft method ++ * AMDI0006: ++ * - should use rev_id 0x0 ++ * - function mask = 0x3: Should use Microsoft method ++ */ ++ const char *hid = acpi_device_hid(adev); + rev_id = 0; + lps0_dsm_func_mask = validate_dsm(adev->handle, + ACPI_LPS0_DSM_UUID_AMD, rev_id, &lps0_dsm_guid); + lps0_dsm_func_mask_microsoft = validate_dsm(adev->handle, + ACPI_LPS0_DSM_UUID_MICROSOFT, rev_id, + &lps0_dsm_guid_microsoft); ++ if (lps0_dsm_func_mask > 0x3 && (!strcmp(hid, "AMD0004") || ++ !strcmp(hid, "AMDI0005"))) { ++ lps0_dsm_func_mask = (lps0_dsm_func_mask << 1) | 0x1; ++ acpi_handle_debug(adev->handle, "_DSM UUID %s: Adjusted function mask: 0x%x\n", ++ ACPI_LPS0_DSM_UUID_AMD, lps0_dsm_func_mask); ++ } + } else { + rev_id = 1; + lps0_dsm_func_mask = validate_dsm(adev->handle, +-- +2.25.1 + + diff --git a/sys-kernel_arch-sources-g14_files-0028-platform-x86-amd-pmc-Fix-command-completion-code.patch b/sys-kernel_arch-sources-g14_files-0028-platform-x86-amd-pmc-Fix-command-completion-code.patch new file mode 100644 index 000000000000..fd71de16e19e --- /dev/null +++ b/sys-kernel_arch-sources-g14_files-0028-platform-x86-amd-pmc-Fix-command-completion-code.patch @@ -0,0 +1,52 @@ +From 375675bfe045e2c3911d6cc5f13281e388ee3544 Mon Sep 17 00:00:00 2001 +From: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> +Date: Thu, 17 Jun 2021 17:00:35 +0530 +Subject: [PATCH] platform/x86: amd-pmc: Fix command completion code + +The protocol to submit a job request to SMU is to wait for +AMD_PMC_REGISTER_RESPONSE to return 1,meaning SMU is ready to take +requests. PMC driver has to make sure that the response code is always +AMD_PMC_RESULT_OK before making any command submissions. + +Also, when we submit a message to SMU, we have to wait until it processes +the request. Adding a read_poll_timeout() check as this was missing in +the existing code. + +Fixes: 156ec4731cb2 ("platform/x86: amd-pmc: Add AMD platform support for S2Idle") +Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> +Reviewed-by: Hans de Goede <hdegoede@redhat.com> +--- + drivers/platform/x86/amd-pmc.c | 10 +++++++++- + 1 file changed, 9 insertions(+), 1 deletion(-) + +diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c +index b9da58ee9b1e..9c8a53120767 100644 +--- a/drivers/platform/x86/amd-pmc.c ++++ b/drivers/platform/x86/amd-pmc.c +@@ -140,7 +140,7 @@ static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set) + + /* Wait until we get a valid response */ + rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE, +- val, val > 0, PMC_MSG_DELAY_MIN_US, ++ val, val == AMD_PMC_RESULT_OK, PMC_MSG_DELAY_MIN_US, + PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX); + if (rc) { + dev_err(dev->dev, "failed to talk to SMU\n"); +@@ -156,6 +156,14 @@ static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set) + /* Write message ID to message ID register */ + msg = (dev->cpu_id == AMD_CPU_ID_RN) ? MSG_OS_HINT_RN : MSG_OS_HINT_PCO; + amd_pmc_reg_write(dev, AMD_PMC_REGISTER_MESSAGE, msg); ++ /* Wait until we get a valid response */ ++ rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE, ++ val, val == AMD_PMC_RESULT_OK, PMC_MSG_DELAY_MIN_US, ++ PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX); ++ if (rc) { ++ dev_err(dev->dev, "SMU response timed out\n"); ++ return rc; ++ } + return 0; + } + +-- +GitLab + diff --git a/sys-kernel_arch-sources-g14_files-0029-platform-x86-amd-pmc-Fix-SMU-firmware-reporting-mechanism.patch b/sys-kernel_arch-sources-g14_files-0029-platform-x86-amd-pmc-Fix-SMU-firmware-reporting-mechanism.patch new file mode 100644 index 000000000000..b5246110db6f --- /dev/null +++ b/sys-kernel_arch-sources-g14_files-0029-platform-x86-amd-pmc-Fix-SMU-firmware-reporting-mechanism.patch @@ -0,0 +1,89 @@ +From 5a1cb72ae0adb1249594de47f6a8e6ef77ce173a Mon Sep 17 00:00:00 2001 +From: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> +Date: Thu, 17 Jun 2021 17:00:36 +0530 +Subject: [PATCH] platform/x86: amd-pmc: Fix SMU firmware reporting mechanism + +It was lately understood that the current mechanism available in the +driver to get SMU firmware info works only on internal SMU builds and +there is a separate way to get all the SMU logging counters (addressed +in the next patch). Hence remove all the smu info shown via debugfs as it +is no more useful. + +Also, use dump registers routine only at one place i.e. after the command +submission to SMU is done. + +Fixes: 156ec4731cb2 ("platform/x86: amd-pmc: Add AMD platform support for S2Idle") +Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> +--- + drivers/platform/x86/amd-pmc.c | 15 +-------------- + 1 file changed, 1 insertion(+), 14 deletions(-) + +diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c +index 9c8a53120767..ce0e2ad94d09 100644 +--- a/drivers/platform/x86/amd-pmc.c ++++ b/drivers/platform/x86/amd-pmc.c +@@ -52,7 +52,6 @@ + #define AMD_CPU_ID_PCO AMD_CPU_ID_RV + #define AMD_CPU_ID_CZN AMD_CPU_ID_RN + +-#define AMD_SMU_FW_VERSION 0x0 + #define PMC_MSG_DELAY_MIN_US 100 + #define RESPONSE_REGISTER_LOOP_MAX 200 + +@@ -88,11 +87,6 @@ static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u3 + #ifdef CONFIG_DEBUG_FS + static int smu_fw_info_show(struct seq_file *s, void *unused) + { +- struct amd_pmc_dev *dev = s->private; +- u32 value; +- +- value = ioread32(dev->smu_base + AMD_SMU_FW_VERSION); +- seq_printf(s, "SMU FW Info: %x\n", value); + return 0; + } + DEFINE_SHOW_ATTRIBUTE(smu_fw_info); +@@ -164,6 +158,7 @@ static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set) + dev_err(dev->dev, "SMU response timed out\n"); + return rc; + } ++ amd_pmc_dump_registers(dev); + return 0; + } + +@@ -176,7 +171,6 @@ static int __maybe_unused amd_pmc_suspend(struct device *dev) + if (rc) + dev_err(pdev->dev, "suspend failed\n"); + +- amd_pmc_dump_registers(pdev); + return 0; + } + +@@ -189,7 +183,6 @@ static int __maybe_unused amd_pmc_resume(struct device *dev) + if (rc) + dev_err(pdev->dev, "resume failed\n"); + +- amd_pmc_dump_registers(pdev); + return 0; + } + +@@ -256,17 +249,11 @@ static int amd_pmc_probe(struct platform_device *pdev) + pci_dev_put(rdev); + base_addr = ((u64)base_addr_hi << 32 | base_addr_lo); + +- dev->smu_base = devm_ioremap(dev->dev, base_addr, AMD_PMC_MAPPING_SIZE); +- if (!dev->smu_base) +- return -ENOMEM; +- + dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET, + AMD_PMC_MAPPING_SIZE); + if (!dev->regbase) + return -ENOMEM; + +- amd_pmc_dump_registers(dev); +- + platform_set_drvdata(pdev, dev); + amd_pmc_dbgfs_register(dev); + return 0; +-- +GitLab + diff --git a/sys-kernel_arch-sources-g14_files-0030-platform-x86-amd-pmc-Add-support-for-logging-SMU-metrics.patch b/sys-kernel_arch-sources-g14_files-0030-platform-x86-amd-pmc-Add-support-for-logging-SMU-metrics.patch new file mode 100644 index 000000000000..6b2eaa3df76c --- /dev/null +++ b/sys-kernel_arch-sources-g14_files-0030-platform-x86-amd-pmc-Add-support-for-logging-SMU-metrics.patch @@ -0,0 +1,278 @@ +From 7852d1ee80a2a74278e6216a1196df734c5c1760 Mon Sep 17 00:00:00 2001 +From: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> +Date: Thu, 17 Jun 2021 17:00:37 +0530 +Subject: [PATCH] platform/x86: amd-pmc: Add support for logging SMU metrics + +SMU provides a way to dump the s0ix debug statistics in the form of a +metrics table via a of set special mailbox commands. + +Add support to the driver which can send these commands to SMU and expose +the information received via debugfs. The information contains the s0ix +entry/exit, active time of each IP block etc. + +As a side note, SMU subsystem logging is not supported on Picasso based +SoC's. + +Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> +--- + drivers/platform/x86/amd-pmc.c | 148 +++++++++++++++++++++++++++++++-- + 1 file changed, 140 insertions(+), 8 deletions(-) + +diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c +index ce0e2ad94d09..bb067324644d 100644 +--- a/drivers/platform/x86/amd-pmc.c ++++ b/drivers/platform/x86/amd-pmc.c +@@ -46,6 +46,14 @@ + #define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE + #define AMD_PMC_RESULT_FAILED 0xFF + ++/* SMU Message Definations */ ++#define SMU_MSG_GETSMUVERSION 0x02 ++#define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04 ++#define SMU_MSG_LOG_GETDRAM_ADDR_LO 0x05 ++#define SMU_MSG_LOG_START 0x06 ++#define SMU_MSG_LOG_RESET 0x07 ++#define SMU_MSG_LOG_DUMP_DATA 0x08 ++#define SMU_MSG_GET_SUP_CONSTRAINTS 0x09 + /* List of supported CPU ids */ + #define AMD_CPU_ID_RV 0x15D0 + #define AMD_CPU_ID_RN 0x1630 +@@ -55,17 +63,42 @@ + #define PMC_MSG_DELAY_MIN_US 100 + #define RESPONSE_REGISTER_LOOP_MAX 200 + ++#define SOC_SUBSYSTEM_IP_MAX 12 ++#define DELAY_MIN_US 2000 ++#define DELAY_MAX_US 3000 + enum amd_pmc_def { + MSG_TEST = 0x01, + MSG_OS_HINT_PCO, + MSG_OS_HINT_RN, + }; + ++struct amd_pmc_bit_map { ++ const char *name; ++ u32 bit_mask; ++}; ++ ++static const struct amd_pmc_bit_map soc15_ip_blk[] = { ++ {"DISPLAY", BIT(0)}, ++ {"CPU", BIT(1)}, ++ {"GFX", BIT(2)}, ++ {"VDD", BIT(3)}, ++ {"ACP", BIT(4)}, ++ {"VCN", BIT(5)}, ++ {"ISP", BIT(6)}, ++ {"NBIO", BIT(7)}, ++ {"DF", BIT(8)}, ++ {"USB0", BIT(9)}, ++ {"USB1", BIT(10)}, ++ {"LAPIC", BIT(11)}, ++ {} ++}; ++ + struct amd_pmc_dev { + void __iomem *regbase; +- void __iomem *smu_base; ++ void __iomem *smu_virt_addr; + u32 base_addr; + u32 cpu_id; ++ u32 active_ips; + struct device *dev; + #if IS_ENABLED(CONFIG_DEBUG_FS) + struct dentry *dbgfs_dir; +@@ -73,6 +106,7 @@ struct amd_pmc_dev { + }; + + static struct amd_pmc_dev pmc; ++static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set, u32 *data, u8 msg, bool ret); + + static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset) + { +@@ -84,9 +118,50 @@ static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u3 + iowrite32(val, dev->regbase + reg_offset); + } + ++struct smu_metrics { ++ u32 table_version; ++ u32 hint_count; ++ u32 s0i3_cyclecount; ++ u32 timein_s0i2; ++ u64 timeentering_s0i3_lastcapture; ++ u64 timeentering_s0i3_totaltime; ++ u64 timeto_resume_to_os_lastcapture; ++ u64 timeto_resume_to_os_totaltime; ++ u64 timein_s0i3_lastcapture; ++ u64 timein_s0i3_totaltime; ++ u64 timein_swdrips_lastcapture; ++ u64 timein_swdrips_totaltime; ++ u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX]; ++ u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX]; ++} __packed; ++ + #ifdef CONFIG_DEBUG_FS + static int smu_fw_info_show(struct seq_file *s, void *unused) + { ++ struct amd_pmc_dev *dev = s->private; ++ struct smu_metrics table; ++ u32 value; ++ int idx; ++ ++ if (dev->cpu_id == AMD_CPU_ID_PCO) ++ return -EINVAL; ++ ++ memcpy_fromio(&table, dev->smu_virt_addr, sizeof(struct smu_metrics)); ++ ++ seq_puts(s, "\n=== SMU Statistics ===\n"); ++ seq_printf(s, "Table Version: %d\n", table.table_version); ++ seq_printf(s, "Hint Count: %d\n", table.hint_count); ++ seq_printf(s, "S0i3 Cycle Count: %d\n", table.s0i3_cyclecount); ++ seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture); ++ seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture); ++ ++ seq_puts(s, "\n=== Active time (in us) ===\n"); ++ for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) { ++ if (soc15_ip_blk[idx].bit_mask & dev->active_ips) ++ seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name, ++ table.timecondition_notmet_lastcapture[idx]); ++ } ++ + return 0; + } + DEFINE_SHOW_ATTRIBUTE(smu_fw_info); +@@ -112,6 +187,32 @@ static inline void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev) + } + #endif /* CONFIG_DEBUG_FS */ + ++static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev) ++{ ++ u32 phys_addr_low, phys_addr_hi; ++ u64 smu_phys_addr; ++ ++ if (dev->cpu_id == AMD_CPU_ID_PCO) ++ return -EINVAL; ++ ++ /* Get Active devices list from SMU */ ++ amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, 1); ++ ++ /* Get dram address */ ++ amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, 1); ++ amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, 1); ++ smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low); ++ ++ dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr, sizeof(struct smu_metrics)); ++ if (!dev->smu_virt_addr) ++ return -ENOMEM; ++ ++ /* Start the logging */ ++ amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, 0); ++ ++ return 0; ++} ++ + static void amd_pmc_dump_registers(struct amd_pmc_dev *dev) + { + u32 value; +@@ -126,10 +227,9 @@ static void amd_pmc_dump_registers(struct amd_pmc_dev *dev) + dev_dbg(dev->dev, "AMD_PMC_REGISTER_MESSAGE:%x\n", value); + } + +-static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set) ++static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set, u32 *data, u8 msg, bool ret) + { + int rc; +- u8 msg; + u32 val; + + /* Wait until we get a valid response */ +@@ -148,8 +248,8 @@ static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set) + amd_pmc_reg_write(dev, AMD_PMC_REGISTER_ARGUMENT, set); + + /* Write message ID to message ID register */ +- msg = (dev->cpu_id == AMD_CPU_ID_RN) ? MSG_OS_HINT_RN : MSG_OS_HINT_PCO; + amd_pmc_reg_write(dev, AMD_PMC_REGISTER_MESSAGE, msg); ++ + /* Wait until we get a valid response */ + rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE, + val, val == AMD_PMC_RESULT_OK, PMC_MSG_DELAY_MIN_US, +@@ -158,16 +258,40 @@ static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set) + dev_err(dev->dev, "SMU response timed out\n"); + return rc; + } ++ ++ if (ret) { ++ /* PMFW may take longer time to return back the data */ ++ usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US); ++ *data = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_ARGUMENT); ++ } ++ + amd_pmc_dump_registers(dev); + return 0; + } + ++static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev) ++{ ++ switch (dev->cpu_id) { ++ case AMD_CPU_ID_PCO: ++ return MSG_OS_HINT_PCO; ++ case AMD_CPU_ID_RN: ++ return MSG_OS_HINT_RN; ++ } ++ return -EINVAL; ++} ++ + static int __maybe_unused amd_pmc_suspend(struct device *dev) + { + struct amd_pmc_dev *pdev = dev_get_drvdata(dev); + int rc; ++ u8 msg; ++ ++ /* Reset and Start SMU logging - to monitor the s0i3 stats */ ++ amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_RESET, 0); ++ amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_START, 0); + +- rc = amd_pmc_send_cmd(pdev, 1); ++ msg = amd_pmc_get_os_hint(pdev); ++ rc = amd_pmc_send_cmd(pdev, 1, NULL, msg, 0); + if (rc) + dev_err(pdev->dev, "suspend failed\n"); + +@@ -178,8 +302,13 @@ static int __maybe_unused amd_pmc_resume(struct device *dev) + { + struct amd_pmc_dev *pdev = dev_get_drvdata(dev); + int rc; ++ u8 msg; ++ ++ /* Let SMU know that we are looking for stats */ ++ amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, 0); + +- rc = amd_pmc_send_cmd(pdev, 0); ++ msg = amd_pmc_get_os_hint(pdev); ++ rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, 0); + if (rc) + dev_err(pdev->dev, "resume failed\n"); + +@@ -202,8 +331,7 @@ static int amd_pmc_probe(struct platform_device *pdev) + { + struct amd_pmc_dev *dev = &pmc; + struct pci_dev *rdev; +- u32 base_addr_lo; +- u32 base_addr_hi; ++ u32 base_addr_lo, base_addr_hi; + u64 base_addr; + int err; + u32 val; +@@ -254,6 +382,10 @@ static int amd_pmc_probe(struct platform_device *pdev) + if (!dev->regbase) + return -ENOMEM; + ++ /* Use SMU to get the s0i3 debug stats */ ++ err = amd_pmc_setup_smu_logging(dev); ++ if (err) ++ dev_err(dev->dev, "SMU debugging info not supported on this platform\n"); + platform_set_drvdata(pdev, dev); + amd_pmc_dbgfs_register(dev); + return 0; +-- +GitLab + diff --git a/sys-kernel_arch-sources-g14_files-0031-platform-x86-amd-pmc-Add-support-for-s0ix-counters.patch b/sys-kernel_arch-sources-g14_files-0031-platform-x86-amd-pmc-Add-support-for-s0ix-counters.patch new file mode 100644 index 000000000000..654b1cb98216 --- /dev/null +++ b/sys-kernel_arch-sources-g14_files-0031-platform-x86-amd-pmc-Add-support-for-s0ix-counters.patch @@ -0,0 +1,123 @@ +From a09d88cec0a5dc088d7859433f2027aad4c68ff4 Mon Sep 17 00:00:00 2001 +From: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> +Date: Thu, 17 Jun 2021 17:00:38 +0530 +Subject: [PATCH] platform/x86: amd-pmc: Add support for logging s0ix counters + +Even the FCH SSC registers provides certain level of information +about the s0ix entry and exit times which comes handy when the SMU +fails to report the statistics via the mailbox communication. + +This information is captured via a new debugfs file "s0ix_stats". +A non-zero entry in this counters would mean that the system entered +the s0ix state. + +If s0ix entry time and exit time don't change during suspend to idle, +the silicon has not entered the deepest state. + +Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> +--- + drivers/platform/x86/amd-pmc.c | 46 ++++++++++++++++++++++++++++++++-- + 1 file changed, 44 insertions(+), 2 deletions(-) + +diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c +index bb067324644d..174f067f0756 100644 +--- a/drivers/platform/x86/amd-pmc.c ++++ b/drivers/platform/x86/amd-pmc.c +@@ -46,6 +46,15 @@ + #define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE + #define AMD_PMC_RESULT_FAILED 0xFF + ++/* FCH SSC Registers */ ++#define FCH_S0I3_ENTRY_TIME_L_OFFSET 0x30 ++#define FCH_S0I3_ENTRY_TIME_H_OFFSET 0x34 ++#define FCH_S0I3_EXIT_TIME_L_OFFSET 0x38 ++#define FCH_S0I3_EXIT_TIME_H_OFFSET 0x3C ++#define FCH_SSC_MAPPING_SIZE 0x800 ++#define FCH_BASE_PHY_ADDR_LOW 0xFED81100 ++#define FCH_BASE_PHY_ADDR_HIGH 0x00000000 ++ + /* SMU Message Definations */ + #define SMU_MSG_GETSMUVERSION 0x02 + #define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04 +@@ -96,6 +105,7 @@ static const struct amd_pmc_bit_map soc15_ip_blk[] = { + struct amd_pmc_dev { + void __iomem *regbase; + void __iomem *smu_virt_addr; ++ void __iomem *fch_virt_addr; + u32 base_addr; + u32 cpu_id; + u32 active_ips; +@@ -140,7 +150,6 @@ static int smu_fw_info_show(struct seq_file *s, void *unused) + { + struct amd_pmc_dev *dev = s->private; + struct smu_metrics table; +- u32 value; + int idx; + + if (dev->cpu_id == AMD_CPU_ID_PCO) +@@ -166,6 +175,29 @@ static int smu_fw_info_show(struct seq_file *s, void *unused) + } + DEFINE_SHOW_ATTRIBUTE(smu_fw_info); + ++static int s0ix_stats_show(struct seq_file *s, void *unused) ++{ ++ struct amd_pmc_dev *dev = s->private; ++ u64 entry_time, exit_time, residency; ++ ++ entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET); ++ entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET); ++ ++ exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET); ++ exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET); ++ ++ /* It's in 48MHz. We need to convert it to unit of 100ns */ ++ residency = (exit_time - entry_time) * 10 / 48; ++ ++ seq_puts(s, "=== S0ix statistics ===\n"); ++ seq_printf(s, "S0ix Entry Time: %lld\n", entry_time); ++ seq_printf(s, "S0ix Exit Time: %lld\n", exit_time); ++ seq_printf(s, "Residency Time: %lld\n", residency); ++ ++ return 0; ++} ++DEFINE_SHOW_ATTRIBUTE(s0ix_stats); ++ + static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev) + { + debugfs_remove_recursive(dev->dbgfs_dir); +@@ -176,6 +208,8 @@ static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev) + dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL); + debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev, + &smu_fw_info_fops); ++ debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev, ++ &s0ix_stats_fops); + } + #else + static inline void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev) +@@ -332,7 +366,7 @@ static int amd_pmc_probe(struct platform_device *pdev) + struct amd_pmc_dev *dev = &pmc; + struct pci_dev *rdev; + u32 base_addr_lo, base_addr_hi; +- u64 base_addr; ++ u64 base_addr, fch_phys_addr; + int err; + u32 val; + +@@ -382,6 +416,14 @@ static int amd_pmc_probe(struct platform_device *pdev) + if (!dev->regbase) + return -ENOMEM; + ++ /* Use FCH registers to get the S0ix stats */ ++ base_addr_lo = FCH_BASE_PHY_ADDR_LOW; ++ base_addr_hi = FCH_BASE_PHY_ADDR_HIGH; ++ fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo); ++ dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE); ++ if (!dev->fch_virt_addr) ++ return -ENOMEM; ++ + /* Use SMU to get the s0i3 debug stats */ + err = amd_pmc_setup_smu_logging(dev); + if (err) +-- +GitLab + diff --git a/sys-kernel_arch-sources-g14_files-0032-platform-x86-amd-pmc-Add-support-for-ACPI-ID-AMDI0006.patch b/sys-kernel_arch-sources-g14_files-0032-platform-x86-amd-pmc-Add-support-for-ACPI-ID-AMDI0006.patch new file mode 100644 index 000000000000..65412a2a35cd --- /dev/null +++ b/sys-kernel_arch-sources-g14_files-0032-platform-x86-amd-pmc-Add-support-for-ACPI-ID-AMDI0006.patch @@ -0,0 +1,28 @@ +From 7f0b4e8abb8921faf082fbcff96600f54de669f7 Mon Sep 17 00:00:00 2001 +From: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> +Date: Thu, 17 Jun 2021 17:00:39 +0530 +Subject: [PATCH] platform/x86: amd-pmc: Add support for ACPI ID AMDI0006 + +Some newer BIOSes have added another ACPI ID for the uPEP device. +SMU statistics behave identically on this device. + +Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> +--- + drivers/platform/x86/amd-pmc.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c +index 174f067f0756..e024fd36bd26 100644 +--- a/drivers/platform/x86/amd-pmc.c ++++ b/drivers/platform/x86/amd-pmc.c +@@ -443,6 +443,7 @@ static int amd_pmc_remove(struct platform_device *pdev) + + static const struct acpi_device_id amd_pmc_acpi_ids[] = { + {"AMDI0005", 0}, ++ {"AMDI0006", 0}, + {"AMD0004", 0}, + { } + }; +-- +GitLab + diff --git a/sys-kernel_arch-sources-g14_files-0033-platform-x86-amd-pmc-Add-new-acpi-for-future-PMC.patch b/sys-kernel_arch-sources-g14_files-0033-platform-x86-amd-pmc-Add-new-acpi-for-future-PMC.patch new file mode 100644 index 000000000000..0328872e9059 --- /dev/null +++ b/sys-kernel_arch-sources-g14_files-0033-platform-x86-amd-pmc-Add-new-acpi-for-future-PMC.patch @@ -0,0 +1,53 @@ +From 6230d05e0540b47ae8334c1b3a1a2e8fa57db379 Mon Sep 17 00:00:00 2001 +From: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> +Date: Thu, 17 Jun 2021 17:00:40 +0530 +Subject: [PATCH] platform/x86: amd-pmc: Add new acpi id for future PMC + controllers + +The upcoming PMC controller would have a newer acpi id, add that to +the supported acpid device list. + +Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> +--- + drivers/platform/x86/amd-pmc.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c +index e024fd36bd26..c26ac561c0d4 100644 +--- a/drivers/platform/x86/amd-pmc.c ++++ b/drivers/platform/x86/amd-pmc.c +@@ -68,6 +68,7 @@ + #define AMD_CPU_ID_RN 0x1630 + #define AMD_CPU_ID_PCO AMD_CPU_ID_RV + #define AMD_CPU_ID_CZN AMD_CPU_ID_RN ++#define AMD_CPU_ID_YC 0x14B5 + + #define PMC_MSG_DELAY_MIN_US 100 + #define RESPONSE_REGISTER_LOOP_MAX 200 +@@ -309,6 +310,7 @@ static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev) + case AMD_CPU_ID_PCO: + return MSG_OS_HINT_PCO; + case AMD_CPU_ID_RN: ++ case AMD_CPU_ID_YC: + return MSG_OS_HINT_RN; + } + return -EINVAL; +@@ -354,6 +356,7 @@ static const struct dev_pm_ops amd_pmc_pm_ops = { + }; + + static const struct pci_device_id pmc_pci_ids[] = { ++ { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) }, +@@ -444,6 +447,7 @@ static int amd_pmc_remove(struct platform_device *pdev) + static const struct acpi_device_id amd_pmc_acpi_ids[] = { + {"AMDI0005", 0}, + {"AMDI0006", 0}, ++ {"AMDI0007", 0}, + {"AMD0004", 0}, + { } + }; +-- +GitLab + |