pkgbuild & patch: add AC200-EPHY enable patch and fixed PKGBUILD

9 files changed, 1033 insertions, 6 deletions

diff --git a/.SRCINFO b/.SRCINFO
index 727277f3e023..022ff51cba1e 100644
--- a/.SRCINFO
+++ b/.SRCINFO
@@ -1,6 +1,6 @@
 pkgbase = linux-tqc-a01
 	pkgver = 5.11.4
-	pkgrel = 3
+	pkgrel = 4
 	url = http://www.kernel.org/
 	arch = aarch64
 	license = GPL2
@@ -16,12 +16,18 @@ pkgbase = linux-tqc-a01
 	options = !strip
 	source = http://cdn.kernel.org/pub/linux/kernel/v5.x/linux-5.11.tar.xz
 	source = sun50i-h6-tqc-a01.dts
+	source = 0001-mfd-Add-support-for-AC200.patch
 	source = 0001-net-smsc95xx-Allow-mac-address-to-be-set-as-a-parame.patch
+	source = 0002-net-phy-Add-support-for-AC200-EPHY.patch
 	source = 0002-net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regu.patch
 	source = 0003-net-stmmac-sun8i-Rename-PHY-regulator-variable-to-re.patch
 	source = 0004-net-stmmac-sun8i-Add-support-for-enabling-a-regulato.patch
+	source = 0005-drm-gem-cma-Export-with-handle-allocator.patch
+	source = 0006-drm-sun4i-Add-GEM-allocator.patch
 	source = 0007-arm64-dts-allwinner-h6-Add-AC200-EPHY-related-nodes.patch
+	source = 0010-general-h6-add-dma-i2c-ir-spi-uart.patch
 	source = 0011-mmc-sunxi-fix-unusuable-eMMC-on-some-H6-boards-by-di.patch
+	source = fix-missing-H6-spi-pins.patch
 	source = config
 	source = kernel.its
 	source = kernel.keyblock
@@ -31,13 +37,19 @@ pkgbase = linux-tqc-a01
 	source = 90-linux.hook
 	source = https://cdn.kernel.org/pub/linux/kernel/v5.x/patch-5.11.4.xz
 	md5sums = d2985a3f16ef1ea3405c04c406e29dcc
-	md5sums = 3bf41e61be58e1cda848dd75983a0ea9
+	md5sums = 257beb93e91b190184f1a161f66d3206
+	md5sums = 17aa0c69176c68cd98b4522740a1b747
 	md5sums = f9b6f367eef351eaa89b23a9b1ffc5a2
+	md5sums = bc7904920675ba8d38f21d46ffac33b5
 	md5sums = 94a69594f90309c50c83a5cc8579fb54
 	md5sums = e1868e41094baff9eceba481fc097c79
 	md5sums = 5d42a68276c8f9e8b3de040fa2579b84
+	md5sums = 335382823f6dc2aae2f6038b7aee339e
+	md5sums = cb38b30491472097c3b9b475de39127f
 	md5sums = 6fd2f4aaa791c975aef5968f32eecb4c
+	md5sums = bc65c0b9e4d6fb2fe3a81b8358886885
 	md5sums = f27a8190e862a7edcf2b09cc27aef180
+	md5sums = 11dfddadb815a896a2db65812e66e6fa
 	md5sums = 5e0c36c663ebe0721fb96b9f2bfef451
 	md5sums = 7f1a96e24f5150f790df94398e9525a3
 	md5sums = 61c5ff73c136ed07a7aadbf58db3d96a
diff --git a/0001-mfd-Add-support-for-AC200.patch b/0001-mfd-Add-support-for-AC200.patch
new file mode 100644
index 000000000000..f74e3c209c36
--- /dev/null
+++ b/0001-mfd-Add-support-for-AC200.patch
@@ -0,0 +1,440 @@
+From d98aa318aabd4aba05328f9c832b23bdf2e1677a Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Fri, 16 Aug 2019 16:38:21 +0200
+Subject: [PATCH 1/4] mfd: Add support for AC200
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+---
+ drivers/mfd/Kconfig       |   9 ++
+ drivers/mfd/Makefile      |   1 +
+ drivers/mfd/ac200.c       | 170 +++++++++++++++++++++++++++++++
+ include/linux/mfd/ac200.h | 208 ++++++++++++++++++++++++++++++++++++++
+ 4 files changed, 388 insertions(+)
+ create mode 100644 drivers/mfd/ac200.c
+ create mode 100644 include/linux/mfd/ac200.h
+
+diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
+index 420900852166..a45e7c88ac9b 100644
+--- a/drivers/mfd/Kconfig
++++ b/drivers/mfd/Kconfig
+@@ -178,6 +178,15 @@ config MFD_AC100
+ 	  This driver include only the core APIs. You have to select individual
+ 	  components like codecs or RTC under the corresponding menus.
+ 
++config MFD_AC200
++	tristate "X-Powers AC200"
++	select MFD_CORE
++	depends on I2C
++	help
++	  If you say Y here you get support for the X-Powers AC200 IC.
++	  This driver include only the core APIs. You have to select individual
++	  components like Ethernet PHY or RTC under the corresponding menus.
++
+ config MFD_AXP20X
+ 	tristate
+ 	select MFD_CORE
+diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
+index aed99f08739f..4431a4cf19ca 100644
+--- a/drivers/mfd/Makefile
++++ b/drivers/mfd/Makefile
+@@ -141,6 +141,7 @@ obj-$(CONFIG_MFD_DA9052_SPI)	+= da9052-spi.o
+ obj-$(CONFIG_MFD_DA9052_I2C)	+= da9052-i2c.o
+ 
+ obj-$(CONFIG_MFD_AC100)		+= ac100.o
++obj-$(CONFIG_MFD_AC200)		+= ac200.o
+ obj-$(CONFIG_MFD_AXP20X)	+= axp20x.o
+ obj-$(CONFIG_MFD_AXP20X_I2C)	+= axp20x-i2c.o
+ obj-$(CONFIG_MFD_AXP20X_RSB)	+= axp20x-rsb.o
+diff --git a/drivers/mfd/ac200.c b/drivers/mfd/ac200.c
+new file mode 100644
+index 000000000000..570573790d91
+--- /dev/null
++++ b/drivers/mfd/ac200.c
+@@ -0,0 +1,170 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * MFD core driver for X-Powers' AC200 IC
++ *
++ * The AC200 is a chip which is co-packaged with Allwinner H6 SoC and
++ * includes analog audio codec, analog TV encoder, ethernet PHY, eFuse
++ * and RTC.
++ *
++ * Copyright (c) 2020 Jernej Skrabec <jernej.skrabec@siol.net>
++ */
++
++#include <linux/i2c.h>
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/mfd/core.h>
++#include <linux/mfd/ac200.h>
++#include <linux/module.h>
++#include <linux/of.h>
++
++/* Interrupts */
++#define AC200_IRQ_RTC  0
++#define AC200_IRQ_EPHY 1
++#define AC200_IRQ_TVE  2
++
++/* IRQ enable register */
++#define AC200_SYS_IRQ_ENABLE_OUT_EN BIT(15)
++#define AC200_SYS_IRQ_ENABLE_RTC    BIT(12)
++#define AC200_SYS_IRQ_ENABLE_EPHY   BIT(8)
++#define AC200_SYS_IRQ_ENABLE_TVE    BIT(4)
++
++static const struct regmap_range_cfg ac200_range_cfg[] = {
++	{
++		.range_min = AC200_SYS_VERSION,
++		.range_max = AC200_IC_CHARA1,
++		.selector_reg = AC200_TWI_REG_ADDR_H,
++		.selector_mask = 0xff,
++		.selector_shift = 0,
++		.window_start = 0,
++		.window_len = 256,
++	}
++};
++
++static const struct regmap_config ac200_regmap_config = {
++	.reg_bits	= 8,
++	.val_bits	= 16,
++	.ranges		= ac200_range_cfg,
++	.num_ranges	= ARRAY_SIZE(ac200_range_cfg),
++	.max_register	= AC200_IC_CHARA1,
++};
++
++static const struct regmap_irq ac200_regmap_irqs[] = {
++	REGMAP_IRQ_REG(AC200_IRQ_RTC,  0, AC200_SYS_IRQ_ENABLE_RTC),
++	REGMAP_IRQ_REG(AC200_IRQ_EPHY, 0, AC200_SYS_IRQ_ENABLE_EPHY),
++	REGMAP_IRQ_REG(AC200_IRQ_TVE,  0, AC200_SYS_IRQ_ENABLE_TVE),
++};
++
++static const struct regmap_irq_chip ac200_regmap_irq_chip = {
++	.name			= "ac200_irq_chip",
++	.status_base		= AC200_SYS_IRQ_STATUS,
++	.mask_base		= AC200_SYS_IRQ_ENABLE,
++	.mask_invert		= true,
++	.irqs			= ac200_regmap_irqs,
++	.num_irqs		= ARRAY_SIZE(ac200_regmap_irqs),
++	.num_regs		= 1,
++};
++
++static const struct resource ephy_resource[] = {
++	DEFINE_RES_IRQ(AC200_IRQ_EPHY),
++};
++
++static const struct mfd_cell ac200_cells[] = {
++	{
++		.name		= "ac200-ephy",
++		.num_resources	= ARRAY_SIZE(ephy_resource),
++		.resources	= ephy_resource,
++		.of_compatible	= "x-powers,ac200-ephy",
++	},
++};
++
++static int ac200_i2c_probe(struct i2c_client *i2c,
++			   const struct i2c_device_id *id)
++{
++	struct device *dev = &i2c->dev;
++	struct ac200_dev *ac200;
++	int ret;
++
++	ac200 = devm_kzalloc(dev, sizeof(*ac200), GFP_KERNEL);
++	if (!ac200)
++		return -ENOMEM;
++
++	i2c_set_clientdata(i2c, ac200);
++
++	ac200->regmap = devm_regmap_init_i2c(i2c, &ac200_regmap_config);
++	if (IS_ERR(ac200->regmap)) {
++		ret = PTR_ERR(ac200->regmap);
++		dev_err(dev, "regmap init failed: %d\n", ret);
++		return ret;
++	}
++
++	/* do a reset to put chip in a known state */
++
++	ret = regmap_write(ac200->regmap, AC200_SYS_CONTROL, 0);
++	if (ret)
++		return ret;
++
++	ret = regmap_write(ac200->regmap, AC200_SYS_CONTROL, 1);
++	if (ret)
++		return ret;
++
++	/* enable interrupt pin */
++
++	ret = regmap_write(ac200->regmap, AC200_SYS_IRQ_ENABLE,
++			   AC200_SYS_IRQ_ENABLE_OUT_EN);
++	if (ret)
++		return ret;
++
++	ret = regmap_add_irq_chip(ac200->regmap, i2c->irq, IRQF_ONESHOT, 0,
++				  &ac200_regmap_irq_chip, &ac200->regmap_irqc);
++	if (ret)
++		return ret;
++
++	ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, ac200_cells,
++				   ARRAY_SIZE(ac200_cells), NULL, 0, NULL);
++	if (ret) {
++		dev_err(dev, "failed to add MFD devices: %d\n", ret);
++		regmap_del_irq_chip(i2c->irq, ac200->regmap_irqc);
++		return ret;
++	}
++
++	return 0;
++}
++
++static int ac200_i2c_remove(struct i2c_client *i2c)
++{
++	struct ac200_dev *ac200 = i2c_get_clientdata(i2c);
++
++	regmap_write(ac200->regmap, AC200_SYS_CONTROL, 0);
++
++	mfd_remove_devices(&i2c->dev);
++	regmap_del_irq_chip(i2c->irq, ac200->regmap_irqc);
++
++	return 0;
++}
++
++static const struct i2c_device_id ac200_ids[] = {
++	{ "ac200", },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(i2c, ac200_ids);
++
++static const struct of_device_id ac200_of_match[] = {
++	{ .compatible = "x-powers,ac200" },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, ac200_of_match);
++
++static struct i2c_driver ac200_i2c_driver = {
++	.driver = {
++		.name	= "ac200",
++		.of_match_table	= of_match_ptr(ac200_of_match),
++	},
++	.probe	= ac200_i2c_probe,
++	.remove = ac200_i2c_remove,
++	.id_table = ac200_ids,
++};
++module_i2c_driver(ac200_i2c_driver);
++
++MODULE_DESCRIPTION("MFD core driver for AC200");
++MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>");
++MODULE_LICENSE("GPL v2");
+diff --git a/include/linux/mfd/ac200.h b/include/linux/mfd/ac200.h
+new file mode 100644
+index 000000000000..0c677094a5b3
+--- /dev/null
++++ b/include/linux/mfd/ac200.h
+@@ -0,0 +1,208 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++/*
++ * AC200 register list
++ *
++ * Copyright (C) 2019 Jernej Skrabec <jernej.skrabec@siol.net>
++ */
++
++#ifndef __LINUX_MFD_AC200_H
++#define __LINUX_MFD_AC200_H
++
++#include <linux/regmap.h>
++
++/* interface registers (can be accessed from any page) */
++#define AC200_TWI_CHANGE_TO_RSB		0x3E
++#define AC200_TWI_PAD_DELAY		0xC4
++#define AC200_TWI_REG_ADDR_H		0xFE
++
++/* General registers */
++#define AC200_SYS_VERSION		0x0000
++#define AC200_SYS_CONTROL		0x0002
++#define AC200_SYS_IRQ_ENABLE		0x0004
++#define AC200_SYS_IRQ_STATUS		0x0006
++#define AC200_SYS_CLK_CTL		0x0008
++#define AC200_SYS_DLDO_OSC_CTL		0x000A
++#define AC200_SYS_PLL_CTL0		0x000C
++#define AC200_SYS_PLL_CTL1		0x000E
++#define AC200_SYS_AUDIO_CTL0		0x0010
++#define AC200_SYS_AUDIO_CTL1		0x0012
++#define AC200_SYS_EPHY_CTL0		0x0014
++#define AC200_SYS_EPHY_CTL1		0x0016
++#define AC200_SYS_TVE_CTL0		0x0018
++#define AC200_SYS_TVE_CTL1		0x001A
++
++/* Audio Codec registers */
++#define AC200_AC_SYS_CLK_CTL		0x2000
++#define AC200_SYS_MOD_RST		0x2002
++#define AC200_SYS_SAMP_CTL		0x2004
++#define AC200_I2S_CTL			0x2100
++#define AC200_I2S_CLK			0x2102
++#define AC200_I2S_FMT0			0x2104
++#define AC200_I2S_FMT1			0x2108
++#define AC200_I2S_MIX_SRC		0x2114
++#define AC200_I2S_MIX_GAIN		0x2116
++#define AC200_I2S_DACDAT_DVC		0x2118
++#define AC200_I2S_ADCDAT_DVC		0x211A
++#define AC200_AC_DAC_DPC		0x2200
++#define AC200_AC_DAC_MIX_SRC		0x2202
++#define AC200_AC_DAC_MIX_GAIN		0x2204
++#define AC200_DACA_OMIXER_CTRL		0x2220
++#define AC200_OMIXER_SR			0x2222
++#define AC200_LINEOUT_CTRL		0x2224
++#define AC200_AC_ADC_DPC		0x2300
++#define AC200_MBIAS_CTRL		0x2310
++#define AC200_ADC_MIC_CTRL		0x2320
++#define AC200_ADCMIXER_SR		0x2322
++#define AC200_ANALOG_TUNING0		0x232A
++#define AC200_ANALOG_TUNING1		0x232C
++#define AC200_AC_AGC_SEL		0x2480
++#define AC200_ADC_DAPLCTRL		0x2500
++#define AC200_ADC_DAPRCTRL		0x2502
++#define AC200_ADC_DAPLSTA		0x2504
++#define AC200_ADC_DAPRSTA		0x2506
++#define AC200_ADC_DAPLTL		0x2508
++#define AC200_ADC_DAPRTL		0x250A
++#define AC200_ADC_DAPLHAC		0x250C
++#define AC200_ADC_DAPLLAC		0x250E
++#define AC200_ADC_DAPRHAC		0x2510
++#define AC200_ADC_DAPRLAC		0x2512
++#define AC200_ADC_DAPLDT		0x2514
++#define AC200_ADC_DAPLAT		0x2516
++#define AC200_ADC_DAPRDT		0x2518
++#define AC200_ADC_DAPRAT		0x251A
++#define AC200_ADC_DAPNTH		0x251C
++#define AC200_ADC_DAPLHNAC		0x251E
++#define AC200_ADC_DAPLLNAC		0x2520
++#define AC200_ADC_DAPRHNAC		0x2522
++#define AC200_ADC_DAPRLNAC		0x2524
++#define AC200_AC_DAPHHPFC		0x2526
++#define AC200_AC_DAPLHPFC		0x2528
++#define AC200_AC_DAPOPT			0x252A
++#define AC200_AC_DAC_DAPCTRL		0x3000
++#define AC200_AC_DRC_HHPFC		0x3002
++#define AC200_AC_DRC_LHPFC		0x3004
++#define AC200_AC_DRC_CTRL		0x3006
++#define AC200_AC_DRC_LPFHAT		0x3008
++#define AC200_AC_DRC_LPFLAT		0x300A
++#define AC200_AC_DRC_RPFHAT		0x300C
++#define AC200_AC_DRC_RPFLAT		0x300E
++#define AC200_AC_DRC_LPFHRT		0x3010
++#define AC200_AC_DRC_LPFLRT		0x3012
++#define AC200_AC_DRC_RPFHRT		0x3014
++#define AC200_AC_DRC_RPFLRT		0x3016
++#define AC200_AC_DRC_LRMSHAT		0x3018
++#define AC200_AC_DRC_LRMSLAT		0x301A
++#define AC200_AC_DRC_RRMSHAT		0x301C
++#define AC200_AC_DRC_RRMSLAT		0x301E
++#define AC200_AC_DRC_HCT		0x3020
++#define AC200_AC_DRC_LCT		0x3022
++#define AC200_AC_DRC_HKC		0x3024
++#define AC200_AC_DRC_LKC		0x3026
++#define AC200_AC_DRC_HOPC		0x3028
++#define AC200_AC_DRC_LOPC		0x302A
++#define AC200_AC_DRC_HLT		0x302C
++#define AC200_AC_DRC_LLT		0x302E
++#define AC200_AC_DRC_HKI		0x3030
++#define AC200_AC_DRC_LKI		0x3032
++#define AC200_AC_DRC_HOPL		0x3034
++#define AC200_AC_DRC_LOPL		0x3036
++#define AC200_AC_DRC_HET		0x3038
++#define AC200_AC_DRC_LET		0x303A
++#define AC200_AC_DRC_HKE		0x303C
++#define AC200_AC_DRC_LKE		0x303E
++#define AC200_AC_DRC_HOPE		0x3040
++#define AC200_AC_DRC_LOPE		0x3042
++#define AC200_AC_DRC_HKN		0x3044
++#define AC200_AC_DRC_LKN		0x3046
++#define AC200_AC_DRC_SFHAT		0x3048
++#define AC200_AC_DRC_SFLAT		0x304A
++#define AC200_AC_DRC_SFHRT		0x304C
++#define AC200_AC_DRC_SFLRT		0x304E
++#define AC200_AC_DRC_MXGHS		0x3050
++#define AC200_AC_DRC_MXGLS		0x3052
++#define AC200_AC_DRC_MNGHS		0x3054
++#define AC200_AC_DRC_MNGLS		0x3056
++#define AC200_AC_DRC_EPSHC		0x3058
++#define AC200_AC_DRC_EPSLC		0x305A
++#define AC200_AC_DRC_HPFHGAIN		0x305E
++#define AC200_AC_DRC_HPFLGAIN		0x3060
++#define AC200_AC_DRC_BISTCR		0x3100
++#define AC200_AC_DRC_BISTST		0x3102
++
++/* TVE registers */
++#define AC200_TVE_CTL0			0x4000
++#define AC200_TVE_CTL1			0x4002
++#define AC200_TVE_MOD0			0x4004
++#define AC200_TVE_MOD1			0x4006
++#define AC200_TVE_DAC_CFG0		0x4008
++#define AC200_TVE_DAC_CFG1		0x400A
++#define AC200_TVE_YC_DELAY		0x400C
++#define AC200_TVE_YC_FILTER		0x400E
++#define AC200_TVE_BURST_FRQ0		0x4010
++#define AC200_TVE_BURST_FRQ1		0x4012
++#define AC200_TVE_FRONT_PORCH		0x4014
++#define AC200_TVE_BACK_PORCH		0x4016
++#define AC200_TVE_TOTAL_LINE		0x401C
++#define AC200_TVE_FIRST_ACTIVE		0x401E
++#define AC200_TVE_BLACK_LEVEL		0x4020
++#define AC200_TVE_BLANK_LEVEL		0x4022
++#define AC200_TVE_PLUG_EN		0x4030
++#define AC200_TVE_PLUG_IRQ_EN		0x4032
++#define AC200_TVE_PLUG_IRQ_STA		0x4034
++#define AC200_TVE_PLUG_STA		0x4038
++#define AC200_TVE_PLUG_DEBOUNCE		0x4040
++#define AC200_TVE_DAC_TEST		0x4042
++#define AC200_TVE_PLUG_PULSE_LEVEL	0x40F4
++#define AC200_TVE_PLUG_PULSE_START	0x40F8
++#define AC200_TVE_PLUG_PULSE_PERIOD	0x40FA
++#define AC200_TVE_IF_CTL		0x5000
++#define AC200_TVE_IF_TIM0		0x5008
++#define AC200_TVE_IF_TIM1		0x500A
++#define AC200_TVE_IF_TIM2		0x500C
++#define AC200_TVE_IF_TIM3		0x500E
++#define AC200_TVE_IF_SYNC0		0x5010
++#define AC200_TVE_IF_SYNC1		0x5012
++#define AC200_TVE_IF_SYNC2		0x5014
++#define AC200_TVE_IF_TIM4		0x5016
++#define AC200_TVE_IF_STATUS		0x5018
++
++/* EPHY registers */
++#define AC200_EPHY_CTL			0x6000
++#define AC200_EPHY_BIST			0x6002
++
++/* eFuse registers (0x8000 - 0x9FFF, layout unknown) */
++
++/* RTC registers */
++#define AC200_LOSC_CTRL0		0xA000
++#define AC200_LOSC_CTRL1		0xA002
++#define AC200_LOSC_AUTO_SWT_STA		0xA004
++#define AC200_INTOSC_CLK_PRESCAL	0xA008
++#define AC200_RTC_YY_MM_DD0		0xA010
++#define AC200_RTC_YY_MM_DD1		0xA012
++#define AC200_RTC_HH_MM_SS0		0xA014
++#define AC200_RTC_HH_MM_SS1		0xA016
++#define AC200_ALARM0_CUR_VLU0		0xA024
++#define AC200_ALARM0_CUR_VLU1		0xA026
++#define AC200_ALARM0_ENABLE		0xA028
++#define AC200_ALARM0_IRQ_EN		0xA02C
++#define AC200_ALARM0_IRQ_STA		0xA030
++#define AC200_ALARM1_WK_HH_MM_SS0	0xA040
++#define AC200_ALARM1_WK_HH_MM_SS1	0xA042
++#define AC200_ALARM1_ENABLE		0xA044
++#define AC200_ALARM1_IRQ_EN		0xA048
++#define AC200_ALARM1_IRQ_STA		0xA04C
++#define AC200_ALARM_CONFIG		0xA050
++#define AC200_LOSC_OUT_GATING		0xA060
++#define AC200_GP_DATA(x)		(0xA100 + (x) * 2)
++#define AC200_RTC_DEB			0xA170
++#define AC200_GPL_HOLD_OUTPUT		0xA180
++#define AC200_VDD_RTC			0xA190
++#define AC200_IC_CHARA0			0xA1F0
++#define AC200_IC_CHARA1			0xA1F2
++
++struct ac200_dev {
++	struct regmap			*regmap;
++	struct regmap_irq_chip_data	*regmap_irqc;
++};
++
++#endif /* __LINUX_MFD_AC200_H */
+-- 
+2.20.1
+
diff --git a/0002-net-phy-Add-support-for-AC200-EPHY.patch b/0002-net-phy-Add-support-for-AC200-EPHY.patch
new file mode 100644
index 000000000000..ff87c895fb3d
--- /dev/null
+++ b/0002-net-phy-Add-support-for-AC200-EPHY.patch
@@ -0,0 +1,272 @@
+From 1b528543ea41a9837d39e9ab621631c77122f1aa Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Fri, 16 Aug 2019 16:38:57 +0200
+Subject: [PATCH 2/4] net: phy: Add support for AC200 EPHY
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+---
+ drivers/net/phy/Kconfig  |   7 ++
+ drivers/net/phy/Makefile |   1 +
+ drivers/net/phy/ac200.c  | 220 +++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 228 insertions(+)
+ create mode 100644 drivers/net/phy/ac200.c
+
+diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
+index 2e016271e126..248d9384091c 100644
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -266,6 +266,13 @@ config ADIN_PHY
+ 	  - ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
+ 	    Ethernet PHY
+ 
++config AC200_PHY
++	tristate "AC200 EPHY"
++	depends on NVMEM
++	depends on OF
++	help
++	  Fast ethernet PHY as found in X-Powers AC200 multi-function device.
++
+ config AMD_PHY
+ 	tristate "AMD PHYs"
+ 	---help---
+diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
+index fe5badf13b65..2143587f010e 100644
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -49,6 +49,7 @@ obj-$(CONFIG_SFP)		+= sfp.o
+ sfp-obj-$(CONFIG_SFP)		+= sfp-bus.o
+ obj-y				+= $(sfp-obj-y) $(sfp-obj-m)
+ 
++obj-$(CONFIG_AC200_PHY)		+= ac200.o
+ obj-$(CONFIG_ADIN_PHY)		+= adin.o
+ obj-$(CONFIG_AMD_PHY)		+= amd.o
+ aquantia-objs			+= aquantia_main.o
+diff --git a/drivers/net/phy/ac200.c b/drivers/net/phy/ac200.c
+new file mode 100644
+index 000000000000..cb713188f7ec
+--- /dev/null
++++ b/drivers/net/phy/ac200.c
+@@ -0,0 +1,220 @@
++// SPDX-License-Identifier: GPL-2.0+
++/**
++ * Driver for AC200 Ethernet PHY
++ *
++ * Copyright (c) 2020 Jernej Skrabec <jernej.skrabec@siol.net>
++ */
++
++#include <linux/clk.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/mfd/ac200.h>
++#include <linux/nvmem-consumer.h>
++#include <linux/of.h>
++#include <linux/phy.h>
++#include <linux/platform_device.h>
++
++#define AC200_EPHY_ID			0x00441400
++#define AC200_EPHY_ID_MASK		0x0ffffff0
++
++/* macros for system ephy control 0 register */
++#define AC200_EPHY_RESET_INVALID	BIT(0)
++#define AC200_EPHY_SYSCLK_GATING	BIT(1)
++
++/* macros for system ephy control 1 register */
++#define AC200_EPHY_E_EPHY_MII_IO_EN	BIT(0)
++#define AC200_EPHY_E_LNK_LED_IO_EN	BIT(1)
++#define AC200_EPHY_E_SPD_LED_IO_EN	BIT(2)
++#define AC200_EPHY_E_DPX_LED_IO_EN	BIT(3)
++
++/* macros for ephy control register */
++#define AC200_EPHY_SHUTDOWN		BIT(0)
++#define AC200_EPHY_LED_POL		BIT(1)
++#define AC200_EPHY_CLK_SEL		BIT(2)
++#define AC200_EPHY_ADDR(x)		(((x) & 0x1F) << 4)
++#define AC200_EPHY_XMII_SEL		BIT(11)
++#define AC200_EPHY_CALIB(x)		(((x) & 0xF) << 12)
++
++struct ac200_ephy_dev {
++	struct clk		*clk;
++	struct phy_driver	*ephy;
++	struct regmap		*regmap;
++};
++
++static char *ac200_phy_name = "AC200 EPHY";
++
++static int ac200_ephy_config_init(struct phy_device *phydev)
++{
++	const struct ac200_ephy_dev *priv = phydev->drv->driver_data;
++	unsigned int value;
++	int ret;
++
++	phy_write(phydev, 0x1f, 0x0100);	/* Switch to Page 1 */
++	phy_write(phydev, 0x12, 0x4824);	/* Disable APS */
++
++	phy_write(phydev, 0x1f, 0x0200);	/* Switch to Page 2 */
++	phy_write(phydev, 0x18, 0x0000);	/* PHYAFE TRX optimization */
++
++	phy_write(phydev, 0x1f, 0x0600);	/* Switch to Page 6 */
++	phy_write(phydev, 0x14, 0x708f);	/* PHYAFE TX optimization */
++	phy_write(phydev, 0x13, 0xF000);	/* PHYAFE RX optimization */
++	phy_write(phydev, 0x15, 0x1530);
++
++	phy_write(phydev, 0x1f, 0x0800);	/* Switch to Page 6 */
++	phy_write(phydev, 0x18, 0x00bc);	/* PHYAFE TRX optimization */
++
++	phy_write(phydev, 0x1f, 0x0100);	/* switch to page 1 */
++	phy_clear_bits(phydev, 0x17, BIT(3));	/* disable intelligent IEEE */
++
++	/* next two blocks disable 802.3az IEEE */
++	phy_write(phydev, 0x1f, 0x0200);	/* switch to page 2 */
++	phy_write(phydev, 0x18, 0x0000);
++
++	phy_write(phydev, 0x1f, 0x0000);	/* switch to page 0 */
++	phy_clear_bits_mmd(phydev, 0x7, 0x3c, BIT(1));
++
++	if (phydev->interface == PHY_INTERFACE_MODE_RMII)
++		value = AC200_EPHY_XMII_SEL;
++	else
++		value = 0;
++
++	ret = regmap_update_bits(priv->regmap, AC200_EPHY_CTL,
++				 AC200_EPHY_XMII_SEL, value);
++	if (ret)
++		return ret;
++
++	/* FIXME: This is H6 specific */
++	phy_set_bits(phydev, 0x13, BIT(12));
++
++	return 0;
++}
++
++static int ac200_ephy_probe(struct platform_device *pdev)
++{
++	struct ac200_dev *ac200 = dev_get_drvdata(pdev->dev.parent);
++	struct device *dev = &pdev->dev;
++	struct ac200_ephy_dev *priv;
++	struct nvmem_cell *calcell;
++	struct phy_driver *ephy;
++	u16 *caldata, calib;
++	size_t callen;
++	int ret;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	ephy = devm_kzalloc(dev, sizeof(*ephy), GFP_KERNEL);
++	if (!ephy)
++		return -ENOMEM;
++
++	priv->clk = devm_clk_get(dev, NULL);
++	if (IS_ERR(priv->clk)) {
++		dev_err(dev, "Can't obtain the clock!\n");
++		return PTR_ERR(priv->clk);
++	}
++
++	calcell = devm_nvmem_cell_get(dev, "calibration");
++	if (IS_ERR(calcell)) {
++		dev_err(dev, "Unable to find calibration data!\n");
++		return PTR_ERR(calcell);
++	}
++
++	caldata = nvmem_cell_read(calcell, &callen);
++	if (IS_ERR(caldata)) {
++		dev_err(dev, "Unable to read calibration data!\n");
++		return PTR_ERR(caldata);
++	}
++
++	if (callen != 2) {
++		dev_err(dev, "Calibration data has wrong length: 2 != %zu\n",
++			callen);
++		kfree(caldata);
++		return -EINVAL;
++	}
++
++	calib = *caldata + 3;
++	kfree(caldata);
++
++	ret = clk_prepare_enable(priv->clk);
++	if (ret)
++		return ret;
++
++	ephy->phy_id = AC200_EPHY_ID;
++	ephy->phy_id_mask = AC200_EPHY_ID_MASK;
++	ephy->name = ac200_phy_name;
++	ephy->driver_data = priv;
++	ephy->soft_reset = genphy_soft_reset;
++	ephy->config_init = ac200_ephy_config_init;
++	ephy->suspend = genphy_suspend;
++	ephy->resume = genphy_resume;
++
++	priv->ephy = ephy;
++	priv->regmap = ac200->regmap;
++	platform_set_drvdata(pdev, priv);
++
++	ret = regmap_write(ac200->regmap, AC200_SYS_EPHY_CTL0,
++			   AC200_EPHY_RESET_INVALID |
++			   AC200_EPHY_SYSCLK_GATING);
++	if (ret)
++		return ret;
++
++	ret = regmap_write(ac200->regmap, AC200_SYS_EPHY_CTL1,
++			   AC200_EPHY_E_EPHY_MII_IO_EN |
++			   AC200_EPHY_E_LNK_LED_IO_EN |
++			   AC200_EPHY_E_SPD_LED_IO_EN |
++			   AC200_EPHY_E_DPX_LED_IO_EN);
++	if (ret)
++		return ret;
++
++	ret = regmap_write(ac200->regmap, AC200_EPHY_CTL,
++			   AC200_EPHY_LED_POL |
++			   AC200_EPHY_CLK_SEL |
++			   AC200_EPHY_ADDR(1) |
++			   AC200_EPHY_CALIB(calib));
++	if (ret)
++		return ret;
++
++	ret = phy_driver_register(priv->ephy, THIS_MODULE);
++	if (ret) {
++		dev_err(dev, "Unable to register phy\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static int ac200_ephy_remove(struct platform_device *pdev)
++{
++	struct ac200_ephy_dev *priv = platform_get_drvdata(pdev);
++
++	phy_driver_unregister(priv->ephy);
++
++	regmap_write(priv->regmap, AC200_EPHY_CTL, AC200_EPHY_SHUTDOWN);
++	regmap_write(priv->regmap, AC200_SYS_EPHY_CTL1, 0);
++	regmap_write(priv->regmap, AC200_SYS_EPHY_CTL0, 0);
++
++	clk_disable_unprepare(priv->clk);
++
++	return 0;
++}
++
++static const struct of_device_id ac200_ephy_match[] = {
++	{ .compatible = "x-powers,ac200-ephy" },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, ac200_ephy_match);
++
++static struct platform_driver ac200_ephy_driver = {
++	.probe		= ac200_ephy_probe,
++	.remove		= ac200_ephy_remove,
++	.driver		= {
++		.name		= "ac200-ephy",
++		.of_match_table	= ac200_ephy_match,
++	},
++};
++module_platform_driver(ac200_ephy_driver);
++
++MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>");
++MODULE_DESCRIPTION("AC200 Ethernet PHY driver");
++MODULE_LICENSE("GPL");
+-- 
+2.20.1
+
diff --git a/0005-drm-gem-cma-Export-with-handle-allocator.patch b/0005-drm-gem-cma-Export-with-handle-allocator.patch
new file mode 100644
index 000000000000..b620041bd910
--- /dev/null
+++ b/0005-drm-gem-cma-Export-with-handle-allocator.patch
@@ -0,0 +1,50 @@
+From ea69ff188dd5d9ac7162f05a22bf299b83a7536e Mon Sep 17 00:00:00 2001
+From: Maxime Ripard <maxime.ripard@free-electrons.com>
+Date: Mon, 7 Dec 2015 09:33:28 +0100
+Subject: [PATCH 005/146] drm: gem: cma: Export with handle allocator
+
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+---
+ drivers/gpu/drm/drm_gem_cma_helper.c | 3 ++-
+ include/drm/drm_gem_cma_helper.h     | 4 ++++
+ 2 files changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/drm_gem_cma_helper.c b/drivers/gpu/drm/drm_gem_cma_helper.c
+index 80a5115c3846..077c61f065d9 100644
+--- a/drivers/gpu/drm/drm_gem_cma_helper.c
++++ b/drivers/gpu/drm/drm_gem_cma_helper.c
+@@ -142,7 +142,7 @@ EXPORT_SYMBOL_GPL(drm_gem_cma_create);
+  * A struct drm_gem_cma_object * on success or an ERR_PTR()-encoded negative
+  * error code on failure.
+  */
+-static struct drm_gem_cma_object *
++struct drm_gem_cma_object *
+ drm_gem_cma_create_with_handle(struct drm_file *file_priv,
+ 			       struct drm_device *drm, size_t size,
+ 			       uint32_t *handle)
+@@ -169,6 +169,7 @@ drm_gem_cma_create_with_handle(struct drm_file *file_priv,
+ 
+ 	return cma_obj;
+ }
++EXPORT_SYMBOL_GPL(drm_gem_cma_create_with_handle);
+ 
+ /**
+  * drm_gem_cma_free_object - free resources associated with a CMA GEM object
+diff --git a/include/drm/drm_gem_cma_helper.h b/include/drm/drm_gem_cma_helper.h
+index 19777145cf8e..79f397c91517 100644
+--- a/include/drm/drm_gem_cma_helper.h
++++ b/include/drm/drm_gem_cma_helper.h
+@@ -79,6 +79,10 @@ int drm_gem_cma_mmap(struct file *filp, struct vm_area_struct *vma);
+ /* allocate physical memory */
+ struct drm_gem_cma_object *drm_gem_cma_create(struct drm_device *drm,
+ 					      size_t size);
++struct drm_gem_cma_object *
++drm_gem_cma_create_with_handle(struct drm_file *file_priv,
++			       struct drm_device *drm, size_t size,
++			       uint32_t *handle);
+ 
+ extern const struct vm_operations_struct drm_gem_cma_vm_ops;
+ 
+-- 
+2.17.1
+
diff --git a/0006-drm-sun4i-Add-GEM-allocator.patch b/0006-drm-sun4i-Add-GEM-allocator.patch
new file mode 100644
index 000000000000..58557aa7768b
--- /dev/null
+++ b/0006-drm-sun4i-Add-GEM-allocator.patch
@@ -0,0 +1,102 @@
+From b143de6aef8be007256082e0f89606b7f5e3c757 Mon Sep 17 00:00:00 2001
+From: Maxime Ripard <maxime.ripard@free-electrons.com>
+Date: Mon, 7 Dec 2015 09:47:34 +0100
+Subject: [PATCH 006/146] drm/sun4i: Add GEM allocator
+
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+---
+ drivers/gpu/drm/sun4i/sun4i_drv.c | 27 +++++++++++++++++++++++++++
+ include/uapi/drm/sun4i_drm.h      | 29 +++++++++++++++++++++++++++++
+ 2 files changed, 56 insertions(+)
+ create mode 100644 include/uapi/drm/sun4i_drm.h
+
+diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
+index 8b0cd08034e0..9f5de14fb2fe 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
++++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
+@@ -22,6 +22,8 @@
+ #include <drm/drm_fb_helper.h>
+ #include <drm/drm_of.h>
+ 
++#include <uapi/drm/sun4i_drm.h>
++
+ #include "sun4i_drv.h"
+ #include "sun4i_frontend.h"
+ #include "sun4i_framebuffer.h"
+@@ -30,6 +32,27 @@
+ 
+ DEFINE_DRM_GEM_CMA_FOPS(sun4i_drv_fops);
+ 
++static int sun4i_gem_create_ioctl(struct drm_device *drm, void *data,
++				  struct drm_file *file_priv)
++{
++	struct drm_sun4i_gem_create *args = data;
++	struct drm_gem_cma_object *cma_obj;
++	size_t size;
++
++	/* The Mali requires a 64 bytes alignment */
++	size = ALIGN(args->size, 64);
++
++	cma_obj = drm_gem_cma_create_with_handle(file_priv, drm, size,
++						 &args->handle);
++
++	return PTR_ERR_OR_ZERO(cma_obj);
++}
++
++static const struct drm_ioctl_desc sun4i_drv_ioctls[] = {
++	DRM_IOCTL_DEF_DRV(SUN4I_GEM_CREATE, sun4i_gem_create_ioctl,
++			  DRM_UNLOCKED | DRM_AUTH),
++};
++
+ static const struct drm_driver sun4i_drv_driver = {
+ 	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
+ 
+@@ -42,6 +65,10 @@ static struct drm_driver sun4i_drv_driver = {
+ 	.major			= 1,
+ 	.minor			= 0,
+ 
++	/* Custom ioctls */
++	.ioctls			= sun4i_drv_ioctls,
++	.num_ioctls		= ARRAY_SIZE(sun4i_drv_ioctls),
++
+ 	/* GEM Operations */
+ 	.dumb_create		= drm_gem_cma_dumb_create,
+ 	.gem_free_object_unlocked = drm_gem_cma_free_object,
+diff --git a/include/uapi/drm/sun4i_drm.h b/include/uapi/drm/sun4i_drm.h
+new file mode 100644
+index 000000000000..67b9dd4ee594
+--- /dev/null
++++ b/include/uapi/drm/sun4i_drm.h
+@@ -0,0 +1,29 @@
++/*
++ * Copyright (C) 2015 Free Electrons
++ * Copyright (C) 2015 NextThing Co
++ *
++ * Maxime Ripard <maxime.ripard@free-electrons.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#ifndef _UAPI_SUN4I_DRM_H_
++#define _UAPI_SUN4I_DRM_H_
++
++#include <drm/drm.h>
++
++struct drm_sun4i_gem_create {
++	__u64 size;
++	__u32 flags;
++	__u32 handle;
++};
++
++#define DRM_SUN4I_GEM_CREATE		0x00
++
++#define DRM_IOCTL_SUN4I_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_SUN4I_GEM_CREATE, \
++						 struct drm_sun4i_gem_create)
++
++#endif
+-- 
+2.17.1
+
diff --git a/0010-general-h6-add-dma-i2c-ir-spi-uart.patch b/0010-general-h6-add-dma-i2c-ir-spi-uart.patch
new file mode 100644
index 000000000000..77cb4dabf281
--- /dev/null
+++ b/0010-general-h6-add-dma-i2c-ir-spi-uart.patch
@@ -0,0 +1,107 @@
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index dc785da9c..141fd186b 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -374,6 +381,17 @@
+ 			#dma-cells = <1>;
+ 		};
+ 
++		gic: interrupt-controller@3021000 {
++			compatible = "arm,gic-400";
++			reg = <0x03021000 0x1000>,
++			      <0x03022000 0x2000>,
++			      <0x03024000 0x2000>,
++			      <0x03026000 0x2000>;
++			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
++			interrupt-controller;
++			#interrupt-cells = <3>;
++		};
++
+ 		sid: efuse@3006000 {
+ 			compatible = "allwinner,sun50i-h6-sid";
+ 			reg = <0x03006000 0x400>;
+@@ -279,6 +305,7 @@
+ 			interrupt-controller;
+ 			#interrupt-cells = <3>;
+ 
++			/omit-if-no-ref/
+ 			ext_rgmii_pins: rgmii-pins {
+ 				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
+ 				       "PD5", "PD7", "PD8", "PD9", "PD10",
+@@ -309,6 +354,7 @@
+ 				bias-pull-up;
+ 			};
+ 
++			/omit-if-no-ref/
+ 			mmc2_pins: mmc2-pins {
+ 				pins = "PC1", "PC4", "PC5", "PC6",
+ 				       "PC7", "PC8", "PC9", "PC10",
+@@ -511,17 +540,26 @@
+ 				pins = "PG8", "PG9";
+ 				function = "uart1";
+ 			};
+-		};
+ 
+-		gic: interrupt-controller@3021000 {
+-			compatible = "arm,gic-400";
+-			reg = <0x03021000 0x1000>,
+-			      <0x03022000 0x2000>,
+-			      <0x03024000 0x2000>,
+-			      <0x03026000 0x2000>;
+-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+-			interrupt-controller;
+-			#interrupt-cells = <3>;
++			uart2_pins: uart2-pins {
++				pins = "PD19", "PD20";
++				function = "uart2";
++			};
++
++			uart2_rts_cts_pins: uart2-rts-cts-pins {
++				pins = "PD21", "PD22";
++				function = "uart2";
++			};
++
++			uart3_pins: uart3-pins {
++				pins = "PD23", "PD24";
++				function = "uart3";
++			};
++
++			uart3_rts_cts_pins: uart3-rts-cts-pins {
++				pins = "PD25", "PD26";
++				function = "uart3";
++			};
+ 		};
+ 
+ 		mmc0: mmc@4020000 {
+@@ -963,6 +1033,19 @@
+ 			};
+ 		};
+ 
++		r_uart: serial@7080000 {
++			compatible = "snps,dw-apb-uart";
++			reg = <0x07080000 0x400>;
++			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
++			reg-shift = <2>;
++			reg-io-width = <4>;
++			clocks = <&r_ccu CLK_R_APB2_UART>;
++			resets = <&r_ccu RST_R_APB2_UART>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&r_uart_pins>;
++			status = "disabled";
++		};
++
+ 		rtc: rtc@7000000 {
+ 			compatible = "allwinner,sun50i-h6-rtc";
+ 			reg = <0x07000000 0x400>;
+@@ -1021,6 +1104,11 @@
+ 				pins = "PL9";
+ 				function = "s_cir_rx";
+ 			};
++
++			r_uart_pins: r-uart-pins {
++				pins = "PL2", "PL3";
++				function = "s_uart";
++			};
+ 		};
+ 
+ 		r_ir: ir@7040000 {
diff --git a/PKGBUILD b/PKGBUILD
index 16891f7edd6a..c5dbe2207e35 100644
--- a/PKGBUILD
+++ b/PKGBUILD
@@ -10,7 +10,7 @@ _srcname=linux-5.11
 _kernelname=${pkgbase#linux}
 _desc="AArch64 kernel for TQC A01"
 pkgver=5.11.4
-pkgrel=3
+pkgrel=4
 arch=('aarch64')
 url="http://www.kernel.org/"
 license=('GPL2')
@@ -18,12 +18,18 @@ makedepends=('xmlto' 'docbook-xsl' 'kmod' 'inetutils' 'bc' 'git' 'uboot-tools' '
 options=('!strip')
 source=("http://cdn.kernel.org/pub/linux/kernel/v5.x/${_srcname}.tar.xz"
         'sun50i-h6-tqc-a01.dts'
+        '0001-mfd-Add-support-for-AC200.patch'
         '0001-net-smsc95xx-Allow-mac-address-to-be-set-as-a-parame.patch'
+        '0002-net-phy-Add-support-for-AC200-EPHY.patch'
         '0002-net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regu.patch'
         '0003-net-stmmac-sun8i-Rename-PHY-regulator-variable-to-re.patch'
         '0004-net-stmmac-sun8i-Add-support-for-enabling-a-regulato.patch'
+        '0005-drm-gem-cma-Export-with-handle-allocator.patch'
+        '0006-drm-sun4i-Add-GEM-allocator.patch'
         '0007-arm64-dts-allwinner-h6-Add-AC200-EPHY-related-nodes.patch'
+        '0010-general-h6-add-dma-i2c-ir-spi-uart.patch'
         '0011-mmc-sunxi-fix-unusuable-eMMC-on-some-H6-boards-by-di.patch'
+        'fix-missing-H6-spi-pins.patch'
         'config'
         'kernel.its'
         'kernel.keyblock'
@@ -36,13 +42,19 @@ source=("http://cdn.kernel.org/pub/linux/kernel/v5.x/${_srcname}.tar.xz"
 source+=("https://cdn.kernel.org/pub/linux/kernel/v5.x/patch-${pkgver}.xz")
 
 md5sums=('d2985a3f16ef1ea3405c04c406e29dcc'
-         '3bf41e61be58e1cda848dd75983a0ea9'
+         '257beb93e91b190184f1a161f66d3206'
+         '17aa0c69176c68cd98b4522740a1b747'
          'f9b6f367eef351eaa89b23a9b1ffc5a2'
+         'bc7904920675ba8d38f21d46ffac33b5'
          '94a69594f90309c50c83a5cc8579fb54'
          'e1868e41094baff9eceba481fc097c79'
          '5d42a68276c8f9e8b3de040fa2579b84'
+         '335382823f6dc2aae2f6038b7aee339e'
+         'cb38b30491472097c3b9b475de39127f'
          '6fd2f4aaa791c975aef5968f32eecb4c'
+         'bc65c0b9e4d6fb2fe3a81b8358886885'
          'f27a8190e862a7edcf2b09cc27aef180'
+         '11dfddadb815a896a2db65812e66e6fa'
          '5e0c36c663ebe0721fb96b9f2bfef451'
          '7f1a96e24f5150f790df94398e9525a3'
          '61c5ff73c136ed07a7aadbf58db3d96a'
@@ -60,18 +72,24 @@ prepare() {
   patch -p1 < "../patch-${pkgver}"
 
   # patches for TQC A01
+  patch -p1 < ../0001-mfd-Add-support-for-AC200.patch
   patch -p1 < ../0001-net-smsc95xx-Allow-mac-address-to-be-set-as-a-parame.patch
+  patch -p1 < ../0002-net-phy-Add-support-for-AC200-EPHY.patch
   patch -p1 < ../0002-net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regu.patch
   patch -p1 < ../0003-net-stmmac-sun8i-Rename-PHY-regulator-variable-to-re.patch
   patch -p1 < ../0004-net-stmmac-sun8i-Add-support-for-enabling-a-regulato.patch
+  patch -p1 < ../0005-drm-gem-cma-Export-with-handle-allocator.patch
+  patch -p1 < ../0006-drm-sun4i-Add-GEM-allocator.patch
   patch -p1 < ../0007-arm64-dts-allwinner-h6-Add-AC200-EPHY-related-nodes.patch
+  patch -p1 < ../0010-general-h6-add-dma-i2c-ir-spi-uart.patch
   patch -p1 < ../0011-mmc-sunxi-fix-unusuable-eMMC-on-some-H6-boards-by-di.patch
+  patch -p1 < ../fix-missing-H6-spi-pins.patch
 
   cat "${srcdir}/config" > ./.config
 
   # dts for TQC-A01
-  target_dts="sun50i-h6-tqc-a01.dtb"
-  echo "dtb-\$(CONFIG_ARCH_SUNXI) += ${target_dts}" >> "./arch/arm64/boot/dts/allwinner/Makefile"
+  target_dts="sun50i-h6-tqc-a01.dts"
+  echo "dtb-\$(CONFIG_ARCH_SUNXI) += ${target_dts//dts/dtb}" >> "./arch/arm64/boot/dts/allwinner/Makefile"
   cat "${srcdir}/${target_dts}" > "./arch/arm64/boot/dts/allwinner/${target_dts}"
 
   # add pkgrel to extraversion
diff --git a/fix-missing-H6-spi-pins.patch b/fix-missing-H6-spi-pins.patch
new file mode 100644
index 000000000000..5791980b7ddb
--- /dev/null
+++ b/fix-missing-H6-spi-pins.patch
@@ -0,0 +1,22 @@
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 2c15b3fb0..00794a6a1 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -608,6 +670,8 @@ spi0: spi@5010000 {
+ 			clock-names = "ahb", "mod";
+ 			dmas = <&dma 22>, <&dma 22>;
+ 			dma-names = "rx", "tx";
++			pinctrl-names = "default";
++			pinctrl-0 = <&spi0_pins>, <&spi0_cs_pin>;
+ 			resets = <&ccu RST_BUS_SPI0>;
+ 			status = "disabled";
+ 			#address-cells = <1>;
+@@ -623,6 +687,8 @@ spi1: spi@5011000 {
+ 			clock-names = "ahb", "mod";
+ 			dmas = <&dma 23>, <&dma 23>;
+ 			dma-names = "rx", "tx";
++			pinctrl-names = "default";
++			pinctrl-0 = <&spi1_pins>, <&spi1_cs_pin>;
+ 			resets = <&ccu RST_BUS_SPI1>;
+ 			status = "disabled";
+ 			#address-cells = <1>;
diff --git a/sun50i-h6-tqc-a01.dts b/sun50i-h6-tqc-a01.dts
index 3fa50719f4bc..71048c67a381 100644
--- a/sun50i-h6-tqc-a01.dts
+++ b/sun50i-h6-tqc-a01.dts
@@ -98,6 +98,10 @@
 	};
 };
 
+&ac200_ephy {
+    status = "okay";
+};
+
 &ac200_pwm_clk {
     status = "okay";
 };