Manually copy verlog for vexriscv core

Also fix version # to match aur standards for git packages.

2 files changed, 6 insertions, 5 deletions

diff --git a/.SRCINFO b/.SRCINFO
index af875ece5e48..d4f7cd92ce6b 100644
--- a/.SRCINFO
+++ b/.SRCINFO
@@ -1,7 +1,7 @@
 pkgbase = litex-git
 	pkgdesc = Migen based SoC
-	pkgver = 3724
-	pkgrel = 3
+	pkgver = latest
+	pkgrel = 2
 	url = https://github.com/enjoy-digital/litex
 	arch = any
 	license = MIT
diff --git a/PKGBUILD b/PKGBUILD
index 9149177db8bd..687a1c9ee042 100644
--- a/PKGBUILD
+++ b/PKGBUILD
@@ -1,7 +1,7 @@
 # Maintainer: Caleb Jamison <cbjamo@gmail.com> 
 pkgname=litex-git
-pkgver=3724
-pkgrel=3
+pkgver=latest
+pkgrel=2
 pkgdesc="Migen based SoC"
 arch=(any)
 url="https://github.com/enjoy-digital/litex"
@@ -20,7 +20,7 @@ sha256sums=('SKIP')
 
 pkgver() {
   cd "${srcdir}/${pkgname%%-git}"
-  git rev-list --count HEAD
+  git describe --long --tags | sed 's/\([^-]*-g\)/r/;s/-/./g'
 }
 
 prepare() {
@@ -38,5 +38,6 @@ build() {
 package() {
   cd "${srcdir}/${pkgname%%-git}"
   python setup.py install --root="$pkgdir/" --skip-build --optimize=1
+  cp -r litex/soc/cores/cpu/vexriscv/verilog $pkgdir/usr/lib/python3.7/site-packages/litex/soc/cores/cpu/vexriscv/
 }