added i915 intel gallium driver

added patches to fix a hang where the HW is hung on a PIPE_CONTROL after a GPGPU_WALKER

4 files changed, 138 insertions, 3 deletions

diff --git a/.SRCINFO b/.SRCINFO
index ee44928120f8..736aa69cc51f 100644
--- a/.SRCINFO
+++ b/.SRCINFO
@@ -1,6 +1,6 @@
 pkgbase = mesa-git
 	pkgdesc = an open-source implementation of the OpenGL specification, git version
-	pkgver = 23.0.0_devel.162765.4ceaed7839a.d41d8cd98f00b204e9800998ecf8427e
+	pkgver = 23.0.0_devel.163974.bafbe7c23a1.d41d8cd98f00b204e9800998ecf8427e
 	pkgrel = 1
 	url = https://www.mesa3d.org
 	arch = x86_64
@@ -62,10 +62,16 @@ pkgbase = mesa-git
 	conflicts = vulkan-swrast
 	conflicts = mesa-libgl
 	source = mesa::git+https://gitlab.freedesktop.org/mesa/mesa.git#branch=main
+	source = 0001-anv-force-MEDIA_INTERFACE_DESCRIPTOR_LOAD-reemit-aft.patch
+	source = 0002-intel-fs-always-mask-the-bottom-bits-of-the-sampler-.patch
 	source = LICENSE
 	md5sums = SKIP
+	md5sums = 102af8525e4c1f266cc54b038d1b9314
+	md5sums = 094f900983f68bec0325bd29d4789ad5
 	md5sums = 5c65a0fe315dd347e09b1f2826a1df5a
 	sha512sums = SKIP
+	sha512sums = 4ff7c359f08aedb1fb6eb2c6bb34bafa399edfa7916cd6cce7844bb38795e84c0265324e3fc7d37237d4824f029cb04da176bcf476785fd2e35a8b0ce4f8a394
+	sha512sums = 5dd0cb8affa9cfe6e7d94f59b8e23727036fd8ab76938321f8d266315f30611584da6f6277fe2aa920130483302adab5e57e2bc08f1bd3c62ea57b3e4b007305
 	sha512sums = 25da77914dded10c1f432ebcbf29941124138824ceecaf1367b3deedafaecabc082d463abcfa3d15abff59f177491472b505bcb5ba0c4a51bb6b93b4721a23c2
 
 pkgname = mesa-git
diff --git a/0001-anv-force-MEDIA_INTERFACE_DESCRIPTOR_LOAD-reemit-aft.patch b/0001-anv-force-MEDIA_INTERFACE_DESCRIPTOR_LOAD-reemit-aft.patch
new file mode 100644
index 000000000000..19c21a04115e
--- /dev/null
+++ b/0001-anv-force-MEDIA_INTERFACE_DESCRIPTOR_LOAD-reemit-aft.patch
@@ -0,0 +1,40 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
+Date: Sun, 12 Jun 2022 23:59:05 +0300
+Subject: [PATCH] anv: force MEDIA_INTERFACE_DESCRIPTOR_LOAD reemit after
+ 3D->GPGPU switch
+
+Seems to fix a hang in Age of Empire 4 where the HW is hung on a
+PIPE_CONTROL after a GPGPU_WALKER but no
+MEDIA_INTERFACE_DESCRIPTOR_LOAD was emitted since the switch from 3D
+to GPGPU.
+
+This would happen in the following case :
+
+   vkCmdBindPipeline(COMPUTE, cs_pipeline);
+   vkCmdDispatch(...);
+   vkCmdBindPipeline(GRAPHICS, gfx_pipeline);
+   vkCmdDraw(...);
+   vkCmdDispatch(...);
+
+Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
+---
+ src/intel/vulkan/genX_cmd_buffer.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
+index 1aa997f2ade2..2e9979c8f63e 100644
+--- a/src/intel/vulkan/genX_cmd_buffer.c
++++ b/src/intel/vulkan/genX_cmd_buffer.c
+@@ -5955,6 +5955,11 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
+    }
+ #endif
+ 
++#if GFX_VERx10 == 120
++   if (pipeline == _3D)
++      cmd_buffer->state.compute.pipeline_dirty = true;
++#endif
++
+    /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
+     * PIPELINE_SELECT [DevBWR+]":
+     *
diff --git a/0002-intel-fs-always-mask-the-bottom-bits-of-the-sampler-.patch b/0002-intel-fs-always-mask-the-bottom-bits-of-the-sampler-.patch
new file mode 100644
index 000000000000..ef12fda3b0c0
--- /dev/null
+++ b/0002-intel-fs-always-mask-the-bottom-bits-of-the-sampler-.patch
@@ -0,0 +1,83 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
+Date: Sat, 25 Jun 2022 23:38:45 +0300
+Subject: [PATCH] intel/fs: always mask the bottom bits of the sampler extended
+ descriptor
+
+Fixes a hang in Age Of Empire 4. The HW is hang with the sampler input
+unit busy. Replaying on simulation showed the extended message length
+in the extended descriptor is invalid. Since the Anv ensures the input
+is correct in anv_surface_state_to_handle(), the likely reason for
+this issue is the use of VK_VALVE_mutable_descriptor_type and the
+application leaving a previous value for a different descriptor type.
+
+Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
+---
+ src/intel/compiler/brw_fs.cpp                 |  2 +-
+ .../compiler/brw_lower_logical_sends.cpp      | 20 +++++++++++++++----
+ 2 files changed, 17 insertions(+), 5 deletions(-)
+
+diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
+index 624454676031..061eb7d603bb 100644
+--- a/src/intel/compiler/brw_fs.cpp
++++ b/src/intel/compiler/brw_fs.cpp
+@@ -4439,7 +4439,7 @@ brw_fb_write_msg_control(const fs_inst *inst,
+    return mctl;
+ }
+ 
+- /**
++/**
+  * Predicate the specified instruction on the sample mask.
+  */
+ void
+diff --git a/src/intel/compiler/brw_lower_logical_sends.cpp b/src/intel/compiler/brw_lower_logical_sends.cpp
+index 1ff064d342ae..90cb00daeb9b 100644
+--- a/src/intel/compiler/brw_lower_logical_sends.cpp
++++ b/src/intel/compiler/brw_lower_logical_sends.cpp
+@@ -1117,30 +1117,42 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op,
+       inst->src[1] = brw_imm_ud(0);
+    } else if (surface_handle.file != BAD_FILE) {
+       /* Bindless surface */
++      const fs_builder ubld = bld.group(1, 0).exec_all();
+       assert(devinfo->ver >= 9);
+       inst->desc = brw_sampler_desc(devinfo,
+                                     GFX9_BTI_BINDLESS,
+                                     sampler.file == IMM ? sampler.ud % 16 : 0,
+                                     msg_type,
+                                     simd_mode,
+                                     0 /* return_format unused on gfx7+ */);
+ 
+       /* For bindless samplers, the entire address is included in the message
+        * header so we can leave the portion in the message descriptor 0.
+        */
+       if (sampler_handle.file != BAD_FILE || sampler.file == IMM) {
+          inst->src[0] = brw_imm_ud(0);
+       } else {
+-         const fs_builder ubld = bld.group(1, 0).exec_all();
+          fs_reg desc = ubld.vgrf(BRW_REGISTER_TYPE_UD);
+          ubld.SHL(desc, sampler, brw_imm_ud(8));
+          inst->src[0] = desc;
+       }
+ 
+-      /* We assume that the driver provided the handle in the top 20 bits so
+-       * we can use the surface handle directly as the extended descriptor.
++      /* We previously assumed that the driver provided the handle in the top
++       * 20 bits (leaving the bottom 12 bits at 0). But with extensions like
++       * VK_VALVE_mutable_descriptor_type, the application is more in control
++       * of the content of VkDescriptors which is where we store
++       * surface/sampler offsets. We experience GPU hangs because the
++       * application left an invalid value in the descriptor (probably used
++       * for another descriptor type than sampler) and the lower 12bits of the
++       * surface handle overlapping with the extended descriptor length make
++       * the HW hang. The following AND() clears those bits and fixes a hang
++       * in Age Of Empire 4.
+        */
+-      inst->src[1] = retype(surface_handle, BRW_REGISTER_TYPE_UD);
++      fs_reg ex_desc = ubld.vgrf(BRW_REGISTER_TYPE_UD);
++      ubld.AND(ex_desc,
++               retype(surface_handle, BRW_REGISTER_TYPE_UD),
++               brw_imm_ud(INTEL_MASK(31, 12)));
++      inst->src[1] = component(ex_desc, 0);
+    } else {
+       /* Immediate portion of the descriptor */
+       inst->desc = brw_sampler_desc(devinfo,
diff --git a/PKGBUILD b/PKGBUILD
index dd196e501454..e439d711ee33 100644
--- a/PKGBUILD
+++ b/PKGBUILD
@@ -12,7 +12,7 @@
 
 pkgname=mesa-git
 pkgdesc="an open-source implementation of the OpenGL specification, git version"
-pkgver=23.0.0_devel.162765.4ceaed7839a.d41d8cd98f00b204e9800998ecf8427e
+pkgver=23.0.0_devel.163975.a3249415e23.5269a95f00c4d6964d487d9dbd94f62b
 pkgrel=1
 arch=('x86_64')
 makedepends=('git' 'python-mako' 'xorgproto'
@@ -26,10 +26,16 @@ conflicts=('mesa' 'opencl-mesa' 'vulkan-intel' 'vulkan-radeon' 'vulkan-mesa-laye
 url="https://www.mesa3d.org"
 license=('custom')
 source=('mesa::git+https://gitlab.freedesktop.org/mesa/mesa.git#branch=main'
+        '0001-anv-force-MEDIA_INTERFACE_DESCRIPTOR_LOAD-reemit-aft.patch'
+        '0002-intel-fs-always-mask-the-bottom-bits-of-the-sampler-.patch'
         'LICENSE')
 md5sums=('SKIP'
+         '102af8525e4c1f266cc54b038d1b9314'
+         '094f900983f68bec0325bd29d4789ad5'
          '5c65a0fe315dd347e09b1f2826a1df5a')
 sha512sums=('SKIP'
+            '4ff7c359f08aedb1fb6eb2c6bb34bafa399edfa7916cd6cce7844bb38795e84c0265324e3fc7d37237d4824f029cb04da176bcf476785fd2e35a8b0ce4f8a394'
+            '5dd0cb8affa9cfe6e7d94f59b8e23727036fd8ab76938321f8d266315f30611584da6f6277fe2aa920130483302adab5e57e2bc08f1bd3c62ea57b3e4b007305'
             '25da77914dded10c1f432ebcbf29941124138824ceecaf1367b3deedafaecabc082d463abcfa3d15abff59f177491472b505bcb5ba0c4a51bb6b93b4721a23c2')
 
 # NINJAFLAGS is an env var used to pass commandline options to ninja
@@ -118,7 +124,7 @@ build () {
        -D b_ndebug=true \
        -D b_lto=false \
        -D platforms=x11,wayland \
-       -D gallium-drivers=r300,r600,radeonsi,nouveau,virgl,svga,swrast,iris,crocus,zink,d3d12 \
+       -D gallium-drivers=r300,r600,radeonsi,nouveau,virgl,svga,swrast,i915,iris,crocus,zink,d3d12 \
        -D vulkan-drivers=amd,intel,swrast,virtio-experimental,intel_hasvk \
        -D vulkan-layers=device-select,overlay \
        -D dri3=enabled \