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author | Cayetano Santos | 2022-09-19 10:15:46 +0200 |
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committer | Cayetano Santos | 2022-09-19 10:15:46 +0200 |
commit | 5bde74ca9eafa68cff308ab9c49791e54411378c (patch) | |
tree | 5bb4d9016a7392d735a9b899c046341c5e6c1a5c | |
parent | f0c7101e794a3548ee24aa237420127c5d4dae95 (diff) | |
download | aur-5bde74ca9eafa68cff308ab9c49791e54411378c.tar.gz |
version 1.7.0
-rw-r--r-- | .SRCINFO | 5 | ||||
-rw-r--r-- | PKGBUILD | 2 |
2 files changed, 3 insertions, 4 deletions
@@ -1,6 +1,6 @@ pkgbase = python-cocotb pkgdesc = Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python - pkgver = 1.6.1 + pkgver = 1.7.0 pkgrel = 1 url = http://github.com/cocotb/cocotb/ arch = any @@ -13,8 +13,7 @@ pkgbase = python-cocotb optdepends = ghdl: for simulating VHDL designs optdepends = gtkwave: for visualizing waveforms options = !emptydirs - source = git+https://github.com/cocotb/cocotb#tag=v1.6.1 + source = git+https://github.com/cocotb/cocotb#tag=v1.7.0 md5sums = SKIP pkgname = python-cocotb - @@ -1,6 +1,6 @@ # Maintainer: csantosb <csantosb dot inventati dot org> pkgname=python-cocotb -pkgver=1.6.1 +pkgver=1.7.0 pkgrel=1 pkgdesc="Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python" arch=('any') |