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author | Cayetano Santos | 2021-12-14 08:48:58 +0100 |
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committer | Cayetano Santos | 2021-12-14 08:48:58 +0100 |
commit | b94aba32b8d448dfee049e6f5c9f3553070a936e (patch) | |
tree | 393a49cdf5ce2806009070818002f41b9c6774b5 | |
parent | 0c98b9de857c6ebc4ee0b296a8f312cbc67a7f58 (diff) | |
download | aur-b94aba32b8d448dfee049e6f5c9f3553070a936e.tar.gz |
Updated to 1.6.1
-rw-r--r-- | .SRCINFO | 4 | ||||
-rw-r--r-- | PKGBUILD | 2 |
2 files changed, 3 insertions, 3 deletions
@@ -1,6 +1,6 @@ pkgbase = python-cocotb pkgdesc = Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python - pkgver = 1.5.2 + pkgver = 1.6.1 pkgrel = 1 url = http://github.com/cocotb/cocotb/ arch = any @@ -13,7 +13,7 @@ pkgbase = python-cocotb optdepends = ghdl: for simulating VHDL designs optdepends = gtkwave: for visualizing waveforms options = !emptydirs - source = git+https://github.com/cocotb/cocotb#tag=v1.5.2 + source = git+https://github.com/cocotb/cocotb#tag=v1.6.1 md5sums = SKIP pkgname = python-cocotb @@ -1,6 +1,6 @@ # Maintainer: csantosb <csantosb dot inventati dot org> pkgname=python-cocotb -pkgver=1.5.2 +pkgver=1.6.1 pkgrel=1 pkgdesc="Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python" arch=('any') |