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| author | Cayetano Santos | 2020-04-22 19:43:30 +0200 |
|---|---|---|
| committer | Cayetano Santos | 2020-04-22 19:43:30 +0200 |
| commit | cfba7db9d4c0ccf37f1a38c4343fe4e5fea1fdaa (patch) | |
| tree | 23e20076b446b032773884ba04f5a9e1723c7245 | |
| parent | b2cddf422d4d82785df03b0cb2d19ee5d77cf9b7 (diff) | |
| download | aur-cfba7db9d4c0ccf37f1a38c4343fe4e5fea1fdaa.tar.gz | |
forget about binutils
| -rw-r--r-- | .SRCINFO | 1 | ||||
| -rw-r--r-- | PKGBUILD | 2 |
2 files changed, 1 insertions, 2 deletions
@@ -9,7 +9,6 @@ pkgbase = python-cocotb-git makedepends = python-setuptools depends = python depends = python-setuptools - depends = binutils optdepends = iverilog: for simulating verilog designs optdepends = ghdl: for simulating VHDL designs optdepends = gtkwave: for visualizing waveforms @@ -8,7 +8,7 @@ url="https://github.com/cocotb/cocotb" license=('BSD') conflicts=('python-cocotb') provides=('python-cocotb-git') -depends=('python' 'python-setuptools' 'binutils') +depends=('python' 'python-setuptools') makedepends=('git' 'python-setuptools') optdepends=('iverilog: for simulating verilog designs' |