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authorCayetano Santos2020-03-21 12:23:03 +0100
committerCayetano Santos2020-03-21 12:23:03 +0100
commitd427a609b9f28a73edb864ecf6d56c583bed3ee9 (patch)
tree4ef9b62fd0a9666616db62b1438d7ef34ac251dd
parente170ecfc62d37330d1639eeabab187339897ab0d (diff)
downloadaur-d427a609b9f28a73edb864ecf6d56c583bed3ee9.tar.gz
comply with independent repo python-cocotb
-rw-r--r--.SRCINFO3
-rw-r--r--PKGBUILD17
2 files changed, 11 insertions, 9 deletions
diff --git a/.SRCINFO b/.SRCINFO
index 1538df25c31c..c5f493f74ad0 100644
--- a/.SRCINFO
+++ b/.SRCINFO
@@ -15,6 +15,7 @@ pkgbase = python-cocotb-git
conflicts = python-cocotb
options = !emptydirs
source = git+https://github.com/cocotb/cocotb
- sha256sums = SKIP
+ md5sums = SKIP
pkgname = python-cocotb-git
+
diff --git a/PKGBUILD b/PKGBUILD
index e176a100a111..22306748f60f 100644
--- a/PKGBUILD
+++ b/PKGBUILD
@@ -6,9 +6,10 @@ pkgdesc="Coroutine based cosimulation library for writing VHDL and Verilog testb
arch=('any')
url="https://github.com/cocotb/cocotb"
license=('BSD')
-conflicts=('cocotb')
-provides=('cocotb')
+conflicts=('python-cocotb')
+provides=('python-cocotb')
depends=('python')
+
makedepends=('git' 'python-setuptools')
optdepends=('iverilog: for simulating verilog designs'
'ghdl: for simulating VHDL designs'
@@ -16,15 +17,15 @@ optdepends=('iverilog: for simulating verilog designs'
options=(!emptydirs)
source=('git+https://github.com/cocotb/cocotb')
-sha256sums=('SKIP')
-
-pkgver() {
- cd "${srcdir}/cocotb"
- printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
-}
+md5sums=('SKIP')
package() {
cd "${srcdir}/cocotb"
python setup.py install --prefix=/usr --root="$pkgdir/" --optimize=1
install -m 644 -D ./LICENSE "$pkgdir"/usr/share/licenses/"$pkgname"/LICENSE
+}
+
+pkgver() {
+ cd "${srcdir}/cocotb"
+ printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
} \ No newline at end of file