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authorCayetano Santos2020-03-21 12:32:51 +0100
committerCayetano Santos2020-03-21 12:32:51 +0100
commit066b8133dc4542598e03e4297bff46b7f46f56a0 (patch)
treec527447304f30cf1efba267e2a84f40f600b9009
parentd056bd8180f5d247125d2ded571c1852e37fc62d (diff)
downloadaur-066b8133dc4542598e03e4297bff46b7f46f56a0.tar.gz
Description
-rw-r--r--.SRCINFO2
-rw-r--r--PKGBUILD2
2 files changed, 2 insertions, 2 deletions
diff --git a/.SRCINFO b/.SRCINFO
index 47ac79377312..798d8d039646 100644
--- a/.SRCINFO
+++ b/.SRCINFO
@@ -1,5 +1,5 @@
pkgbase = python-fusesoc
- pkgdesc = Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
+ pkgdesc = Package manager and build abstraction tool for FPGA/ASIC development.
pkgver = 1.10
pkgrel = 0
url = http://github.com/olofk/fusesoc/
diff --git a/PKGBUILD b/PKGBUILD
index 8d111efd5e06..a1834051af5e 100644
--- a/PKGBUILD
+++ b/PKGBUILD
@@ -2,7 +2,7 @@
pkgname=python-fusesoc
pkgver=1.10
pkgrel=0
-pkgdesc="Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python"
+pkgdesc="Package manager and build abstraction tool for FPGA/ASIC development."
arch=('any')
url="http://github.com/olofk/fusesoc/"
license=('GPLv3')