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author | Cayetano Santos | 2020-03-21 12:32:51 +0100 |
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committer | Cayetano Santos | 2020-03-21 12:32:51 +0100 |
commit | 066b8133dc4542598e03e4297bff46b7f46f56a0 (patch) | |
tree | c527447304f30cf1efba267e2a84f40f600b9009 | |
parent | d056bd8180f5d247125d2ded571c1852e37fc62d (diff) | |
download | aur-066b8133dc4542598e03e4297bff46b7f46f56a0.tar.gz |
Description
-rw-r--r-- | .SRCINFO | 2 | ||||
-rw-r--r-- | PKGBUILD | 2 |
2 files changed, 2 insertions, 2 deletions
@@ -1,5 +1,5 @@ pkgbase = python-fusesoc - pkgdesc = Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python + pkgdesc = Package manager and build abstraction tool for FPGA/ASIC development. pkgver = 1.10 pkgrel = 0 url = http://github.com/olofk/fusesoc/ @@ -2,7 +2,7 @@ pkgname=python-fusesoc pkgver=1.10 pkgrel=0 -pkgdesc="Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python" +pkgdesc="Package manager and build abstraction tool for FPGA/ASIC development." arch=('any') url="http://github.com/olofk/fusesoc/" license=('GPLv3') |