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| author | Cayetano Santos | 2020-07-12 13:15:49 +0200 |
|---|---|---|
| committer | Cayetano Santos | 2020-07-12 13:15:49 +0200 |
| commit | 7dd29767b010562625fe0955d128b6ae5685660c (patch) | |
| tree | db16f0b363c7e7c6a0116e3a8420c6e5c18c2b4f | |
| parent | 1edbd41a937ab3b7db85edd4ec9d746e238df6d4 (diff) | |
| download | aur-7dd29767b010562625fe0955d128b6ae5685660c.tar.gz | |
update to 1.11.0
| -rw-r--r-- | .SRCINFO | 5 | ||||
| -rw-r--r-- | .gitlab-ci.yml | 7 | ||||
| -rw-r--r-- | PKGBUILD | 4 |
3 files changed, 6 insertions, 10 deletions
@@ -1,6 +1,6 @@ pkgbase = python-fusesoc pkgdesc = Package manager and build abstraction tool for FPGA/ASIC development. - pkgver = 1.10 + pkgver = 1.11 pkgrel = 0 url = http://github.com/olofk/fusesoc/ arch = any @@ -18,7 +18,8 @@ pkgbase = python-fusesoc provides = python-fusesoc conflicts = python-fusesoc-git options = !emptydirs - source = git+https://github.com/olofk/fusesoc#tag=1.10 + source = git+https://github.com/olofk/fusesoc#tag=1.11 md5sums = SKIP pkgname = python-fusesoc + diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index e14af1a346bd..11dc4112f2a7 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -8,7 +8,7 @@ stages: before_script: - pacman --noconfirm -Syu - - pacman --noconfirm -S sudo git fakeroot binutils + - pacman --noconfirm -S sudo git fakeroot binutils python-edalize - useradd -m notroot - echo "$DOSUDO" > /etc/sudoers.d/notroot @@ -18,11 +18,6 @@ build-package: stage: test script: - cd /home/notroot - - su notroot -c "git clone https://aur.archlinux.org/python-edalize.git" - - cd python-edalize - - su notroot -c "makepkg --noconfirm --syncdeps --rmdeps --install --clean" - - python -c 'import edalize; print("All OK")' - - cd /home/notroot - su notroot -c "git clone https://aur.archlinux.org/python-fusesoc.git" - cd python-fusesoc - su notroot -c "makepkg --noconfirm --syncdeps --rmdeps --install --clean" @@ -1,6 +1,6 @@ # Maintainer: csantosb <csantosb dot inventati dot org> pkgname=python-fusesoc -pkgver=1.10 +pkgver=1.11 pkgrel=0 pkgdesc="Package manager and build abstraction tool for FPGA/ASIC development." arch=('any') @@ -16,7 +16,7 @@ optdepends=('iverilog: for simulating verilog designs' 'gtkwave: for visualizing waveforms') options=(!emptydirs) -source=("git+https://github.com/olofk/fusesoc#tag=${pkgver}") +source=("git+https://github.com/olofk/fusesoc#tag=${pkgver}.${pkgrel}") md5sums=('SKIP') build() { |