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authorCayetano Santos2020-04-29 19:53:17 +0200
committerCayetano Santos2020-04-29 19:53:17 +0200
commitbb7d428e3b90cf4200298fe93dc194b31a090302 (patch)
treea8db7490549e4ae88f0592cb0bb8640eece553fa
parenta50386a3fd1731a6c543e162e0e10f29136a085d (diff)
downloadaur-bb7d428e3b90cf4200298fe93dc194b31a090302.tar.gz
remove dependency on jinja
-rw-r--r--.SRCINFO1
-rw-r--r--PKGBUILD2
2 files changed, 1 insertions, 2 deletions
diff --git a/.SRCINFO b/.SRCINFO
index 7ff2f1d132b6..4dcd2d9b1771 100644
--- a/.SRCINFO
+++ b/.SRCINFO
@@ -12,7 +12,6 @@ pkgbase = python-fusesoc
depends = python-setuptools
depends = python-pyaml
depends = python-jsonschema
- depends = python-jinja
optdepends = iverilog: for simulating verilog designs
optdepends = ghdl: for simulating VHDL designs
optdepends = gtkwave: for visualizing waveforms
diff --git a/PKGBUILD b/PKGBUILD
index 407c491e7f65..cef11c29710d 100644
--- a/PKGBUILD
+++ b/PKGBUILD
@@ -8,7 +8,7 @@ url="http://github.com/olofk/fusesoc/"
license=('GPLv3')
conflicts=('python-fusesoc-git')
provides=('python-fusesoc')
-depends=('python' 'python-edalize' 'python-setuptools' 'python-pyaml' 'python-jsonschema' 'python-jinja')
+depends=('python' 'python-edalize' 'python-setuptools' 'python-pyaml' 'python-jsonschema')
makedepends=('git' 'python-pip')
optdepends=('iverilog: for simulating verilog designs'