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| author | Cayetano Santos | 2020-03-16 20:13:22 +0100 |
|---|---|---|
| committer | Cayetano Santos | 2020-03-16 20:13:22 +0100 |
| commit | d056bd8180f5d247125d2ded571c1852e37fc62d (patch) | |
| tree | 9d6fb8ba7756bf65f8d47f94fffbbea76acbf2fd | |
| parent | 379d2a1afb8d7a17dae77a04149a4beb499f1adf (diff) | |
| download | aur-d056bd8180f5d247125d2ded571c1852e37fc62d.tar.gz | |
update srcinfo
| -rw-r--r-- | .SRCINFO | 7 |
1 files changed, 4 insertions, 3 deletions
@@ -1,6 +1,6 @@ pkgbase = python-fusesoc pkgdesc = Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python - pkgver = 1.9 + pkgver = 1.10 pkgrel = 0 url = http://github.com/olofk/fusesoc/ arch = any @@ -13,7 +13,8 @@ pkgbase = python-fusesoc provides = python-fusesoc conflicts = python-fusesoc options = !emptydirs - source = https://github.com/olofk/fusesoc/releases/download/1.9/fusesoc-1.9.tar.gz - md5sums = eec2d6fd3c8c68ce00b2eae7edb8e1a7 + source = git+https://github.com/olofk/fusesoc#tag=1.10 + md5sums = SKIP pkgname = python-fusesoc + |