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author | Simone Baratta | 2015-08-07 20:32:29 +0200 |
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committer | Simone Baratta | 2015-08-07 20:32:29 +0200 |
commit | 6f48692a90121bddfc3ab842a28e23c41ef94b32 (patch) | |
tree | 84bd3699ba04981197fcb8123548a50bf42f8462 | |
download | aur-6f48692a90121bddfc3ab842a28e23c41ef94b32.tar.gz |
First revision (hope)
-rw-r--r-- | .SRCINFO | 12 | ||||
-rw-r--r-- | PKGBUILD | 29 |
2 files changed, 41 insertions, 0 deletions
diff --git a/.SRCINFO b/.SRCINFO new file mode 100644 index 000000000000..0fe1c8930b1e --- /dev/null +++ b/.SRCINFO @@ -0,0 +1,12 @@ +pkgbase = smartsim-git + pkgdesc = SmartSim is a digital logic circuit design and simulation package. + pkgver = r73.20aa4bd + pkgrel = 1 + url = http://github.com/ashleynewson/SmartSim + arch = any + license = GPL3 + source = git+https://github.com/ashleynewson/SmartSim.git + md5sums = SKIP + +pkgname = smartsim-git + diff --git a/PKGBUILD b/PKGBUILD new file mode 100644 index 000000000000..f1c7df378ef6 --- /dev/null +++ b/PKGBUILD @@ -0,0 +1,29 @@ +# Maintainer: Simone Baratta -- Conte91 <at> gmail <dot> com +pkgname=smartsim-git +pkgver=r73.20aa4bd +pkgrel=1 +pkgdesc="SmartSim is a digital logic circuit design and simulation package." +arch=('any') +license=('GPL3') +_reponame='SmartSim' +_authorname='ashleynewson' +url="http://github.com/$_authorname/$_reponame" +source=("git+https://github.com/$_authorname/$_reponame.git") + +pkgver() { + cd "$srcdir/$_reponame" + echo "r`git rev-list --count HEAD`.`git rev-parse --short HEAD`" +} + +build(){ + cd "$srcdir/$_reponame" + ./configure --prefix=/usr + make +} + +package() { + cd $srcdir/$_reponame + make DESTDIR=$pkgdir install +} + +md5sums=('SKIP') |