diff options
| author | VitalyR | 2023-06-01 15:15:41 +0800 |
|---|---|---|
| committer | VitalyR | 2023-06-01 15:15:41 +0800 |
| commit | bdfdce88b02bfb46278a6d707cdf54c3f40153f9 (patch) | |
| tree | 631303e16cf6905b868da128171dd5362b0c8994 | |
| parent | 3cfcd3828b54ba4498efdd79fb8bcefc171fa932 (diff) | |
| download | aur-bdfdce88b02bfb46278a6d707cdf54c3f40153f9.tar.gz | |
Update to 2023.1
| -rw-r--r-- | .SRCINFO | 6 | ||||
| -rw-r--r-- | PKGBUILD | 11 |
2 files changed, 9 insertions, 8 deletions
@@ -1,6 +1,6 @@ pkgbase = vivado pkgdesc = FPGA/CPLD design suite for Xilinx devices - pkgver = 2022.2 + pkgver = 2023.1 pkgrel = 1 url = https://www.xilinx.com/products/design-tools/vivado.html arch = x86_64 @@ -18,9 +18,9 @@ pkgbase = vivado optdepends = matlab: Model Composer optdepends = qt4: Model Composer options = !strip - source = file:///Xilinx_Unified_2022.2_1014_8888.tar.gz + source = file:///Xilinx_Unified_2023.1_0507_1903.tar.gz source = spoof_homedir.c - md5sums = 4b4e84306eb631fe67d3efb469122671 + md5sums = f2011ceba52b109e3551c1d3189a8c9c md5sums = 69d14ad64f6ec44e041eaa8ffcb6f87c pkgname = vivado @@ -1,3 +1,4 @@ +# Maintainer: VitalyR <vr@vitalyr.com> # Maintainer: xiretza <aur@xiretza.xyz> # Contributor: Darren Wu <$(base64 --decode <<<'ZGFycmVuMTk5NzA4MTBAZ21haWwuY29tCg==')> @@ -5,7 +6,7 @@ # # 1. Log in to xilinx.com # 2. Go to https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools.html -# 3. Download "Xilinx Unified Installer SFD (TAR/GZIP)" - WARNING: This file is >90GB in size +# 3. Download "Xilinx Unified Installer SFD (TAR/GZIP)" - WARNING: This file is >110GB in size # 4. Place the .tar.gz in the same directory as the PKGBUILD # 5. Build! # @@ -13,7 +14,7 @@ # # SOME MORE NOTES: # -# This package is huge. The download alone is a barely-compressed 90GB .tar.gz (extracts to ~90GB) +# This package is huge. The download alone is a barely-compressed 110GB .tar.gz (extracts to ~110GB) # and the final zstd-compressed package is another 20GB. Reserve at least 200GB in total for building. # # It can also take up to two hours to build, being mostly limited by I/O and single-thread @@ -27,8 +28,8 @@ pkgname=vivado _srcname=Xilinx_Unified -pkgver=2022.2 -_more_ver=1014_8888 +pkgver=2023.1 +_more_ver=0507_1903 pkgrel=1 pkgdesc="FPGA/CPLD design suite for Xilinx devices" url="https://www.xilinx.com/products/design-tools/vivado.html" @@ -53,7 +54,7 @@ source=("file:///${_srcname}_${pkgver}_${_more_ver}.tar.gz" 'spoof_homedir.c') # checksum from https://www.xilinx.com/support/download.html -md5sums=('4b4e84306eb631fe67d3efb469122671' +md5sums=('f2011ceba52b109e3551c1d3189a8c9c' '69d14ad64f6ec44e041eaa8ffcb6f87c') # takes forever for probably minimal gain |