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| author | Xiretza | 2021-06-25 17:40:04 +0200 |
|---|---|---|
| committer | Xiretza | 2021-06-25 17:40:04 +0200 |
| commit | c0dba52eeaef2edf15d51a87a2727fb1208140eb (patch) | |
| tree | 447a4b2ca4a02d4d7a4f1d60a6017b5078517285 | |
| parent | 9f5783e04dabc7da2c43d4c4d5e38e4a781f1804 (diff) | |
| download | aur-c0dba52eeaef2edf15d51a87a2727fb1208140eb.tar.gz | |
Update to 2021.1
| -rw-r--r-- | .SRCINFO | 7 | ||||
| -rw-r--r-- | PKGBUILD | 12 |
2 files changed, 9 insertions, 10 deletions
@@ -1,6 +1,6 @@ pkgbase = vivado pkgdesc = FPGA/CPLD design suite for Xilinx devices - pkgver = 2020.2 + pkgver = 2021.1 pkgrel = 1 url = https://www.xilinx.com/products/design-tools/vivado.html arch = x86_64 @@ -13,10 +13,9 @@ pkgbase = vivado optdepends = digilent.adept.runtime optdepends = digilent.adept.utilities options = !strip - source = file:///Xilinx_Unified_2020.2_1118_1232.tar.gz + source = file:///Xilinx_Unified_2021.1_0610_2318.tar.gz source = spoof_homedir.c - md5sums = 523e8596f114ab5e389c14df50ecb1d8 + md5sums = 3a88784dbed40ab1008c28b040717f72 md5sums = 69d14ad64f6ec44e041eaa8ffcb6f87c pkgname = vivado - @@ -5,7 +5,7 @@ # # 1. Log in to xilinx.com # 2. Go to https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools.html -# 3. Download "All OS installer Single-File Download (TAR/GZIP)" - WARNING: This file is >35GB in size +# 3. Download "Xilinx Unified Installer SFD (TAR/GZIP)" - WARNING: This file is >50GB in size # 4. Place the .tar.gz in the same directory as the PKGBUILD # 5. Build! # @@ -13,7 +13,7 @@ # # SOME MORE NOTES: # -# This package is huge. The download alone is a 44GB .tar.gz, which decompresses to ~45GB, +# This package is huge. The download alone is a 52GB .tar.gz, which decompresses to ~54GB, # and the final zstd-compressed package is another 21GB. Reserve ~150GB in total for building. # # It can also take up to two hours to build, being mostly limited by I/O and single-thread @@ -27,8 +27,8 @@ pkgname=vivado _srcname=Xilinx_Unified -pkgver=2020.2 -_more_ver=1118_1232 +pkgver=2021.1 +_more_ver=0610_2318 pkgrel=1 pkgdesc="FPGA/CPLD design suite for Xilinx devices" url="https://www.xilinx.com/products/design-tools/vivado.html" @@ -46,7 +46,7 @@ source=("file:///${_srcname}_${pkgver}_${_more_ver}.tar.gz" 'spoof_homedir.c') # checksum from https://www.xilinx.com/support/download.html -md5sums=('523e8596f114ab5e389c14df50ecb1d8' +md5sums=('3a88784dbed40ab1008c28b040717f72' '69d14ad64f6ec44e041eaa8ffcb6f87c') # takes forever for probably minimal gain @@ -69,7 +69,7 @@ package() { --batch Install \ --agree XilinxEULA,3rdPartyEULA,WebTalkTerms \ --product Vivado \ - --edition 'Vivado HL WebPACK' \ + --edition 'Vivado ML Standard' \ --location "$pkgdir/opt/Xilinx" # install udev rules |