updpkg: linux-tqc-a01 5.17.7

author: yjun 2022-05-17 12:16:32 +0800
committer: yjun 2022-05-17 12:16:32 +0800
commit: d66c7d0fc0b35270f9fe591a311563cc0d851555 (patch)
tree: 78708ccbe7b46d0494838100815004e5f5fff152
parent: df61abd38d06cbb1f4eca16f1e070d986a8b6dbd (diff)
download: aur-d66c7d0fc0b35270f9fe591a311563cc0d851555.tar.gz
36 files changed, 4117 insertions, 2018 deletions
diff --git a/.SRCINFO b/.SRCINFO
index 3d3e55981ce0..7a4ea1c9ed21 100644
--- a/.SRCINFO
+++ b/.SRCINFO
@@ -1,5 +1,5 @@
 pkgbase = linux-tqc-a01
-	pkgver = 5.14.8
+	pkgver = 5.17.7
 	pkgrel = 1
 	url = http://www.kernel.org/
 	arch = aarch64
@@ -14,50 +14,72 @@ pkgbase = linux-tqc-a01
 	makedepends = vboot-utils
 	makedepends = dtc
 	options = !strip
-	source = http://cdn.kernel.org/pub/linux/kernel/v5.x/linux-5.14.tar.xz
+	source = https://mirror.bjtu.edu.cn/kernel/linux/kernel/v5.x/linux-5.17.tar.xz
 	source = sun50i-h6-tqc-a01.dts
-	source = 0001-mfd-Add-support-for-AC200.patch
-	source = 0001-HACK-h6-Add-HDMI-sound-card.patch
 	source = 0001-make-proc-cpuinfo-consistent-on-arm64-and-arm.patch
-	source = 0002-net-phy-Add-support-for-AC200-EPHY.patch
-	source = 0002-net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regu.patch
-	source = 0003-net-stmmac-sun8i-Rename-PHY-regulator-variable-to-re.patch
-	source = 0003-arm64-dts-allwinner-h6-Add-AC200-EPHY-related-nodes.patch
-	source = 0004-net-stmmac-sun8i-Add-support-for-enabling-a-regulato.patch
-	source = 0005-drm-gem-cma-Export-with-handle-allocator.patch
-	source = 0006-drm-sun4i-Add-GEM-allocator.patch
-	source = 0010-general-h6-add-dma-i2c-ir-spi-uart.patch
 	source = 0011-dts-h6-tqc-a01-cpu-opp-2ghz.patch
 	source = 0012-arm64-h6-gpu-devfreq-enable.patch
-	source = 0040-wip-H6-deinterlace.patch
-	source = 0041-arm64-dts-h6-deinterlace.patch
+	source = 0012-fix-h6-emmc.patch
+	source = 0013-x-fix-h6-emmc-dts.patch
+	source = arm64-dts-sun50i-h6-Add-AC200-EPHY-related-nodes.patch
+	source = drv-net-phy-Add-support-for-AC200-EPHY.patch
+	source = drv-mfd-Add-support-for-AC200.patch
+	source = net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch
+	source = net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch
+	source = net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch
+	source = arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch
+	source = 0009-allwinner-h6-support-ac200-audio-codec.patch
+	source = 0010-allwinner-add-sunxi_get_soc_chipid-and-sunxi_get_ser.patch
+	source = arm64-dts-sun50i-h6.dtsi-improve-thermals.patch
+	source = arm64-dts-allwinner-h6-Add-SCPI-protocol.patch
+	source = arm64-dts-allwinner-h6-Protect-SCP-clocks.patch
+	source = drv-pinctrl-sunxi-pinctrl-sun50i-h6.c-GPIO-disable_strict_mode.patch
+	source = WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch
+	source = HACK-media-uapi-hevc-tiles-and-num_slices.patch
+	source = Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch
+	source = drv-media-cedrus-10-bit-HEVC-support.patch
+	source = drv-media-cedrus-Add-callback-for-buffer-cleanup.patch
+	source = drv-media-cedrus-h264-Improve-buffer-management.patch
+	source = drv-media-cedrus-hevc-Improve-buffer-management.patch
+	source = drv-media-cedrus-hevc-tiles-hack.patch
 	source = config
 	source = linux.preset
 	source = 60-linux.hook
 	source = 90-linux.hook
-	source = https://cdn.kernel.org/pub/linux/kernel/v5.x/patch-5.14.8.xz
-	md5sums = a082ef5748b813abca0649dab8be5f52
-	md5sums = 46d921dba031a9f397955a787c71911e
-	md5sums = 17aa0c69176c68cd98b4522740a1b747
-	md5sums = 2285d81ec6fb859d34b7abfd46a59550
+	source = https://mirror.bjtu.edu.cn/kernel/linux/kernel/v5.x/patch-5.17.7.xz
+	md5sums = 07321a70a48d062cebd0358132f11771
+	md5sums = 5dc58208abd2ad11ad2aa67fadf1c66f
 	md5sums = 7a18066683f3351b2bbd2653db783f80
-	md5sums = bc7904920675ba8d38f21d46ffac33b5
-	md5sums = 94a69594f90309c50c83a5cc8579fb54
-	md5sums = e1868e41094baff9eceba481fc097c79
-	md5sums = 2d2de8db5e0c7d8f51a05fd33000c19a
-	md5sums = 5d42a68276c8f9e8b3de040fa2579b84
-	md5sums = 335382823f6dc2aae2f6038b7aee339e
-	md5sums = cb38b30491472097c3b9b475de39127f
-	md5sums = bc65c0b9e4d6fb2fe3a81b8358886885
 	md5sums = 74baf0cb243b3abd5e38f0131c95408f
-	md5sums = 05c4d9cbe622d5ff15e6b84b1c5c1a70
-	md5sums = d1543c205b4faf9be4552d4308228217
-	md5sums = e4ef0ae46cdfb23abb11d729452f68b2
-	md5sums = 80fec552244267a059d06399c1a3c931
+	md5sums = 947f64e1c0eec0564cb683940a5af51f
+	md5sums = 6c58c6697e1275038acf579251c69d31
+	md5sums = 2d7918618ec227b65d35078b3c7862ce
+	md5sums = 5cf059c6de6dbee8d20041dcb735f5b1
+	md5sums = f0826f12d7b1f597fba32913e8580543
+	md5sums = 714a3df875f3a05aee07c7c464ad3fe0
+	md5sums = c6bb7c8ce8d41c93d5c2b70f4110135f
+	md5sums = abe164c89da5fb50bb4c866c1d5fe03b
+	md5sums = 72a95b87caccf7f36dff15ed1e4a6df9
+	md5sums = f8aa3197a5c1e6d01cb1809c31cc2d92
+	md5sums = eda5ceb6d7f63318bba5ec63c601ae93
+	md5sums = a709f3089148690f41c739275e66e9b0
+	md5sums = 99368425ced226332796b7f69fda3a2b
+	md5sums = 6ab19f7244b9f82f56edabeb7e1e1004
+	md5sums = a95bab65e3009909138c0982ab7234aa
+	md5sums = 113ec102b9b94a8c8c44dbde7e9b8d59
+	md5sums = 196331c28fc1c77f78d7c6378cfb9e9e
+	md5sums = ec38509f11f44b412f4de990502a3fb7
+	md5sums = 52d4ddae2d47320b97ce311106b407af
+	md5sums = 2eb1edf94864c3c0b2a6f82463f84d67
+	md5sums = 28ce48cd57b8776a75f4fed54569ffd1
+	md5sums = f5e2e35d9f0955cef5cf2332f901ff09
+	md5sums = b36af4f711a0aeb3f0edeb522a9e97bf
+	md5sums = dafb6c0da0e1c6be55c18fc50c850fab
+	md5sums = ce726485a1ab9c726037aa02fdfa15f1
 	md5sums = 66e0ae63183426b28c0ec0c7e10b5e16
 	md5sums = ce6c81ad1ad1f8b333fd6077d47abdaf
 	md5sums = 3dc88030a8f2f5a5f97266d99b149f77
-	md5sums = 767e2bd13b4f1497f7500877792cbff2
+	md5sums = c942f79b0f310ca6e8d5828fad539a7f
 
 pkgname = linux-tqc-a01
 	pkgdesc = The Linux Kernel and modules - AArch64 kernel for TQC A01
@@ -67,7 +89,7 @@ pkgname = linux-tqc-a01
 	depends = kmod
 	depends = mkinitcpio>=0.7
 	optdepends = crda: to set the correct wireless channels of your country
-	provides = linux=5.14.8
+	provides = linux=5.17.7
 	provides = WIREGUARD-MODULE
 	conflicts = linux
 	replaces = linux-armv8
@@ -75,5 +97,5 @@ pkgname = linux-tqc-a01
 
 pkgname = linux-tqc-a01-headers
 	pkgdesc = Header files and scripts for building modules for linux kernel - AArch64 kernel for TQC A01
-	provides = linux-headers=5.14.8
+	provides = linux-headers=5.17.7
 	conflicts = linux-headers
diff --git a/0001-HACK-h6-Add-HDMI-sound-card.patch b/0001-HACK-h6-Add-HDMI-sound-card.patch
deleted file mode 100644
index 71663f441cac..000000000000
--- a/0001-HACK-h6-Add-HDMI-sound-card.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jernej Skrabec <jernej.skrabec@siol.net>
-Date: Sat, 16 Jan 2021 10:58:14 +0100
-Subject: [PATCH] HACK: h6: Add HDMI sound card
-
-Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
----
- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 20 +++++++++++++++++++-
- 1 file changed, 19 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
-@@ -108,6 +108,24 @@
- 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- 	};
- 
-+	sound_hdmi: sound {
-+		compatible = "simple-audio-card";
-+		simple-audio-card,format = "i2s";
-+		simple-audio-card,name = "allwinner-hdmi";
-+		simple-audio-card,mclk-fs = <128>;
-+		simple-audio-card,frame-inversion;
-+
-+		simple-audio-card,codec {
-+			sound-dai = <&hdmi>;
-+		};
-+
-+		simple-audio-card,cpu {
-+			sound-dai = <&i2s1>;
-+			dai-tdm-slot-num = <2>;
-+			dai-tdm-slot-width = <32>;
-+		};
-+	};
-+
- 	soc {
- 		compatible = "simple-bus";
- 		#address-cells = <1>;
-@@ -652,7 +670,6 @@
- 			dmas = <&dma 4>, <&dma 4>;
- 			resets = <&ccu RST_BUS_I2S1>;
- 			dma-names = "rx", "tx";
--			status = "disabled";
- 		};
- 
- 		spdif: spdif@5093000 {
-@@ -785,6 +802,7 @@
- 		};
- 
- 		hdmi: hdmi@6000000 {
-+			#sound-dai-cells = <0>;
- 			compatible = "allwinner,sun50i-h6-dw-hdmi";
- 			reg = <0x06000000 0x10000>;
- 			reg-io-width = <1>;
diff --git a/0005-drm-gem-cma-Export-with-handle-allocator.patch b/0005-drm-gem-cma-Export-with-handle-allocator.patch
deleted file mode 100644
index b620041bd910..000000000000
--- a/0005-drm-gem-cma-Export-with-handle-allocator.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From ea69ff188dd5d9ac7162f05a22bf299b83a7536e Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Mon, 7 Dec 2015 09:33:28 +0100
-Subject: [PATCH 005/146] drm: gem: cma: Export with handle allocator
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- drivers/gpu/drm/drm_gem_cma_helper.c | 3 ++-
- include/drm/drm_gem_cma_helper.h     | 4 ++++
- 2 files changed, 6 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/drm_gem_cma_helper.c b/drivers/gpu/drm/drm_gem_cma_helper.c
-index 80a5115c3846..077c61f065d9 100644
---- a/drivers/gpu/drm/drm_gem_cma_helper.c
-+++ b/drivers/gpu/drm/drm_gem_cma_helper.c
-@@ -142,7 +142,7 @@ EXPORT_SYMBOL_GPL(drm_gem_cma_create);
-  * A struct drm_gem_cma_object * on success or an ERR_PTR()-encoded negative
-  * error code on failure.
-  */
--static struct drm_gem_cma_object *
-+struct drm_gem_cma_object *
- drm_gem_cma_create_with_handle(struct drm_file *file_priv,
- 			       struct drm_device *drm, size_t size,
- 			       uint32_t *handle)
-@@ -169,6 +169,7 @@ drm_gem_cma_create_with_handle(struct drm_file *file_priv,
- 
- 	return cma_obj;
- }
-+EXPORT_SYMBOL_GPL(drm_gem_cma_create_with_handle);
- 
- /**
-  * drm_gem_cma_free_object - free resources associated with a CMA GEM object
-diff --git a/include/drm/drm_gem_cma_helper.h b/include/drm/drm_gem_cma_helper.h
-index 19777145cf8e..79f397c91517 100644
---- a/include/drm/drm_gem_cma_helper.h
-+++ b/include/drm/drm_gem_cma_helper.h
-@@ -79,6 +79,10 @@ int drm_gem_cma_mmap(struct file *filp, struct vm_area_struct *vma);
- /* allocate physical memory */
- struct drm_gem_cma_object *drm_gem_cma_create(struct drm_device *drm,
- 					      size_t size);
-+struct drm_gem_cma_object *
-+drm_gem_cma_create_with_handle(struct drm_file *file_priv,
-+			       struct drm_device *drm, size_t size,
-+			       uint32_t *handle);
- 
- extern const struct vm_operations_struct drm_gem_cma_vm_ops;
- 
--- 
-2.17.1
-
diff --git a/0006-drm-sun4i-Add-GEM-allocator.patch b/0006-drm-sun4i-Add-GEM-allocator.patch
deleted file mode 100644
index 58557aa7768b..000000000000
--- a/0006-drm-sun4i-Add-GEM-allocator.patch
+++ /dev/null
@@ -1,102 +0,0 @@
-From b143de6aef8be007256082e0f89606b7f5e3c757 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Mon, 7 Dec 2015 09:47:34 +0100
-Subject: [PATCH 006/146] drm/sun4i: Add GEM allocator
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- drivers/gpu/drm/sun4i/sun4i_drv.c | 27 +++++++++++++++++++++++++++
- include/uapi/drm/sun4i_drm.h      | 29 +++++++++++++++++++++++++++++
- 2 files changed, 56 insertions(+)
- create mode 100644 include/uapi/drm/sun4i_drm.h
-
-diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
-index 8b0cd08034e0..9f5de14fb2fe 100644
---- a/drivers/gpu/drm/sun4i/sun4i_drv.c
-+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
-@@ -22,6 +22,8 @@
- #include <drm/drm_fb_helper.h>
- #include <drm/drm_of.h>
- 
-+#include <uapi/drm/sun4i_drm.h>
-+
- #include "sun4i_drv.h"
- #include "sun4i_frontend.h"
- #include "sun4i_framebuffer.h"
-@@ -30,6 +32,27 @@
- 
- DEFINE_DRM_GEM_CMA_FOPS(sun4i_drv_fops);
- 
-+static int sun4i_gem_create_ioctl(struct drm_device *drm, void *data,
-+				  struct drm_file *file_priv)
-+{
-+	struct drm_sun4i_gem_create *args = data;
-+	struct drm_gem_cma_object *cma_obj;
-+	size_t size;
-+
-+	/* The Mali requires a 64 bytes alignment */
-+	size = ALIGN(args->size, 64);
-+
-+	cma_obj = drm_gem_cma_create_with_handle(file_priv, drm, size,
-+						 &args->handle);
-+
-+	return PTR_ERR_OR_ZERO(cma_obj);
-+}
-+
-+static const struct drm_ioctl_desc sun4i_drv_ioctls[] = {
-+	DRM_IOCTL_DEF_DRV(SUN4I_GEM_CREATE, sun4i_gem_create_ioctl,
-+			  DRM_UNLOCKED | DRM_AUTH),
-+};
-+
- static const struct drm_driver sun4i_drv_driver = {
- 	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
- 
-@@ -42,6 +65,10 @@ static struct drm_driver sun4i_drv_driver = {
- 	.major			= 1,
- 	.minor			= 0,
- 
-+	/* Custom ioctls */
-+	.ioctls			= sun4i_drv_ioctls,
-+	.num_ioctls		= ARRAY_SIZE(sun4i_drv_ioctls),
-+
- 	/* GEM Operations */
- 	.dumb_create		= drm_gem_cma_dumb_create,
- 	.gem_free_object_unlocked = drm_gem_cma_free_object,
-diff --git a/include/uapi/drm/sun4i_drm.h b/include/uapi/drm/sun4i_drm.h
-new file mode 100644
-index 000000000000..67b9dd4ee594
---- /dev/null
-+++ b/include/uapi/drm/sun4i_drm.h
-@@ -0,0 +1,29 @@
-+/*
-+ * Copyright (C) 2015 Free Electrons
-+ * Copyright (C) 2015 NextThing Co
-+ *
-+ * Maxime Ripard <maxime.ripard@free-electrons.com>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ */
-+
-+#ifndef _UAPI_SUN4I_DRM_H_
-+#define _UAPI_SUN4I_DRM_H_
-+
-+#include <drm/drm.h>
-+
-+struct drm_sun4i_gem_create {
-+	__u64 size;
-+	__u32 flags;
-+	__u32 handle;
-+};
-+
-+#define DRM_SUN4I_GEM_CREATE		0x00
-+
-+#define DRM_IOCTL_SUN4I_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_SUN4I_GEM_CREATE, \
-+						 struct drm_sun4i_gem_create)
-+
-+#endif
--- 
-2.17.1
-
diff --git a/0009-allwinner-h6-support-ac200-audio-codec.patch b/0009-allwinner-h6-support-ac200-audio-codec.patch
new file mode 100644
index 000000000000..7f4c6273e756
--- /dev/null
+++ b/0009-allwinner-h6-support-ac200-audio-codec.patch
@@ -0,0 +1,1878 @@
+From 818b55daa8e217a54a8baf61943ca3b302371f78 Mon Sep 17 00:00:00 2001
+From: afaulkner420 <afaulkner420@gmail.com>
+Date: Fri, 25 Mar 2022 20:33:02 +0000
+Subject: [PATCH 09/11] allwinner: h6: Support ac200 audio codec
+
+---
+ drivers/mfd/Makefile                   |    2 +-
+ drivers/mfd/{ac200.c => sunxi-ac200.c} |   16 +-
+ include/linux/mfd/ac200.h              |    2 +
+ sound/soc/codecs/Kconfig               |    8 +
+ sound/soc/codecs/Makefile              |    2 +
+ sound/soc/codecs/acx00.c               | 1371 ++++++++++++++++++++++++
+ sound/soc/codecs/acx00.h               |  356 ++++++
+ 7 files changed, 1755 insertions(+), 2 deletions(-)
+ rename drivers/mfd/{ac200.c => sunxi-ac200.c} (93%)
+ mode change 100644 => 100755
+ create mode 100644 sound/soc/codecs/acx00.c
+ create mode 100644 sound/soc/codecs/acx00.h
+
+diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
+index 7edc825f9..669f838ab 100644
+--- a/drivers/mfd/Makefile
++++ b/drivers/mfd/Makefile
+@@ -142,7 +142,7 @@ obj-$(CONFIG_MFD_DA9052_SPI)	+= da9052-spi.o
+ obj-$(CONFIG_MFD_DA9052_I2C)	+= da9052-i2c.o
+ 
+ obj-$(CONFIG_MFD_AC100)		+= ac100.o
+-obj-$(CONFIG_MFD_AC200)		+= ac200.o
++obj-$(CONFIG_MFD_AC200)		+= sunxi-ac200.o
+ obj-$(CONFIG_MFD_AXP20X)	+= axp20x.o
+ obj-$(CONFIG_MFD_AXP20X_I2C)	+= axp20x-i2c.o
+ obj-$(CONFIG_MFD_AXP20X_RSB)	+= axp20x-rsb.o
+diff --git a/drivers/mfd/ac200.c b/drivers/mfd/sunxi-ac200.c
+old mode 100644
+new mode 100644
+similarity index 93%
+rename from drivers/mfd/ac200.c
+rename to drivers/mfd/sunxi-ac200.c
+index 570573790..368a54587
+--- a/drivers/mfd/ac200.c
++++ b/drivers/mfd/sunxi-ac200.c
+@@ -41,6 +41,7 @@ static const struct regmap_range_cfg ac200_range_cfg[] = {
+ };
+ 
+ static const struct regmap_config ac200_regmap_config = {
++	.name = "ac200",
+ 	.reg_bits	= 8,
+ 	.val_bits	= 16,
+ 	.ranges		= ac200_range_cfg,
+@@ -75,6 +76,10 @@ static const struct mfd_cell ac200_cells[] = {
+ 		.resources	= ephy_resource,
+ 		.of_compatible	= "x-powers,ac200-ephy",
+ 	},
++	{
++		.name = "acx00-codec",
++		.of_compatible	= "x-powers,ac200-codec",
++	},
+ };
+ 
+ static int ac200_i2c_probe(struct i2c_client *i2c,
+@@ -97,8 +102,17 @@ static int ac200_i2c_probe(struct i2c_client *i2c,
+ 		return ret;
+ 	}
+ 
+-	/* do a reset to put chip in a known state */
++	ac200->clk = devm_clk_get(dev, NULL);
++	if (IS_ERR(ac200->clk)) {
++	      dev_err(dev, "Can't obtain the clock!\n");
++	      return PTR_ERR(ac200->clk);
++	}
+ 
++	ret = clk_prepare_enable(ac200->clk);
++	if (ret)
++	      return ret;
++
++	/* do a reset to put chip in a known state */
+ 	ret = regmap_write(ac200->regmap, AC200_SYS_CONTROL, 0);
+ 	if (ret)
+ 		return ret;
+diff --git a/include/linux/mfd/ac200.h b/include/linux/mfd/ac200.h
+index 0c677094a..c8c140226 100644
+--- a/include/linux/mfd/ac200.h
++++ b/include/linux/mfd/ac200.h
+@@ -9,6 +9,7 @@
+ #define __LINUX_MFD_AC200_H
+ 
+ #include <linux/regmap.h>
++#include <linux/clk.h>
+ 
+ /* interface registers (can be accessed from any page) */
+ #define AC200_TWI_CHANGE_TO_RSB		0x3E
+@@ -201,6 +202,7 @@
+ #define AC200_IC_CHARA1			0xA1F2
+ 
+ struct ac200_dev {
++	struct clk                    *clk;
+ 	struct regmap			*regmap;
+ 	struct regmap_irq_chip_data	*regmap_irqc;
+ };
+diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
+index 6fd8bc760..d98d9b300 100644
+--- a/sound/soc/codecs/Kconfig
++++ b/sound/soc/codecs/Kconfig
+@@ -1943,4 +1943,12 @@ config SND_SOC_LPASS_TX_MACRO
+ 	select REGMAP_MMIO
+ 	tristate "Qualcomm TX Macro in LPASS(Low Power Audio SubSystem)"
+ 
++config SND_SOC_ACX00
++	tristate "ACX00 Codec"
++	select MFD_ACX00
++	default n
++	help
++		ACX00 now used as SUN50IW6 internal Codec, Connect Through I2S0.
++		Say Y or M if you want to add support internal audio codec.
++
+ endmenu
+diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
+index bb3607f33..04ea67b1a 100644
+--- a/sound/soc/codecs/Makefile
++++ b/sound/soc/codecs/Makefile
+@@ -318,6 +318,7 @@ snd-soc-wm9713-objs := wm9713.o
+ snd-soc-wm-hubs-objs := wm_hubs.o
+ snd-soc-wsa881x-objs := wsa881x.o
+ snd-soc-zl38060-objs := zl38060.o
++snd-soc-acx00-objs := acx00.o
+ # Amp
+ snd-soc-max9877-objs := max9877.o
+ snd-soc-max98504-objs := max98504.o
+@@ -650,6 +651,7 @@ obj-$(CONFIG_SND_SOC_WM_ADSP)	+= snd-soc-wm-adsp.o
+ obj-$(CONFIG_SND_SOC_WM_HUBS)	+= snd-soc-wm-hubs.o
+ obj-$(CONFIG_SND_SOC_WSA881X)	+= snd-soc-wsa881x.o
+ obj-$(CONFIG_SND_SOC_ZL38060)	+= snd-soc-zl38060.o
++obj-$(CONFIG_SND_SOC_ACX00)	+= snd-soc-acx00.o
+ 
+ # Amp
+ obj-$(CONFIG_SND_SOC_MAX9877)	+= snd-soc-max9877.o
+diff --git a/sound/soc/codecs/acx00.c b/sound/soc/codecs/acx00.c
+new file mode 100644
+index 000000000..ab7467e4e
+--- /dev/null
++++ b/sound/soc/codecs/acx00.c
+@@ -0,0 +1,1371 @@
++/*
++ * acx00.c  --  ACX00 ALSA Soc Audio Codec driver
++ *
++ * (C) Copyright 2010-2016 Allwinnertech Technology., Ltd.
++ *
++ * Author: Wolfgang Huang <huangjinhui@allwinner.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/firmware.h>
++#include <linux/delay.h>
++#include <linux/pm.h>
++#include <linux/i2c.h>
++#include <linux/clk.h>
++#include <linux/of_gpio.h>
++#include <linux/of_device.h>
++#include <linux/of_platform.h>
++#include <linux/debugfs.h>
++#include <linux/slab.h>
++#include <linux/mfd/ac200.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/initval.h>
++#include <sound/tlv.h>
++#include <linux/workqueue.h>
++
++#include "acx00.h"
++
++
++#define ACX00_DEF_VOL		0x9F9F
++#undef ACX00_DAPM_LINEOUT
++
++struct acx00_priv {
++	struct ac200_dev *acx00;	/* parent mfd device struct */
++	struct snd_soc_component *component;
++	struct clk *clk;
++	unsigned int sample_rate;
++	unsigned int fmt;
++	unsigned int enable;
++	unsigned int spk_gpio;
++	unsigned int switch_gpio;
++	bool spk_gpio_used;
++	struct mutex mutex;
++	struct delayed_work spk_work;
++	struct delayed_work resume_work;
++};
++
++struct sample_rate {
++	unsigned int samplerate;
++	unsigned int rate_bit;
++};
++
++static const struct sample_rate sample_rate_conv[] = {
++	{44100, 7},
++	{48000, 8},
++	{8000, 0},
++	{32000, 6},
++	{22050, 4},
++	{24000, 5},
++	{16000, 3},
++	{11025, 1},
++	{12000, 2},
++	{192000, 10},
++	{96000, 9},
++};
++
++void __iomem *io_stat_addr;
++
++static const DECLARE_TLV_DB_SCALE(i2s_mixer_adc_tlv, -600, 600, 1);
++static const DECLARE_TLV_DB_SCALE(i2s_mixer_dac_tlv, -600, 600, 1);
++static const DECLARE_TLV_DB_SCALE(dac_mixer_adc_tlv, -600, 600, 1);
++static const DECLARE_TLV_DB_SCALE(dac_mixer_dac_tlv, -600, 600, 1);
++static const DECLARE_TLV_DB_SCALE(line_out_tlv, -450, 150, 0);
++static const DECLARE_TLV_DB_SCALE(mic_out_tlv, -450, 150, 0);
++static const DECLARE_TLV_DB_SCALE(phoneout_tlv, -450, 150, 0);
++static const DECLARE_TLV_DB_SCALE(adc_input_tlv, -450, 150, 0);
++static const DECLARE_TLV_DB_SCALE(lineout_tlv, -4800, 150, 1);
++static const unsigned int mic_boost_tlv[] = {
++	TLV_DB_RANGE_HEAD(2),
++	0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
++	1, 7, TLV_DB_SCALE_ITEM(2400, 300, 0),
++};
++
++static const struct snd_kcontrol_new acx00_codec_controls[] = {
++	SOC_DOUBLE_TLV("I2S Mixer ADC Volume", AC_I2S_MIXER_GAIN,
++			I2S_MIXERL_GAIN_ADC, I2S_MIXERR_GAIN_ADC,
++			0x1, 0, i2s_mixer_adc_tlv),
++	SOC_DOUBLE_TLV("I2S Mixer DAC Volume", AC_I2S_MIXER_GAIN,
++			I2S_MIXERL_GAIN_DAC, I2S_MIXERR_GAIN_DAC,
++			0x1, 0, i2s_mixer_dac_tlv),
++	SOC_DOUBLE_TLV("DAC Mixer ADC Volume", AC_DAC_MIXER_GAIN,
++			DAC_MIXERL_GAIN_ADC, DAC_MIXERR_GAIN_ADC,
++			0x1, 0, dac_mixer_adc_tlv),
++	SOC_DOUBLE_TLV("DAC Mxier DAC Volume", AC_DAC_MIXER_GAIN,
++			DAC_MIXERL_GAIN_DAC, DAC_MIXERR_GAIN_DAC,
++			0x1, 0, dac_mixer_dac_tlv),
++	SOC_SINGLE_TLV("Line Out Mixer Volume", AC_OUT_MIXER_CTL,
++			OUT_MIXER_LINE_VOL, 0x7, 0, line_out_tlv),
++	SOC_DOUBLE_TLV("MIC Out Mixer Volume", AC_OUT_MIXER_CTL,
++			OUT_MIXER_MIC1_VOL, OUT_MIXER_MIC2_VOL,
++			0x7, 0, mic_out_tlv),
++	SOC_SINGLE_TLV("ADC Input Volume", AC_ADC_MIC_CTL,
++			ADC_GAIN, 0x07, 0, adc_input_tlv),
++	SOC_SINGLE_TLV("Master Volume", AC_LINEOUT_CTL,
++			LINEOUT_VOL, 0x1f, 0, lineout_tlv),
++	SOC_SINGLE_TLV("MIC1 Boost Volume", AC_ADC_MIC_CTL,
++			MIC1_BOOST, 0x07, 0, mic_boost_tlv),
++	SOC_SINGLE_TLV("MIC2 Boost Volume", AC_ADC_MIC_CTL,
++			MIC2_BOOST, 0x07, 0, mic_boost_tlv),
++};
++
++/* Enable I2S & DAC clk, then enable the DAC digital part */
++static int acx00_playback_event(struct snd_soc_dapm_widget *w,
++				struct snd_kcontrol *k, int event)
++{
++	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
++
++	switch (event) {
++	case	SND_SOC_DAPM_POST_PMU:
++		snd_soc_component_update_bits(component, AC_SYS_CLK_CTL,
++				(0x1<<SYS_CLK_DAC), (0x1<<SYS_CLK_DAC));
++		snd_soc_component_update_bits(component, AC_SYS_MOD_RST,
++				(0x1<<MOD_RST_DAC), (0x1<<MOD_RST_DAC));
++		snd_soc_component_update_bits(component, AC_DAC_CTL,
++				(0x1<<DAC_CTL_DAC_EN), (0x1<<DAC_CTL_DAC_EN));
++		break;
++	case	SND_SOC_DAPM_POST_PMD:
++		snd_soc_component_update_bits(component, AC_SYS_CLK_CTL,
++				(0x1<<SYS_CLK_DAC), (0x0<<SYS_CLK_DAC));
++		snd_soc_component_update_bits(component, AC_SYS_MOD_RST,
++				(0x1<<MOD_RST_DAC), (0x0<<MOD_RST_DAC));
++		snd_soc_component_update_bits(component, AC_DAC_CTL,
++				(0x1<<DAC_CTL_DAC_EN), (0x0<<DAC_CTL_DAC_EN));
++		break;
++	default:
++		break;
++	}
++	return 0;
++}
++
++/* Enable I2S & ADC clk, then enable the ADC digital part */
++static int acx00_capture_event(struct snd_soc_dapm_widget *w,
++				struct snd_kcontrol *k, int event)
++{
++	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
++
++	switch (event) {
++	case	SND_SOC_DAPM_POST_PMU:
++		snd_soc_component_update_bits(component, AC_SYS_CLK_CTL,
++				(0x1<<SYS_CLK_ADC), (0x1<<SYS_CLK_ADC));
++		snd_soc_component_update_bits(component, AC_SYS_MOD_RST,
++				(0x1<<MOD_RST_ADC), (0x1<<MOD_RST_ADC));
++		snd_soc_component_update_bits(component, AC_ADC_CTL,
++				(0x1<<ADC_EN), (0x1<<ADC_EN));
++		break;
++	case	SND_SOC_DAPM_POST_PMD:
++		snd_soc_component_update_bits(component, AC_SYS_CLK_CTL,
++				(0x1<<SYS_CLK_ADC), (0x0<<SYS_CLK_ADC));
++		snd_soc_component_update_bits(component, AC_SYS_MOD_RST,
++				(0x1<<MOD_RST_ADC), (0x0<<MOD_RST_ADC));
++		snd_soc_component_update_bits(component, AC_ADC_CTL,
++				(0x1<<ADC_EN), (0x0<<ADC_EN));
++		break;
++	default:
++		break;
++	}
++	return 0;
++}
++
++/*
++ * we used for three scene:
++ * 1. No external Spker & DAPM LINEOUT used, we just enable the LINEOUT in the
++ * ALSA codec probe(acx00_codec_probe) and resume, and we shutdown the LINEOUT
++ * in device shutdown or suspend.
++ * 2. No external Spker, but DAPM LINEOUT used, we just using the LINEOUT
++ * enable or disable throught the DAPM control.
++ * 3. External Spker & DAPM LINEOUT used, we just using the LINEOUT and
++ * External Spker control GPIO enable or disable through DAPM control.
++ */
++static unsigned int spk_delay = 100;
++module_param(spk_delay, int, 0644);
++MODULE_PARM_DESC(spk_delay, "ACX00-Codec spk mute delay time");
++
++static void acx00_spk_enable(struct work_struct *work)
++{
++	struct acx00_priv *priv = container_of(work,
++			struct acx00_priv, spk_work.work);
++	gpio_set_value(priv->spk_gpio, 1);
++}
++
++static int acx00_lineout_event(struct snd_soc_dapm_widget *w,
++				struct snd_kcontrol *k, int event)
++{
++	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
++	struct acx00_priv *priv = snd_soc_component_get_drvdata(component);
++
++	switch (event) {
++	case	SND_SOC_DAPM_POST_PMU:
++		if (!priv->enable) {
++			snd_soc_component_update_bits(priv->component, AC_LINEOUT_CTL,
++					(1<<LINEL_SRC_EN), (1<<LINEL_SRC_EN));
++			snd_soc_component_update_bits(priv->component, AC_LINEOUT_CTL,
++					(1<<LINER_SRC_EN), (1<<LINER_SRC_EN));
++			msleep(100);
++			priv->enable = 1;
++		}
++#ifdef ACX00_DAPM_LINEOUT
++		snd_soc_component_update_bits(component, AC_LINEOUT_CTL,
++				(1<<LINEOUT_EN), (1<<LINEOUT_EN));
++		mdelay(50);
++#endif
++		if (priv->spk_gpio_used) {
++			if (spk_delay == 0) {
++				gpio_set_value(priv->spk_gpio, 1);
++				/*
++				* time delay to wait spk pa work fine,
++				* general setting 50ms
++				*/
++				mdelay(50);
++			} else
++				schedule_delayed_work(&priv->spk_work,
++					msecs_to_jiffies(spk_delay));
++		}
++		break;
++	case	SND_SOC_DAPM_PRE_PMD:
++		mdelay(50);
++		if (priv->spk_gpio_used) {
++			gpio_set_value(priv->spk_gpio, 0);
++			msleep(50);
++		}
++#ifdef ACX00_DAPM_LINEOUT
++		snd_soc_component_update_bits(component, AC_LINEOUT_CTL,
++				(1<<LINEOUT_EN), (0<<LINEOUT_EN));
++#endif
++		break;
++	default:
++		break;
++	}
++	return 0;
++}
++
++/* AC_I2S_MIXER_SRC : 0x2114 */
++static const struct snd_kcontrol_new i2sl_mixer_src[] = {
++	SOC_DAPM_SINGLE("I2SDACL Switch", AC_I2S_MIXER_SRC,
++			I2S_MIXERL_SRC_DAC, 1, 0),
++	SOC_DAPM_SINGLE("ADCL Switch", AC_I2S_MIXER_SRC,
++			I2S_MIXERL_SRC_ADC, 1, 0),
++};
++
++static const struct snd_kcontrol_new i2sr_mixer_src[] = {
++	SOC_DAPM_SINGLE("I2SDACR Switch", AC_I2S_MIXER_SRC,
++			I2S_MIXERR_SRC_DAC, 1, 0),
++	SOC_DAPM_SINGLE("ADCR Switch", AC_I2S_MIXER_SRC,
++			I2S_MIXERR_SRC_ADC, 1, 0),
++};
++
++/* AC_DAC_MIXER_SRC : 0x2202 */
++static const struct snd_kcontrol_new dacl_mixer_src[] = {
++	SOC_DAPM_SINGLE("I2SDACL Switch", AC_DAC_MIXER_SRC,
++			DAC_MIXERL_SRC_DAC, 1, 0),
++	SOC_DAPM_SINGLE("ADCL Switch", AC_DAC_MIXER_SRC,
++			DAC_MIXERL_SRC_ADC, 1, 0),
++};
++
++static const struct snd_kcontrol_new dacr_mixer_src[] = {
++	SOC_DAPM_SINGLE("I2SDACR Switch", AC_DAC_MIXER_SRC,
++			DAC_MIXERR_SRC_DAC, 1, 0),
++	SOC_DAPM_SINGLE("ADCR Switch", AC_DAC_MIXER_SRC,
++			DAC_MIXERR_SRC_ADC, 1, 0),
++};
++
++/* AC_OUT_MIXER_SRC : 0x2222 */
++static const struct snd_kcontrol_new left_output_mixer[] = {
++	SOC_DAPM_SINGLE("MIC1 Switch", AC_OUT_MIXER_SRC,
++			OUT_MIXERL_SRC_MIC1, 1, 0),
++	SOC_DAPM_SINGLE("MIC2 Switch", AC_OUT_MIXER_SRC,
++			OUT_MIXERL_SRC_MIC2, 1, 0),
++	SOC_DAPM_SINGLE("PhonePN Switch", AC_OUT_MIXER_SRC,
++			OUT_MIXERL_SRC_PHPN, 1, 0),
++	SOC_DAPM_SINGLE("PhoneN Switch", AC_OUT_MIXER_SRC,
++			OUT_MIXERL_SRC_PHN, 1, 0),
++	SOC_DAPM_SINGLE("LINEINL Switch", AC_OUT_MIXER_SRC,
++			OUT_MIXERL_SRC_LINEL, 1, 0),
++	SOC_DAPM_SINGLE("DACL Switch", AC_OUT_MIXER_SRC,
++			OUT_MIXERL_SRC_DACL, 1, 0),
++	SOC_DAPM_SINGLE("DACR Switch", AC_OUT_MIXER_SRC,
++			OUT_MIXERL_SRC_DACR, 1, 0),
++};
++
++static const struct snd_kcontrol_new right_output_mixer[] = {
++	SOC_DAPM_SINGLE("MIC1 Switch", AC_OUT_MIXER_SRC,
++			OUT_MIXERR_SRC_MIC1, 1, 0),
++	SOC_DAPM_SINGLE("MIC2 Switch", AC_OUT_MIXER_SRC,
++			OUT_MIXERR_SRC_MIC2, 1, 0),
++	SOC_DAPM_SINGLE("PhonePN Switch", AC_OUT_MIXER_SRC,
++			OUT_MIXERR_SRC_PHPN, 1, 0),
++	SOC_DAPM_SINGLE("PhoneP Switch", AC_OUT_MIXER_SRC,
++			OUT_MIXERR_SRC_PHP, 1, 0),
++	SOC_DAPM_SINGLE("LINEINR Switch", AC_OUT_MIXER_SRC,
++			OUT_MIXERR_SRC_LINER, 1, 0),
++	SOC_DAPM_SINGLE("DACR Switch", AC_OUT_MIXER_SRC,
++			OUT_MIXERR_SRC_DACR, 1, 0),
++	SOC_DAPM_SINGLE("DACL Switch", AC_OUT_MIXER_SRC,
++			OUT_MIXERR_SRC_DACL, 1, 0),
++};
++
++/* AC_LINEOUT_CTL : 0x2224 */
++const char * const left_lineout_text[] = {
++	"Left OMixer", "LR OMixer",
++};
++
++static const struct soc_enum left_lineout_enum =
++	SOC_ENUM_SINGLE(AC_LINEOUT_CTL, LINEL_SRC,
++		ARRAY_SIZE(left_lineout_text), left_lineout_text);
++
++static const struct snd_kcontrol_new left_lineout_mux =
++	SOC_DAPM_ENUM("Left LINEOUT Mux", left_lineout_enum);
++
++const char * const right_lineout_text[] = {
++	"Right OMixer", "LR OMixer",
++};
++
++static const struct soc_enum right_lineout_enum =
++	SOC_ENUM_SINGLE(AC_LINEOUT_CTL, LINER_SRC,
++		ARRAY_SIZE(right_lineout_text), right_lineout_text);
++
++static const struct snd_kcontrol_new right_lineout_mux =
++	SOC_DAPM_ENUM("Right LINEOUT Mux", right_lineout_enum);
++
++/* AC_ADC_MIXER_SRC : 0x2322 */
++static const struct snd_kcontrol_new left_input_mixer[] = {
++	SOC_DAPM_SINGLE("MIC1 Switch", AC_ADC_MIXER_SRC,
++			ADC_MIXERL_MIC1, 1, 0),
++	SOC_DAPM_SINGLE("MIC2 Switch", AC_ADC_MIXER_SRC,
++			ADC_MIXERL_MIC2, 1, 0),
++	SOC_DAPM_SINGLE("PhonePN Switch", AC_ADC_MIXER_SRC,
++			ADC_MIXERL_PHPN, 1, 0),
++	SOC_DAPM_SINGLE("PhoneN Switch", AC_ADC_MIXER_SRC,
++			ADC_MIXERL_PHN, 1, 0),
++	SOC_DAPM_SINGLE("LINEINL Switch", AC_ADC_MIXER_SRC,
++			ADC_MIXERL_LINEL, 1, 0),
++	SOC_DAPM_SINGLE("OMixerL Switch", AC_ADC_MIXER_SRC,
++			ADC_MIXERL_MIXL, 1, 0),
++	SOC_DAPM_SINGLE("OMixerR Switch", AC_ADC_MIXER_SRC,
++			ADC_MIXERL_MIXR, 1, 0),
++};
++
++static const struct snd_kcontrol_new right_input_mixer[] = {
++	SOC_DAPM_SINGLE("MIC1 Switch", AC_ADC_MIXER_SRC,
++			ADC_MIXERR_MIC1, 1, 0),
++	SOC_DAPM_SINGLE("MIC2 Switch", AC_ADC_MIXER_SRC,
++			ADC_MIXERR_MIC2, 1, 0),
++	SOC_DAPM_SINGLE("PhonePN Switch", AC_ADC_MIXER_SRC,
++			ADC_MIXERR_PHPN, 1, 0),
++	SOC_DAPM_SINGLE("PhoneP Switch", AC_ADC_MIXER_SRC,
++			ADC_MIXERR_PHP, 1, 0),
++	SOC_DAPM_SINGLE("LINEINR Switch", AC_ADC_MIXER_SRC,
++			ADC_MIXERR_LINER, 1, 0),
++	SOC_DAPM_SINGLE("OMixerR Switch", AC_ADC_MIXER_SRC,
++			ADC_MIXERR_MIXR, 1, 0),
++	SOC_DAPM_SINGLE("OMixerL Switch", AC_ADC_MIXER_SRC,
++			ADC_MIXERR_MIXL, 1, 0),
++};
++
++static const struct snd_soc_dapm_widget acx00_codec_dapm_widgets[] = {
++	SND_SOC_DAPM_AIF_IN_E("DACL", "Playback", 0, AC_DAC_CTL,
++			OUT_MIXER_DACL_EN, 0,
++			acx00_playback_event,
++			SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
++	SND_SOC_DAPM_AIF_IN_E("DACR", "Playback", 0,
++			AC_DAC_CTL, OUT_MIXER_DACR_EN, 0,
++			acx00_playback_event,
++			SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
++
++	SND_SOC_DAPM_AIF_OUT_E("ADCL", "Capture", 0,
++			AC_ADC_MIC_CTL, ADCL_EN, 0,
++			acx00_capture_event,
++			SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
++	SND_SOC_DAPM_AIF_OUT_E("ADCR", "Capture", 0,
++			AC_ADC_MIC_CTL, ADCR_EN, 0,
++			acx00_capture_event,
++			SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
++
++	SND_SOC_DAPM_MIXER("Left Output Mixer", AC_OUT_MIXER_CTL,
++			OUT_MIXER_LMIX_EN, 0,
++			left_output_mixer, ARRAY_SIZE(left_output_mixer)),
++
++	SND_SOC_DAPM_MIXER("Right Output Mixer", AC_OUT_MIXER_CTL,
++			OUT_MIXER_RMIX_EN, 0, right_output_mixer,
++			ARRAY_SIZE(right_output_mixer)),
++
++	SND_SOC_DAPM_MIXER("Left Input Mixer", SND_SOC_NOPM, 0, 0,
++			left_input_mixer, ARRAY_SIZE(left_input_mixer)),
++	SND_SOC_DAPM_MIXER("Right Input Mixer", SND_SOC_NOPM, 0, 0,
++			right_input_mixer, ARRAY_SIZE(right_input_mixer)),
++
++	SND_SOC_DAPM_MIXER("Left DAC Mixer", AC_OUT_MIXER_CTL,
++			OUT_MIXER_DACL_EN, 0, dacl_mixer_src,
++			ARRAY_SIZE(dacl_mixer_src)),
++	SND_SOC_DAPM_MIXER("Right DAC Mixer", AC_OUT_MIXER_CTL,
++			OUT_MIXER_DACR_EN, 0, dacr_mixer_src,
++			ARRAY_SIZE(dacr_mixer_src)),
++
++	SND_SOC_DAPM_MIXER("Left I2S Mixer", SND_SOC_NOPM,
++			0, 0, i2sl_mixer_src, ARRAY_SIZE(i2sl_mixer_src)),
++	SND_SOC_DAPM_MIXER("Right I2S Mixer", SND_SOC_NOPM,
++			0, 0, i2sr_mixer_src, ARRAY_SIZE(i2sr_mixer_src)),
++
++	SND_SOC_DAPM_MUX("Left LINEOUT Mux", SND_SOC_NOPM,
++			0, 0, &left_lineout_mux),
++	SND_SOC_DAPM_MUX("Right LINEOUT Mux", SND_SOC_NOPM,
++			0, 0, &right_lineout_mux),
++
++	SND_SOC_DAPM_PGA("MIC1 PGA", AC_ADC_MIC_CTL,
++			MIC1_GAIN_EN, 0, NULL, 0),
++	SND_SOC_DAPM_PGA("MIC2 PGA", AC_ADC_MIC_CTL,
++			MIC2_GAIN_EN, 0, NULL, 0),
++
++	SND_SOC_DAPM_MICBIAS("MIC Bias", AC_MICBIAS_CTL,
++			MMBIAS_EN, 0),
++
++	/* PHONEIN & PHONEOUT not enable in pin assign */
++	SND_SOC_DAPM_INPUT("PHONEINP"),
++	SND_SOC_DAPM_INPUT("PHONEINN"),
++	SND_SOC_DAPM_INPUT("PHONEINPN"),
++
++	/* endpoint define */
++	SND_SOC_DAPM_LINE("LINEIN", NULL),
++	SND_SOC_DAPM_LINE("LINEOUT", acx00_lineout_event),
++	SND_SOC_DAPM_MIC("MIC1", NULL),
++	SND_SOC_DAPM_MIC("MIC2", NULL),
++};
++
++static const struct snd_soc_dapm_route acx00_codec_dapm_routes[] = {
++	{"Left Output Mixer", "MIC1 Switch", "MIC1 PGA"},
++	{"Left Output Mixer", "MIC2 Switch", "MIC2 PGA"},
++	{"Left Output Mixer", "PhonePN Switch", "PHONEINPN"},
++	{"Left Output Mixer", "PhoneN Switch", "PHONEINN"},
++	{"Left Output Mixer", "LINEINL Switch", "LINEIN"},
++	{"Left Output Mixer", "DACR Switch", "Right DAC Mixer"},
++	{"Left Output Mixer", "DACL Switch", "Left DAC Mixer"},
++
++	{"Right Output Mixer", "MIC1 Switch", "MIC1 PGA"},
++	{"Right Output Mixer", "MIC2 Switch", "MIC2 PGA"},
++	{"Right Output Mixer", "PhonePN Switch", "PHONEINPN"},
++	{"Right Output Mixer", "PhoneP Switch", "PHONEINP"},
++	{"Right Output Mixer", "LINEINR Switch", "LINEIN"},
++	{"Right Output Mixer", "DACR Switch", "Right DAC Mixer"},
++	{"Right Output Mixer", "DACL Switch", "Left DAC Mixer"},
++
++	{"Left LINEOUT Mux", NULL, "Left Output Mixer"},
++	{"Left LINEOUT Mux", "LR OMixer", "Right Output Mixer"},
++	{"Right LINEOUT Mux", NULL, "Right Output Mixer"},
++	{"Right LINEOUT Mux", "LR OMixer", "Left Output Mixer"},
++
++	{"Left Input Mixer", "MIC1 Switch", "MIC1 PGA"},
++	{"Left Input Mixer", "MIC2 Switch", "MIC2 PGA"},
++	{"Left Input Mixer", "PhonePN Switch", "PHONEINPN"},
++	{"Left Input Mixer", "PhoneN Switch", "PHONEINN"},
++	{"Left Input Mixer", "LINEINL Switch", "LINEIN"},
++	{"Left Input Mixer", "OMixerL Switch", "Left Output Mixer"},
++	{"Left Input Mixer", "OMixerR Switch", "Right Output Mixer"},
++
++	{"Right Input Mixer", "MIC1 Switch", "MIC1 PGA"},
++	{"Right Input Mixer", "MIC2 Switch", "MIC2 PGA"},
++	{"Right Input Mixer", "PhonePN Switch", "PHONEINPN"},
++	{"Right Input Mixer", "PhoneP Switch", "PHONEINP"},
++	{"Right Input Mixer", "LINEINR Switch", "LINEIN"},
++	{"Right Input Mixer", "OMixerR Switch", "Right Output Mixer"},
++	{"Right Input Mixer", "OMixerL Switch", "Left Output Mixer"},
++
++	{"Left I2S Mixer", "I2SDACL Switch", "DACL"},
++	{"Left I2S Mixer", "ADCL Switch", "Left Input Mixer"},
++
++	{"Right I2S Mixer", "I2SDACR Switch", "DACR"},
++	{"Right I2S Mixer", "ADCR Switch", "Right Input Mixer"},
++
++	{"Left DAC Mixer", "I2SDACL Switch", "DACL"},
++	{"Left DAC Mixer", "ADCL Switch", "Left Input Mixer"},
++
++	{"Right DAC Mixer", "I2SDACR Switch", "DACR"},
++	{"Right DAC Mixer", "ADCR Switch", "Right Input Mixer"},
++
++	{"ADCL", NULL, "Left I2S Mixer"},
++	{"ADCR", NULL, "Right I2S Mixer"},
++
++	{"LINEOUT", NULL, "Left LINEOUT Mux"},
++	{"LINEOUT", NULL, "Right LINEOUT Mux"},
++
++	{"MIC Bias", NULL, "MIC1"},
++	{"MIC Bias", NULL, "MIC2"},
++	{"MIC1 PGA", NULL, "MIC Bias"},
++	{"MIC2 PGA", NULL, "MIC Bias"},
++};
++
++static void acx00_codec_txctrl_enable(struct snd_soc_component *component,
++					int enable)
++{
++	pr_debug("Enter %s, enable %d\n", __func__, enable);
++	if (enable) {
++		snd_soc_component_update_bits(component, AC_I2S_CTL,
++					(1<<I2S_RX_EN), (1<<I2S_RX_EN));
++	} else {
++		snd_soc_component_update_bits(component, AC_I2S_CTL,
++					(1<<I2S_RX_EN), (0<<I2S_RX_EN));
++	}
++	pr_debug("End %s, enable %d\n", __func__, enable);
++}
++
++static void acx00_codec_rxctrl_enable(struct snd_soc_component *component,
++					int enable)
++{
++	pr_debug("Enter %s, enable %d\n", __func__, enable);
++	if (enable) {
++		snd_soc_component_update_bits(component, AC_I2S_CTL,
++					(1<<I2S_TX_EN), (1<<I2S_TX_EN));
++	} else {
++		snd_soc_component_update_bits(component, AC_I2S_CTL,
++					(1<<I2S_TX_EN), (0<<I2S_TX_EN));
++	}
++	pr_debug("End %s, enable %d\n", __func__, enable);
++}
++
++int acx00_reg_read(struct ac200_dev *acx00, unsigned short reg)
++{
++        unsigned int val;
++        int ret;
++
++        ret = regmap_read(acx00->regmap, reg, &val);
++
++        if (ret < 0)
++                return ret;
++        else
++                return val;
++}
++
++int acx00_reg_write(struct ac200_dev *acx00, unsigned short reg, unsigned short val)
++{
++	return regmap_write(acx00->regmap, reg, val);
++}
++
++static void acx00_codec_init(struct snd_soc_component *component)
++{
++	struct acx00_priv *priv = snd_soc_component_get_drvdata(component);
++
++	acx00_reg_write(priv->acx00, 0x50, 0x82b1);
++	acx00_reg_write(priv->acx00, 0xc, 0xce01);
++
++	/* acx00_codec sysctl init */
++	acx00_reg_write(priv->acx00, 0x0010, 0x03);
++	acx00_reg_write(priv->acx00, 0x0012, 0x01);
++
++	/* The bit3 need to setup to 1 for bias current. */
++	snd_soc_component_update_bits(component, AC_MICBIAS_CTL,
++			(0x1 << ADDA_BIAS_CUR), (0x1 << ADDA_BIAS_CUR));
++
++	/* enable the output & global enable bit */
++	snd_soc_component_update_bits(component, AC_I2S_CTL,
++			(1<<I2S_SDO0_EN), (1<<I2S_SDO0_EN));
++	snd_soc_component_update_bits(component, AC_I2S_CTL, (1<<I2S_GEN), (1<<I2S_GEN));
++
++	/* Default setting slot width as 32 bit for I2S */
++	snd_soc_component_update_bits(component, AC_I2S_FMT0,
++			(7<<I2S_FMT_SLOT_WIDTH), (7<<I2S_FMT_SLOT_WIDTH));
++
++	/* default setting 0xA0A0 for ADC & DAC Volume */
++	snd_soc_component_write(component, AC_I2S_DAC_VOL, ACX00_DEF_VOL);
++	snd_soc_component_write(component, AC_I2S_ADC_VOL, ACX00_DEF_VOL);
++
++	/* Enable HPF for high pass filter */
++	snd_soc_component_update_bits(component, AC_DAC_CTL,
++			(1<<DAC_CTL_HPF_EN), (1<<DAC_CTL_HPF_EN));
++
++	/* LINEOUT ANTI POP & Click noise */
++	snd_soc_component_update_bits(component, AC_LINEOUT_CTL,
++			(0x7<<LINE_ANTI_TIME), (0x3<<LINE_ANTI_TIME));
++	snd_soc_component_update_bits(component, AC_LINEOUT_CTL,
++			(0x3<<LINE_SLOPE_SEL), (0x3<<LINE_SLOPE_SEL));
++
++	/* enable & setting adc convert delay time */
++	snd_soc_component_update_bits(component, AC_ADC_CTL, (0x3<<ADC_DELAY_TIME),
++			(0x3<<ADC_DELAY_TIME));
++	snd_soc_component_update_bits(component, AC_ADC_CTL, (1<<ADC_DELAY_EN),
++			(1<<ADC_DELAY_EN));
++
++	if (priv->spk_gpio_used) {
++		snd_soc_component_update_bits(priv->component, AC_LINEOUT_CTL,
++					(1<<LINEL_SRC_EN), (1<<LINEL_SRC_EN));
++		snd_soc_component_update_bits(priv->component, AC_LINEOUT_CTL,
++					(1<<LINER_SRC_EN), (1<<LINER_SRC_EN));
++		priv->enable = 1;
++	}
++#ifndef ACX00_DAPM_LINEOUT
++	snd_soc_component_update_bits(component, AC_LINEOUT_CTL, (1<<LINEOUT_EN),
++			(1<<LINEOUT_EN));
++#endif
++
++	snd_soc_component_update_bits(component, AC_LINEOUT_CTL, 0x1f, 0x0f);
++	snd_soc_component_write(component, AC_DAC_MIXER_SRC, 0x2200);
++	snd_soc_component_write(component, AC_OUT_MIXER_SRC, 0x0202);
++}
++
++static int acx00_codec_hw_params(struct snd_pcm_substream *substream,
++		struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
++{
++	struct snd_soc_component *component = dai->component;
++	int i;
++
++	switch (params_format(params)) {
++	case SNDRV_PCM_FORMAT_S16_LE:
++		snd_soc_component_update_bits(component, AC_I2S_FMT0,
++			(7<<I2S_FMT_SAMPLE), (3<<I2S_FMT_SAMPLE));
++		break;
++	case SNDRV_PCM_FORMAT_S24_LE:
++		snd_soc_component_update_bits(component, AC_I2S_FMT0,
++			(7<<I2S_FMT_SAMPLE), (5<<I2S_FMT_SAMPLE));
++		break;
++	case SNDRV_PCM_FORMAT_S32_LE:
++		snd_soc_component_update_bits(component, AC_I2S_FMT0,
++			(7<<I2S_FMT_SAMPLE), (7<<I2S_FMT_SAMPLE));
++		break;
++	default:
++		dev_err(component->dev, "unrecognized format support\n");
++		break;
++	}
++	for (i = 0; i < ARRAY_SIZE(sample_rate_conv); i++) {
++		if (sample_rate_conv[i].samplerate == params_rate(params)) {
++			snd_soc_component_update_bits(component, AC_SYS_SR_CTL,
++				(SYS_SR_MASK<<SYS_SR_BIT),
++				(sample_rate_conv[i].rate_bit<<SYS_SR_BIT));
++		}
++	}
++
++	return 0;
++}
++
++static int acx00_codec_dai_set_sysclk(struct snd_soc_dai *codec_dai,
++		int clk_id, unsigned int freq, int dir)
++{
++	return 0;
++}
++
++static int acx00_codec_dai_set_fmt(struct snd_soc_dai *codec_dai,
++		unsigned int fmt)
++{
++	struct acx00_priv *priv = snd_soc_dai_get_drvdata(codec_dai);
++	struct snd_soc_component *component = priv->component;
++
++	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++	/* codec clk & FRM master */
++	case SND_SOC_DAIFMT_CBM_CFM:
++		snd_soc_component_update_bits(component, AC_I2S_CLK,
++				(0x1<<I2S_BCLK_OUT), (0x1<<I2S_BCLK_OUT));
++		snd_soc_component_update_bits(component, AC_I2S_CLK,
++				(0x1<<I2S_LRCK_OUT), (0x1<<I2S_LRCK_OUT));
++		break;
++	/* codec clk & FRM slave */
++	case SND_SOC_DAIFMT_CBS_CFS:
++		snd_soc_component_update_bits(component, AC_I2S_CLK,
++				(0x1<<I2S_BCLK_OUT), 0x0<<I2S_BCLK_OUT);
++		snd_soc_component_update_bits(component, AC_I2S_CLK,
++				(0x1<<I2S_LRCK_OUT), 0x0<<I2S_LRCK_OUT);
++		break;
++	}
++
++	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++	case SND_SOC_DAIFMT_I2S:
++		snd_soc_component_update_bits(component, AC_I2S_CLK,
++				(0x3FF<<I2S_LRCK_PERIOD),
++				(0x1F<<I2S_LRCK_PERIOD));
++		snd_soc_component_update_bits(component, AC_I2S_FMT0,
++				(0x3<<I2S_FMT_MODE), (0x1<<I2S_FMT_MODE));
++		snd_soc_component_update_bits(component, AC_I2S_FMT0,
++				(0x1<<I2S_FMT_TX_OFFSET),
++				(0x1<<I2S_FMT_TX_OFFSET));
++		snd_soc_component_update_bits(component, AC_I2S_FMT0,
++				(0x1<<I2S_FMT_RX_OFFSET),
++				(0x1<<I2S_FMT_RX_OFFSET));
++		break;
++	case SND_SOC_DAIFMT_RIGHT_J:
++		snd_soc_component_update_bits(component, AC_I2S_CLK,
++				(0x3FF<<I2S_LRCK_PERIOD),
++				(0x1F<<I2S_LRCK_PERIOD));
++		snd_soc_component_update_bits(component, AC_I2S_FMT0,
++				(0x3<<I2S_FMT_MODE), (0x2<<I2S_FMT_MODE));
++		snd_soc_component_update_bits(component, AC_I2S_FMT0,
++				(0x1<<I2S_FMT_TX_OFFSET),
++				(0x0<<I2S_FMT_TX_OFFSET));
++		snd_soc_component_update_bits(component, AC_I2S_FMT0,
++				(0x1<<I2S_FMT_TX_OFFSET),
++				(0x0<<I2S_FMT_RX_OFFSET));
++		break;
++	case SND_SOC_DAIFMT_LEFT_J:
++		snd_soc_component_update_bits(component, AC_I2S_CLK,
++				(0x3FF<<I2S_LRCK_PERIOD),
++				(0x1F<<I2S_LRCK_PERIOD));
++		snd_soc_component_update_bits(component, AC_I2S_FMT0,
++				(0x3<<I2S_FMT_MODE), (0x1<<I2S_FMT_MODE));
++		snd_soc_component_update_bits(component, AC_I2S_FMT0,
++				(0x1<<I2S_FMT_TX_OFFSET),
++				(0x0<<I2S_FMT_TX_OFFSET));
++		snd_soc_component_update_bits(component, AC_I2S_FMT0,
++				(0x1<<I2S_FMT_RX_OFFSET),
++				(0x0<<I2S_FMT_RX_OFFSET));
++		break;
++	case SND_SOC_DAIFMT_DSP_A:
++		snd_soc_component_update_bits(component, AC_I2S_CLK,
++				(0x3FF<<I2S_LRCK_PERIOD),
++				(0x3F<<I2S_LRCK_PERIOD));
++		snd_soc_component_update_bits(component, AC_I2S_FMT0,
++				(0x3<<I2S_FMT_MODE), (0x0<<I2S_FMT_MODE));
++		snd_soc_component_update_bits(component, AC_I2S_FMT0,
++				(0x1<<I2S_FMT_TX_OFFSET),
++				(0x1<<I2S_FMT_TX_OFFSET));
++		snd_soc_component_update_bits(component, AC_I2S_FMT0,
++				(0x1<<I2S_FMT_RX_OFFSET),
++				(0x1<<I2S_FMT_RX_OFFSET));
++		break;
++	case SND_SOC_DAIFMT_DSP_B:
++		snd_soc_component_update_bits(component, AC_I2S_CLK,
++				(0x3FF<<I2S_LRCK_PERIOD),
++				(0x3F<<I2S_LRCK_PERIOD));
++		snd_soc_component_update_bits(component, AC_I2S_FMT0,
++				(0x3<<I2S_FMT_MODE), (0x0<<I2S_FMT_MODE));
++		snd_soc_component_update_bits(component, AC_I2S_FMT0,
++				(0x1<<I2S_FMT_TX_OFFSET),
++				(0x0<<I2S_FMT_TX_OFFSET));
++		snd_soc_component_update_bits(component, AC_I2S_FMT0,
++				(0x1<<I2S_FMT_RX_OFFSET),
++				(0x0<<I2S_FMT_RX_OFFSET));
++		break;
++	default:
++		dev_err(component->dev, "format setting failed\n");
++		break;
++	}
++
++	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
++	case SND_SOC_DAIFMT_NB_NF:
++		snd_soc_component_update_bits(component, AC_I2S_FMT1,
++				(0x1<<I2S_FMT_BCLK_POLAR),
++				(0x0<<I2S_FMT_BCLK_POLAR));
++		snd_soc_component_update_bits(component, AC_I2S_FMT1,
++				(0x1<<I2S_FMT_LRCK_POLAR),
++				(0x0<<I2S_FMT_LRCK_POLAR));
++		break;
++	case SND_SOC_DAIFMT_NB_IF:
++		snd_soc_component_update_bits(component, AC_I2S_FMT1,
++				(0x1<<I2S_FMT_BCLK_POLAR),
++				(0x0<<I2S_FMT_BCLK_POLAR));
++		snd_soc_component_update_bits(component, AC_I2S_FMT1,
++				(0x1<<I2S_FMT_LRCK_POLAR),
++				(0x1<<I2S_FMT_LRCK_POLAR));
++		break;
++	case SND_SOC_DAIFMT_IB_NF:
++		snd_soc_component_update_bits(component, AC_I2S_FMT1,
++				(0x1<<I2S_FMT_BCLK_POLAR),
++				(0x1<<I2S_FMT_BCLK_POLAR));
++		snd_soc_component_update_bits(component, AC_I2S_FMT1,
++				(0x1<<I2S_FMT_LRCK_POLAR),
++				(0x0<<I2S_FMT_LRCK_POLAR));
++		break;
++	case SND_SOC_DAIFMT_IB_IF:
++		snd_soc_component_update_bits(component, AC_I2S_FMT1,
++				(0x1<<I2S_FMT_BCLK_POLAR),
++				(0x1<<I2S_FMT_BCLK_POLAR));
++		snd_soc_component_update_bits(component, AC_I2S_FMT1,
++				(0x1<<I2S_FMT_LRCK_POLAR),
++				(0x1<<I2S_FMT_LRCK_POLAR));
++		break;
++	default:
++		dev_err(component->dev, "invert clk setting failed\n");
++		return -EINVAL;
++	}
++	return 0;
++}
++
++static int acx00_codec_dai_set_clkdiv(struct snd_soc_dai *codec_dai,
++		int clk_id, int clk_div)
++{
++	struct acx00_priv *priv = snd_soc_dai_get_drvdata(codec_dai);
++	struct snd_soc_component *component = priv->component;
++	unsigned int bclk_div;
++	/*
++	 * when PCM mode, setting as 64fs, when I2S mode as 32fs,
++	 * then two channel, then just as 64fs
++	 */
++	unsigned int div_ratio = clk_div / 64;
++
++	switch (div_ratio) {
++	case 1:
++		bclk_div = I2S_BCLK_DIV_1;
++		break;
++	case 2:
++		bclk_div = I2S_BCLK_DIV_2;
++		break;
++	case 4:
++		bclk_div = I2S_BCLK_DIV_3;
++		break;
++	case 6:
++		bclk_div = I2S_BCLK_DIV_4;
++		break;
++	case 8:
++		bclk_div = I2S_BCLK_DIV_5;
++		break;
++	case 12:
++		bclk_div = I2S_BCLK_DIV_6;
++		break;
++	case 16:
++		bclk_div = I2S_BCLK_DIV_7;
++		break;
++	case 24:
++		bclk_div = I2S_BCLK_DIV_8;
++		break;
++	case 32:
++		bclk_div = I2S_BCLK_DIV_9;
++		break;
++	case 48:
++		bclk_div = I2S_BCLK_DIV_10;
++		break;
++	case 64:
++		bclk_div = I2S_BCLK_DIV_11;
++		break;
++	case 96:
++		bclk_div = I2S_BCLK_DIV_12;
++		break;
++	case 128:
++		bclk_div = I2S_BCLK_DIV_13;
++		break;
++	case 176:
++		bclk_div = I2S_BCLK_DIV_14;
++		break;
++	case 192:
++		bclk_div = I2S_BCLK_DIV_15;
++		break;
++	default:
++		dev_err(component->dev, "setting blck div failed\n");
++		break;
++	}
++
++	snd_soc_component_update_bits(component, AC_I2S_CLK,
++			(I2S_BCLK_DIV_MASK<<I2S_BLCK_DIV),
++			(bclk_div<<I2S_BLCK_DIV));
++	return 0;
++}
++
++static int acx00_codec_startup(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *codec_dai)
++{
++	return 0;
++}
++
++static bool acx00_loop_en;
++module_param(acx00_loop_en, bool, 0644);
++MODULE_PARM_DESC(acx00_loop_en, "ACX00-Codec audio loopback debug(Y=enable, N=disable)");
++
++static int acx00_codec_trigger(struct snd_pcm_substream *substream,
++		int cmd, struct snd_soc_dai *codec_dai)
++{
++	struct snd_soc_component *component = codec_dai->component;
++	return 0;
++}
++
++static int acx00_codec_prepare(struct snd_pcm_substream *substream,
++		struct snd_soc_dai *codec_dai)
++{
++	struct snd_soc_component *component = codec_dai->component;
++
++	snd_soc_component_update_bits(component, AC_SYS_CLK_CTL,
++			(0x1<<SYS_CLK_I2S), (0x1<<SYS_CLK_I2S));
++	snd_soc_component_update_bits(component, AC_SYS_MOD_RST,
++			(0x1<<MOD_RST_I2S), (0x1<<MOD_RST_I2S));
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++		if (acx00_loop_en)
++			snd_soc_component_update_bits(component, AC_I2S_FMT0,
++				(0x1<<I2S_FMT_LOOP),
++				(0x1<<I2S_FMT_LOOP));
++		else
++			snd_soc_component_update_bits(component, AC_I2S_FMT0,
++				(0x1<<I2S_FMT_LOOP),
++				(0x0<<I2S_FMT_LOOP));
++		acx00_codec_txctrl_enable(component, 1);
++	} else
++		acx00_codec_rxctrl_enable(component, 1);
++	return 0;
++}
++
++static int acx00_codec_digital_mute(struct snd_soc_dai *codec_dai,
++				int mute)
++{
++	struct snd_soc_component *component = codec_dai->component;
++
++	if (mute)
++		snd_soc_component_write(component, AC_I2S_DAC_VOL, 0);
++	else
++		snd_soc_component_write(component, AC_I2S_DAC_VOL, ACX00_DEF_VOL);
++	return 0;
++}
++
++static void acx00_codec_shutdown(struct snd_pcm_substream *substream,
++				struct snd_soc_dai *dai)
++{
++	struct snd_soc_component *component = dai->component;
++
++	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++		acx00_codec_txctrl_enable(component, 0);
++	else
++		acx00_codec_rxctrl_enable(component, 0);
++}
++
++static const struct snd_soc_dai_ops acx00_codec_dai_ops = {
++	.hw_params	= acx00_codec_hw_params,
++	.shutdown	= acx00_codec_shutdown,
++//	.digital_mute	= acx00_codec_digital_mute,
++	.set_sysclk	= acx00_codec_dai_set_sysclk,
++	.set_fmt	= acx00_codec_dai_set_fmt,
++	.set_clkdiv	= acx00_codec_dai_set_clkdiv,
++	.startup	= acx00_codec_startup,
++	.trigger	= acx00_codec_trigger,
++	.prepare	= acx00_codec_prepare,
++};
++
++static struct snd_soc_dai_driver acx00_codec_dai[] = {
++	{
++		.name = "acx00-dai",
++		.playback = {
++			.stream_name = "Playback",
++			.channels_min = 1,
++			.channels_max = 2,
++			.rates = SNDRV_PCM_RATE_8000_192000
++				| SNDRV_PCM_RATE_KNOT,
++			.formats = SNDRV_PCM_FMTBIT_S16_LE
++				| SNDRV_PCM_FMTBIT_S24_LE
++				| SNDRV_PCM_FMTBIT_S32_LE,
++		},
++
++		.capture = {
++			.stream_name = "Capture",
++			.channels_min = 1,
++			.channels_max = 2,
++			.rates = SNDRV_PCM_RATE_8000_192000
++				| SNDRV_PCM_RATE_KNOT,
++			.formats = SNDRV_PCM_FMTBIT_S16_LE
++				| SNDRV_PCM_FMTBIT_S24_LE
++				| SNDRV_PCM_FMTBIT_S32_LE,
++		},
++
++		.ops = &acx00_codec_dai_ops,
++	},
++};
++
++static void acx00_codec_resume_work(struct work_struct *work)
++{
++	struct acx00_priv *priv = container_of(work,
++			struct acx00_priv, resume_work.work);
++
++	acx00_codec_init(priv->component);
++}
++
++static int acx00_codec_probe(struct snd_soc_component *component)
++{
++	struct acx00_priv *priv = snd_soc_component_get_drvdata(component);
++	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
++	int ret = 0;
++
++	mutex_init(&priv->mutex);
++
++	priv->component = component;
++#if 0
++	/* Add virtual switch */
++	ret = snd_soc_add_component_controls(component, acx00_codec_controls,
++					ARRAY_SIZE(acx00_codec_controls));
++	if (ret) {
++		pr_err("[audio-codec] Failed to register audio mode control, will continue without it.\n");
++	}
++	snd_soc_dapm_new_controls(dapm, acx00_codec_dapm_widgets, ARRAY_SIZE(acx00_codec_dapm_widgets));
++	snd_soc_dapm_add_routes(dapm, acx00_codec_dapm_routes, ARRAY_SIZE(acx00_codec_dapm_routes));
++#endif
++	/* using late_initcall to wait 120ms acx00-core to make chip reset */
++	acx00_codec_init(component);
++	INIT_DELAYED_WORK(&priv->spk_work, acx00_spk_enable);
++	INIT_DELAYED_WORK(&priv->resume_work, acx00_codec_resume_work);
++	return 0;
++}
++
++static void acx00_codec_remove(struct snd_soc_component *component)
++{
++	struct acx00_priv *priv = snd_soc_component_get_drvdata(component);
++
++	cancel_delayed_work_sync(&priv->spk_work);
++	cancel_delayed_work_sync(&priv->resume_work);
++}
++
++static unsigned int acx00_codec_read(struct snd_soc_component *component,
++					unsigned int reg)
++{
++	unsigned int data;
++	struct acx00_priv *priv = snd_soc_component_get_drvdata(component);
++
++	/* Device I/O API */
++	data = acx00_reg_read(priv->acx00, reg);
++	return data;
++}
++
++static int acx00_codec_write(struct snd_soc_component *component,
++			unsigned int reg, unsigned int value)
++{
++	struct acx00_priv *priv = snd_soc_component_get_drvdata(component);
++
++	return acx00_reg_write(priv->acx00, reg, value);
++}
++
++static int sunxi_gpio_iodisable(u32 gpio)
++{
++	char pin_name[8];
++	u32 config, ret;
++#if 0
++	sunxi_gpio_to_name(gpio, pin_name);
++	config = 7 << 16;
++	ret = pin_config_set(SUNXI_PINCTRL, pin_name, config);
++#endif
++	return ret;
++}
++
++static int acx00_codec_suspend(struct snd_soc_component *component)
++{
++	struct acx00_priv *priv = snd_soc_component_get_drvdata(component);
++
++	pr_debug("Enter %s\n", __func__);
++
++	clk_disable_unprepare(priv->clk);
++
++	/* PA_CTRL first setting low state, then make it iodisabled */
++	if (priv->spk_gpio_used) {
++		sunxi_gpio_iodisable(priv->spk_gpio);
++		msleep(30);
++	}
++
++	/*
++	 * when codec suspend, then the register reset, if auto reset produce
++	 * Pop & Click noise, then we should cut down the LINEOUT in this town.
++	 */
++	if (priv->enable) {
++		snd_soc_component_update_bits(component, AC_LINEOUT_CTL,
++				(1<<LINEOUT_EN), (0<<LINEOUT_EN));
++		snd_soc_component_update_bits(priv->component, AC_LINEOUT_CTL,
++				(1<<LINEL_SRC_EN), (0<<LINEL_SRC_EN));
++		snd_soc_component_update_bits(priv->component, AC_LINEOUT_CTL,
++				(1<<LINER_SRC_EN), (0<<LINER_SRC_EN));
++		priv->enable = 0;
++	}
++
++	pr_debug("Exit %s\n", __func__);
++
++	return 0;
++}
++
++static int acx00_codec_resume(struct snd_soc_component *component)
++{
++	struct acx00_priv *priv = snd_soc_component_get_drvdata(component);
++
++	pr_debug("Enter %s\n", __func__);
++
++	if (clk_prepare_enable(priv->clk)) {
++		dev_err(component->dev, "codec resume clk failed\n");
++		return -EBUSY;
++	}
++
++	schedule_delayed_work(&priv->resume_work, msecs_to_jiffies(300));
++
++	if (priv->spk_gpio_used) {
++		gpio_direction_output(priv->spk_gpio, 1);
++		gpio_set_value(priv->spk_gpio, 0);
++	}
++
++	pr_debug("Exit %s\n", __func__);
++
++	return 0;
++}
++
++
++static int acx00_codec_set_bias_level(struct snd_soc_component *component,
++		enum snd_soc_bias_level level)
++{
++	component->dapm.bias_level = level;
++	return 0;
++}
++
++struct label {
++	const char *name;
++	int value;
++};
++
++#define LABEL(constant) { #constant, constant }
++#define LABEL_END { NULL, -1 }
++
++static struct label reg_labels[] = {
++	LABEL(AC_SYS_CLK_CTL),
++	LABEL(AC_SYS_MOD_RST),
++	LABEL(AC_SYS_SR_CTL),
++	LABEL(AC_I2S_CTL),
++	LABEL(AC_I2S_CLK),
++	LABEL(AC_I2S_FMT0),
++	LABEL(AC_I2S_FMT1),
++	LABEL(AC_I2S_MIXER_SRC),
++	LABEL(AC_I2S_MIXER_GAIN),
++	LABEL(AC_I2S_DAC_VOL),
++	LABEL(AC_I2S_ADC_VOL),
++	LABEL(AC_DAC_CTL),
++	LABEL(AC_DAC_MIXER_SRC),
++	LABEL(AC_DAC_MIXER_GAIN),
++	LABEL(AC_OUT_MIXER_CTL),
++	LABEL(AC_OUT_MIXER_SRC),
++	LABEL(AC_LINEOUT_CTL),
++	LABEL(AC_ADC_CTL),
++	LABEL(AC_MICBIAS_CTL),
++	LABEL(AC_ADC_MIC_CTL),
++	LABEL(AC_ADC_MIXER_SRC),
++	LABEL(AC_BIAS_CTL),
++	LABEL(AC_ANALOG_PROF_CTL),
++	LABEL_END,
++};
++
++static ssize_t show_audio_reg(struct device *dev,
++			struct device_attribute *attr, char *buf)
++{
++	struct acx00_priv *priv = dev_get_drvdata(dev);
++	int count = 0, i = 0;
++	unsigned int reg_val;
++
++	count += sprintf(buf, "dump audio reg:\n");
++
++	while (reg_labels[i].name != NULL) {
++		reg_val = acx00_reg_read(priv->acx00, reg_labels[i].value);
++		count += sprintf(buf + count, "%s 0x%x: 0x%x\n",
++		reg_labels[i].name, (reg_labels[i].value), reg_val);
++		i++;
++	}
++
++	return count;
++}
++
++/*
++ * param 1: 0 read;1 write
++ * param 2: 1 digital reg; 2 analog reg
++ * param 3: reg value;
++ * param 4: write value;
++ * read:
++ * echo 0,1,0x00> audio_reg
++ * echo 0,2,0x00> audio_reg
++ * write:
++ * echo 1,1,0x00,0xa > audio_reg
++ * echo 1,2,0x00,0xff > audio_reg
++*/
++static ssize_t store_audio_reg(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t count)
++{
++	int ret;
++	int rw_flag;
++	unsigned int input_reg_val = 0;
++	int input_reg_group = 0;
++	unsigned int input_reg_offset = 0;
++	struct acx00_priv *priv = dev_get_drvdata(dev);
++
++	ret = sscanf(buf, "%d,%d,0x%x,0x%x", &rw_flag, &input_reg_group,
++			&input_reg_offset, &input_reg_val);
++	dev_info(dev, "ret:%d, reg_group:%d, reg_offset:%d, reg_val:0x%x\n",
++			ret, input_reg_group, input_reg_offset, input_reg_val);
++
++	if (input_reg_group != 1) {
++		pr_err("not exist reg group\n");
++		ret = count;
++		goto out;
++	}
++	if (!(rw_flag == 1 || rw_flag == 0)) {
++		pr_err("not rw_flag\n");
++		ret = count;
++		goto out;
++	}
++
++	if (rw_flag) {
++		acx00_reg_write(priv->acx00, input_reg_offset, input_reg_val);
++	} else {
++		input_reg_val = acx00_reg_read(priv->acx00, input_reg_offset);
++		dev_info(dev, "\n\n Reg[0x%x] : 0x%04x\n\n",
++				input_reg_offset, input_reg_val);
++	}
++	ret = count;
++
++out:
++	return ret;
++}
++
++static DEVICE_ATTR(audio_reg, 0644, show_audio_reg, store_audio_reg);
++
++static struct attribute *audio_debug_attrs[] = {
++	&dev_attr_audio_reg.attr,
++	NULL,
++};
++
++static struct attribute_group audio_debug_attr_group = {
++	.name   = "audio_reg_debug",
++	.attrs  = audio_debug_attrs,
++};
++
++static struct snd_soc_component_driver soc_codec_driver_acx00 = {
++	.probe			= acx00_codec_probe,
++	.remove			= acx00_codec_remove,
++	.suspend		= acx00_codec_suspend,
++	.resume			= acx00_codec_resume,
++	.read			= acx00_codec_read,
++	.write			= acx00_codec_write,
++//	.ignore_pmdown_time	= 1,
++	.set_bias_level		= acx00_codec_set_bias_level,
++	.controls		= acx00_codec_controls,
++	.num_controls		= ARRAY_SIZE(acx00_codec_controls),
++	.dapm_widgets		= acx00_codec_dapm_widgets,
++	.num_dapm_widgets	= ARRAY_SIZE(acx00_codec_dapm_widgets),
++	.dapm_routes		= acx00_codec_dapm_routes,
++	.num_dapm_routes	= ARRAY_SIZE(acx00_codec_dapm_routes),
++};
++
++/* through acx00 is part of mfd devices, after the mfd */
++static int acx00_codec_dev_probe(struct platform_device *pdev)
++{
++	struct acx00_priv *priv;
++	int ret;
++	struct device_node *np = of_find_compatible_node(NULL, NULL, "allwinner,ac200_codec");
++
++	priv = devm_kzalloc(&pdev->dev, sizeof(struct acx00_priv), GFP_KERNEL);
++	if (!priv) {
++		dev_err(&pdev->dev, "acx00 codec priv mem alloc failed\n");
++		return -ENOMEM;
++	}
++
++	platform_set_drvdata(pdev, priv);
++	priv->acx00 = dev_get_drvdata(pdev->dev.parent);
++
++	if (np) {
++		ret = of_get_named_gpio(np, "gpio-spk", 0);
++		if (ret >= 0) {
++			priv->spk_gpio_used = 1;
++			priv->spk_gpio = ret;
++			if (!gpio_is_valid(priv->spk_gpio)) {
++				dev_err(&pdev->dev, "gpio-spk is valid\n");
++				ret = -EINVAL;
++				goto err_devm_kfree;
++			} else {
++				ret = devm_gpio_request(&pdev->dev,
++				priv->spk_gpio, "SPK");
++				if (ret) {
++					dev_err(&pdev->dev,
++						"failed request gpio-spk\n");
++					ret = -EBUSY;
++					goto err_devm_kfree;
++				} else {
++					gpio_direction_output(priv->spk_gpio,
++								1);
++					gpio_set_value(priv->spk_gpio, 0);
++				}
++			}
++		} else {
++			priv->spk_gpio_used = 0;
++		}
++
++		ret = of_get_named_gpio(np, "gpio-switch", 0);
++		if (ret >= 0) {
++			priv->switch_gpio = ret;
++			if (!gpio_is_valid(priv->switch_gpio)) {
++				dev_err(&pdev->dev, "gpio-switch is valid\n");
++				ret = -EINVAL;
++				goto err_devm_kfree;
++			} else {
++				ret = devm_gpio_request(&pdev->dev, priv->switch_gpio, "SWITCH");
++				if (ret) {
++					dev_err(&pdev->dev,
++						"failed request gpio-switch\n");
++					ret = -EBUSY;
++					goto err_devm_kfree;
++				} else {
++					gpio_direction_output(priv->switch_gpio, 1);
++					gpio_set_value(priv->switch_gpio, 1);
++				}
++			}
++		} 
++	}
++
++	ret = snd_soc_register_component(&pdev->dev, &soc_codec_driver_acx00,
++			acx00_codec_dai, ARRAY_SIZE(acx00_codec_dai));
++
++	if (ret < 0)
++		dev_err(&pdev->dev, "Failed register acx00: %d\n", ret);
++
++	ret  = sysfs_create_group(&pdev->dev.kobj, &audio_debug_attr_group);
++	if (ret)
++		dev_warn(&pdev->dev, "failed to create attr group\n");
++
++	return 0;
++
++err_devm_kfree:
++	devm_kfree(&pdev->dev, priv);
++	return ret;
++}
++
++/* Mark this space to clear the LINEOUT & gpio */
++static void acx00_codec_dev_shutdown(struct platform_device *pdev)
++{
++	struct acx00_priv *priv = platform_get_drvdata(pdev);
++
++	if (priv->spk_gpio_used)
++		gpio_set_value(priv->spk_gpio, 0);
++}
++
++static int acx00_codec_dev_remove(struct platform_device *pdev)
++{
++	struct acx00_priv *priv = platform_get_drvdata(pdev);
++
++#ifndef ACX00_DAPM_LINEOUT
++	/*
++	snd_soc_component_update_bits(priv->component, AC_LINEOUT_CTL,
++			(1<<LINEOUT_EN), (0<<LINEOUT_EN));
++	*/
++#endif
++	snd_soc_unregister_component(&pdev->dev);
++	clk_disable_unprepare(priv->clk);
++	devm_kfree(&pdev->dev, priv);
++	return 0;
++}
++
++static const struct of_device_id acx00_codec_match[] = {
++	{ .compatible = "x-powers,ac200-codec" },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, acx00_codec_match);
++
++static struct platform_driver acx00_codec_driver = {
++	.driver = {
++		.name = "acx00-codec",
++		.of_match_table = acx00_codec_match,
++	},
++	.probe = acx00_codec_dev_probe,
++	.remove = acx00_codec_dev_remove,
++	.shutdown = acx00_codec_dev_shutdown,
++};
++
++static int __init acx00_codec_driver_init(void)
++{
++	return platform_driver_register(&acx00_codec_driver);
++}
++
++static void __exit acx00_codec_driver_exit(void)
++{
++	platform_driver_unregister(&acx00_codec_driver);
++}
++late_initcall(acx00_codec_driver_init);
++module_exit(acx00_codec_driver_exit);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("SUNXI ASoC ACX00 Codec Driver");
++MODULE_AUTHOR("wolfgang huang");
++MODULE_ALIAS("platform:acx00-codec");
+diff --git a/sound/soc/codecs/acx00.h b/sound/soc/codecs/acx00.h
+new file mode 100644
+index 000000000..5137cf365
+--- /dev/null
++++ b/sound/soc/codecs/acx00.h
+@@ -0,0 +1,356 @@
++/*
++ * sound\soc\codecs\acx00.h
++ * (C) Copyright 2012-2016
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Wolfgang Huang <huangjinhui@allwinnertech.com>
++ *
++ * some simple description for this code
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ */
++
++#ifndef __ACX00_H_
++#define __ACX00_H_
++
++/* ACX00 register offset list */
++#define AC_SYS_CLK_CTL		0x2000
++#define AC_SYS_MOD_RST		0x2002
++#define AC_SYS_SR_CTL		0x2004
++/* Left blank */
++#define AC_I2S_CTL		0x2100
++#define AC_I2S_CLK		0x2102
++#define AC_I2S_FMT0		0x2104
++/* Left blank */
++#define AC_I2S_FMT1		0x2108
++/* Left blank */
++#define AC_I2S_MIXER_SRC	0x2114
++#define AC_I2S_MIXER_GAIN	0x2116
++#define AC_I2S_DAC_VOL		0x2118
++#define AC_I2S_ADC_VOL		0x211A
++/* Left blank */
++#define AC_DAC_CTL		0x2200
++#define AC_DAC_MIXER_SRC	0x2202
++#define AC_DAC_MIXER_GAIN	0x2204
++/* Left blank */
++#define AC_OUT_MIXER_CTL	0x2220
++#define AC_OUT_MIXER_SRC	0x2222
++#define AC_LINEOUT_CTL		0x2224
++/* Left blank */
++#define AC_ADC_CTL		0x2300
++/* Left blank */
++#define AC_MICBIAS_CTL		0x2310
++/* Left blank */
++#define AC_ADC_MIC_CTL		0x2320
++#define AC_ADC_MIXER_SRC	0x2322
++/* Left blank */
++#define AC_BIAS_CTL		0x232A
++#define AC_ANALOG_PROF_CTL	0x232C
++/* Left blank */
++#define AC_ADC_DAPL_CTRL	0x2500
++#define AC_ADC_DAPR_CTRL	0x2502
++#define AC_ADC_DAPLSTA		0x2504
++#define AC_ADC_DAPRSTA		0x2506
++#define AC_ADC_DAP_LTL		0x2508
++#define AC_ADC_DAP_RTL		0x250A
++#define AC_ADC_DAP_LHAC		0x250C
++#define AC_ADC_DAP_LLAC		0x250E
++#define AC_ADC_DAP_RHAC		0x2510
++#define AC_ADC_DAP_RLAC		0x2512
++#define AC_ADC_DAP_LDT		0x2514
++#define AC_ADC_DAP_LAT		0x2516
++#define AC_ADC_DAP_RDT		0x2518
++#define AC_ADC_DAP_RAT		0x251A
++#define AC_ADC_DAP_NTH		0x251C
++#define AC_ADC_DAP_LHNAC	0x251E
++#define AC_ADC_DAP_LLNAC	0x2520
++#define AC_ADC_DAP_RHNAC	0x2522
++#define AC_ADC_DAP_RLNAC	0x2524
++#define AC_ADC_DAP_HHPFC	0x2526
++#define AC_ADC_DAP_LHPFC	0x2528
++#define AC_ADC_DAP_OPT		0x252A
++/* Left blank */
++#define AC_AGC_SEL		0x2480
++/* Left blank */
++#define AC_ADC_DAPL_CTRL	0x2500
++#define AC_ADC_DAPR_CTRL	0x2502
++#define AC_ADC_DAPLSTA		0x2504
++#define AC_ADC_DAPRSTA		0x2506
++#define AC_ADC_DAP_LTL		0x2508
++#define AC_ADC_DAP_RTL		0x250A
++#define AC_ADC_DAP_LHAC		0x250C
++#define AC_ADC_DAP_LLAC		0x250E
++#define AC_ADC_DAP_RHAC		0x2510
++#define AC_ADC_DAP_RLAC		0x2512
++#define AC_ADC_DAP_LDT		0x2514
++#define AC_ADC_DAP_LAT		0x2516
++#define AC_ADC_DAP_RDT		0x2518
++#define AC_ADC_DAP_RAT		0x251A
++#define AC_ADC_DAP_NTH		0x251C
++#define AC_ADC_DAP_LHNAC	0x251E
++#define AC_ADC_DAP_LLNAC	0x2520
++#define AC_ADC_DAP_RHNAC	0x2522
++#define AC_ADC_DAP_RLNAC	0x2524
++#define AC_ADC_DAP_HHPFC	0x2526
++#define AC_ADC_DAP_LHPFC	0x2528
++#define AC_ADC_DAP_OPT		0x252A
++/* Left blank */
++#define AC_DRC_SEL		0x2f80
++/* Left blank */
++#define AC_DRC_CHAN_CTRL	0x3000
++#define AC_DRC_HHPFC		0x3002
++#define AC_DRC_LHPFC		0x3004
++#define AC_DRC_CTRL		0x3006
++#define AC_DRC_LPFHAT		0x3008
++#define AC_DRC_LPFLAT		0x300A
++#define AC_DRC_RPFHAT		0x300C
++#define AC_DRC_RPFLAT		0x300E
++#define AC_DRC_LPFHRT		0x3010
++#define AC_DRC_LPFLRT		0x3012
++#define AC_DRC_RPFHRT		0x3014
++#define AC_DRC_RPFLRT		0x3016
++#define AC_DRC_LRMSHAT		0x3018
++#define AC_DRC_LRMSLAT		0x301A
++#define AC_DRC_RRMSHAT		0x301C
++#define AC_DRC_RRMSLAT		0x301E
++#define AC_DRC_HCT		0x3020
++#define AC_DRC_LCT		0x3022
++#define AC_DRC_HKC		0x3024
++#define AC_DRC_LKC		0x3026
++#define AC_DRC_HOPC		0x3028
++#define AC_DRC_LOPC		0x302A
++#define AC_DRC_HLT		0x302C
++#define AC_DRC_LLT		0x302E
++#define AC_DRC_HKI		0x3030
++#define AC_DRC_LKI		0x3032
++#define AC_DRC_HOPL		0x3034
++#define AC_DRC_LOPL		0x3036
++#define AC_DRC_HET		0x3038
++#define AC_DRC_LET		0x303A
++#define AC_DRC_HKE		0x303C
++#define AC_DRC_LKE		0x303E
++#define AC_DRC_HOPE		0x3040
++#define AC_DRC_LOPE		0x3042
++#define AC_DRC_HKN		0x3044
++#define AC_DRC_LKN		0x3046
++#define AC_DRC_SFHAT		0x3048
++#define AC_DRC_SFLAT		0x304A
++#define AC_DRC_SFHRT		0x304C
++#define AC_DRC_SFLRT		0x304E
++#define AC_DRC_MXGHS		0x3050
++#define AC_DRC_MXGLS		0x3052
++#define AC_DRC_MNGHS		0x3054
++#define AC_DRC_MNGLS		0x3056
++#define AC_DRC_EPSHC		0x3058
++#define AC_DRC_EPSLC		0x305A
++#define AC_DRC_OPT		0x305C
++#define AC_DRC_HPFHGAIN		0x305E
++#define AC_DRC_HPFLGAIN		0x3060
++#define AC_DRC_BISTCR		0x3100
++#define AC_DRC_BISTST		0x3102
++
++/* AC_SYS_CLK_CTL : 0x2000 */
++#define SYS_CLK_I2S		15
++#define SYS_CLK_AGC		7
++#define SYS_CLK_DRC		6
++#define SYS_CLK_ADC		3
++#define SYS_CLK_DAC		2
++
++/* AC_SYS_MOD_RST : 0x2002 */
++#define MOD_RST_I2S		15
++#define MOD_RST_AGC		7
++#define MOD_RST_DRC		6
++#define MOD_RST_ADC		3
++#define MOD_RST_DAC		2
++
++/* AC_SYS_SR_CTL : 0x2004 */
++#define SYS_SR_BIT		0
++#define SYS_SR_MASK		0xF
++#define SYS_SR_BIT_0		0	/* 8000 */
++#define SYS_SR_BIT_1		1	/* 11025 */
++#define SYS_SR_BIT_2		2	/* 12000 */
++#define SYS_SR_BIT_3		3	/* 16000 */
++#define SYS_SR_BIT_4		4	/* 22050 */
++#define SYS_SR_BIT_5		5	/* 24000 */
++#define SYS_SR_BIT_6		6	/* 32000 */
++#define SYS_SR_BIT_7		7	/* 44100 */
++#define SYS_SR_BIT_8		8	/* 48000 */
++#define SYS_SR_BIT_9		9	/* 96000 */
++#define SYS_SR_BIT_10		10	/* 192000 */
++
++/* AC_I2S_CTL : 0x2100 */
++#define I2S_SDO0_EN		3
++#define I2S_TX_EN		2
++#define I2S_RX_EN		1
++#define I2S_GEN			0
++
++/* AC_I2S_CLK : 0x2102 */
++#define I2S_BCLK_OUT		15
++#define I2S_LRCK_OUT		14
++#define I2S_BLCK_DIV		10
++#define I2S_LRCK_PERIOD		0
++/* BCLK DIV Define */
++#define I2S_BCLK_DIV_MASK	0xF
++#define I2S_BCLK_DIV_1		1
++#define I2S_BCLK_DIV_2		2
++#define I2S_BCLK_DIV_3		3
++#define I2S_BCLK_DIV_4		4
++#define I2S_BCLK_DIV_5		5
++#define I2S_BCLK_DIV_6		6
++#define I2S_BCLK_DIV_7		7
++#define I2S_BCLK_DIV_8		8
++#define I2S_BCLK_DIV_9		9
++#define I2S_BCLK_DIV_10		10
++#define I2S_BCLK_DIV_11		11
++#define I2S_BCLK_DIV_12		12
++#define I2S_BCLK_DIV_13		13
++#define I2S_BCLK_DIV_14		14
++#define I2S_BCLK_DIV_15		15
++#define I2S_LRCK_PERIOD_MASK	0x3FF
++
++/* AC_I2S_FMT0 : 0x2104 */
++#define I2S_FMT_MODE		14
++#define I2S_FMT_TX_OFFSET	10
++#define I2S_FMT_RX_OFFSET	8
++#define I2S_FMT_SAMPLE		4
++#define I2S_FMT_SLOT_WIDTH	1
++#define I2S_FMT_LOOP		0
++
++/* AC_I2S_FMT1 : 0x2108 */
++#define I2S_FMT_BCLK_POLAR	15
++#define I2S_FMT_LRCK_POLAR	14
++#define I2S_FMT_EDGE_TRANSFER	13
++#define I2S_FMT_RX_MLS		11
++#define I2S_FMT_TX_MLS		10
++#define I2S_FMT_EXTEND		9
++#define I2S_FMT_LRCK_WIDTH	4	/* PCM long/short Frame */
++#define I2S_MFT_RX_PDM		2
++#define I2S_FMT_TX_PDM		0
++
++/* AC_I2S_MIXER_SRC : 0x2114 */
++#define I2S_MIXERL_SRC_DAC	13
++#define I2S_MIXERL_SRC_ADC	12
++#define I2S_MIXERR_SRC_DAC	9
++#define I2S_MIXERR_SRC_ADC	8
++
++/* AC_I2S_MIXER_GAIN : 0x2116 */
++#define I2S_MIXERL_GAIN_DAC	13
++#define I2S_MIXERL_GAIN_ADC	12
++#define I2S_MIXERR_GAIN_DAC	9
++#define I2S_MIXERR_GAIN_ADC	8
++
++
++/* AC_I2S_DAC_VOL : 0x2118 */
++#define I2S_DACL_VOL		8
++#define I2S_DACR_VOL		0
++
++/* AC_I2S_ADC_VOL : 0x211A */
++#define I2S_ADCL_VOL		8
++#define I2S_ADCR_VOL		0
++
++/* AC_DAC_CTL : 0x2200 */
++#define DAC_CTL_DAC_EN		15
++#define DAC_CTL_HPF_EN		14
++#define DAC_CTL_FIR			13
++#define DAC_CTL_MODQU		8
++
++/* AC_DAC_MIXER_SRC : 0x2202 */
++#define DAC_MIXERL_SRC_DAC	13
++#define DAC_MIXERL_SRC_ADC	12
++#define DAC_MIXERR_SRC_DAC	9
++#define DAC_MIXERR_SRC_ADC	8
++
++/* AC_DAC_MIXER_GAIN : 0x2204 */
++#define DAC_MIXERL_GAIN_DAC	13
++#define DAC_MIXERL_GAIN_ADC	12
++#define DAC_MIXERR_GAIN_DAC	9
++#define DAC_MIXERR_GAIN_ADC	8
++
++/* AC_OUT_MIXER_CTL : 0x2220 */
++#define OUT_MIXER_DACR_EN	15
++#define OUT_MIXER_DACL_EN	14
++#define OUT_MIXER_RMIX_EN	13
++#define OUT_MIXER_LMIX_EN	12
++#define OUT_MIXER_LINE_VOL	8
++#define OUT_MIXER_MIC1_VOL	4
++#define OUT_MIXER_MIC2_VOL	0
++
++/* AC_OUT_MIXER_SRC : 0x2222 */
++#define OUT_MIXERR_SRC_MIC1	14
++#define OUT_MIXERR_SRC_MIC2	13
++#define OUT_MIXERR_SRC_PHPN	12
++#define OUT_MIXERR_SRC_PHP	11
++#define OUT_MIXERR_SRC_LINER	10
++#define OUT_MIXERR_SRC_DACR	9
++#define OUT_MIXERR_SRC_DACL	8
++#define OUT_MIXERL_SRC_MIC1	6
++#define OUT_MIXERL_SRC_MIC2	5
++#define OUT_MIXERL_SRC_PHPN	4
++#define OUT_MIXERL_SRC_PHN	3
++#define OUT_MIXERL_SRC_LINEL	2
++#define OUT_MIXERL_SRC_DACL	1
++#define OUT_MIXERL_SRC_DACR	0
++
++/* AC_LINEOUT_CTL : 0x2224 */
++#define LINEOUT_EN		15
++#define LINEL_SRC_EN		14
++#define LINER_SRC_EN		13
++#define LINEL_SRC		12
++#define LINER_SRC		11
++/* ramp just skip */
++#define LINE_SLOPE_SEL		8
++#define LINE_ANTI_TIME		5
++#define LINEOUT_VOL			0
++
++/* AC_ADC_CTL : 0x2300 */
++#define ADC_EN			15
++#define ADC_ENDM		14
++#define ADC_FIR			13
++#define ADC_DELAY_TIME		2
++#define ADC_DELAY_EN		1
++
++/* AC_MICBIAS_CTL : 0x2310 */
++#define MMBIAS_EN		15
++#define MMBIAS_CHOPPER		14
++#define MMBIAS_CHOP_CLK		12
++#define MMBIAS_SEL		8
++#define ADDA_BIAS_CUR		3
++
++/* AC_ADC_MIC_CTL : 0x2320 */
++#define ADCR_EN			15
++#define ADCL_EN			14
++#define ADC_GAIN		8
++#define MIC1_GAIN_EN		7
++#define MIC1_BOOST		4
++#define MIC2_GAIN_EN		3
++#define MIC2_BOOST		0
++
++/* AC_ADC_MIXER_SRC : 0x2322 */
++#define ADC_MIXERR_MIC1		14
++#define ADC_MIXERR_MIC2		13
++#define ADC_MIXERR_PHPN		12
++#define ADC_MIXERR_PHP		11
++#define ADC_MIXERR_LINER	10
++#define ADC_MIXERR_MIXR		9
++#define ADC_MIXERR_MIXL		8
++#define ADC_MIXERL_MIC1		6
++#define ADC_MIXERL_MIC2		5
++#define ADC_MIXERL_PHPN		4
++#define ADC_MIXERL_PHN		3
++#define ADC_MIXERL_LINEL	2
++#define ADC_MIXERL_MIXL		1
++#define ADC_MIXERL_MIXR		0
++
++/* AC_BIAS_CTL : 0x232A */
++
++/* AC_ANALOG_PROF_CTL : 0x232C */
++/* used for current performance measure */
++
++/* AC_DLDO_OSC_CTL : 0x2340 */
++/* AC_ALDO_CTL : 0x2342 */
++/* used for digital & analog LDO test... etc */
++
++#endif
+-- 
+2.25.1
+
diff --git a/0010-allwinner-add-sunxi_get_soc_chipid-and-sunxi_get_ser.patch b/0010-allwinner-add-sunxi_get_soc_chipid-and-sunxi_get_ser.patch
new file mode 100644
index 000000000000..4fc50184b485
--- /dev/null
+++ b/0010-allwinner-add-sunxi_get_soc_chipid-and-sunxi_get_ser.patch
@@ -0,0 +1,59 @@
+From caaa7def76801cbe9937602603f6b471f776e6f6 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Sat, 16 Apr 2022 11:19:05 +0300
+Subject: [PATCH] nvmem: sunxi_sid: add sunxi_get_soc_chipid, sunxi_get_serial
+
+---
+ drivers/nvmem/sunxi_sid.c | 28 ++++++++++++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+
+diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c
+index 37a6abb0e..c81fac63d 100644
+--- a/drivers/nvmem/sunxi_sid.c
++++ b/drivers/nvmem/sunxi_sid.c
+@@ -37,6 +37,25 @@ struct sunxi_sid {
+ 	u32			value_offset;
+ };
+ 
++static unsigned int sunxi_soc_chipid[4];
++static unsigned int sunxi_serial[4];
++
++int sunxi_get_soc_chipid(unsigned char *chipid)
++{
++	memcpy(chipid, sunxi_soc_chipid, 16);
++
++	return 0;
++}
++EXPORT_SYMBOL(sunxi_get_soc_chipid);
++
++int sunxi_get_serial(unsigned       char *serial)
++{
++	memcpy(serial, sunxi_serial, 16);
++
++	return 0;
++}
++EXPORT_SYMBOL(sunxi_get_serial);
++
+ static int sunxi_sid_read(void *context, unsigned int offset,
+ 			  void *val, size_t bytes)
+ {
+@@ -167,6 +186,15 @@ static int sunxi_sid_probe(struct platform_device *pdev)
+ 
+ 	platform_set_drvdata(pdev, nvmem);
+ 
++	nvmem_cfg->reg_read(sid, 0, &sunxi_soc_chipid[0], sizeof(int));
++	nvmem_cfg->reg_read(sid, 4, &sunxi_soc_chipid[1], sizeof(int));
++	nvmem_cfg->reg_read(sid, 8, &sunxi_soc_chipid[2], sizeof(int));
++	nvmem_cfg->reg_read(sid, 12, &sunxi_soc_chipid[3], sizeof(int));
++
++	sunxi_serial[0] = sunxi_soc_chipid[3];
++	sunxi_serial[1] = sunxi_soc_chipid[2];
++	sunxi_serial[2] = (sunxi_soc_chipid[1] >> 16) & 0x0ffff;
++
+ 	return 0;
+ }
+ 
+-- 
+2.34.1
+
+
diff --git a/0010-general-h6-add-dma-i2c-ir-spi-uart.patch b/0010-general-h6-add-dma-i2c-ir-spi-uart.patch
deleted file mode 100644
index 77cb4dabf281..000000000000
--- a/0010-general-h6-add-dma-i2c-ir-spi-uart.patch
+++ /dev/null
@@ -1,107 +0,0 @@
-diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
-index dc785da9c..141fd186b 100644
---- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
-@@ -374,6 +381,17 @@
- 			#dma-cells = <1>;
- 		};
- 
-+		gic: interrupt-controller@3021000 {
-+			compatible = "arm,gic-400";
-+			reg = <0x03021000 0x1000>,
-+			      <0x03022000 0x2000>,
-+			      <0x03024000 0x2000>,
-+			      <0x03026000 0x2000>;
-+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-+			interrupt-controller;
-+			#interrupt-cells = <3>;
-+		};
-+
- 		sid: efuse@3006000 {
- 			compatible = "allwinner,sun50i-h6-sid";
- 			reg = <0x03006000 0x400>;
-@@ -279,6 +305,7 @@
- 			interrupt-controller;
- 			#interrupt-cells = <3>;
- 
-+			/omit-if-no-ref/
- 			ext_rgmii_pins: rgmii-pins {
- 				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
- 				       "PD5", "PD7", "PD8", "PD9", "PD10",
-@@ -309,6 +354,7 @@
- 				bias-pull-up;
- 			};
- 
-+			/omit-if-no-ref/
- 			mmc2_pins: mmc2-pins {
- 				pins = "PC1", "PC4", "PC5", "PC6",
- 				       "PC7", "PC8", "PC9", "PC10",
-@@ -511,17 +540,26 @@
- 				pins = "PG8", "PG9";
- 				function = "uart1";
- 			};
--		};
- 
--		gic: interrupt-controller@3021000 {
--			compatible = "arm,gic-400";
--			reg = <0x03021000 0x1000>,
--			      <0x03022000 0x2000>,
--			      <0x03024000 0x2000>,
--			      <0x03026000 0x2000>;
--			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
--			interrupt-controller;
--			#interrupt-cells = <3>;
-+			uart2_pins: uart2-pins {
-+				pins = "PD19", "PD20";
-+				function = "uart2";
-+			};
-+
-+			uart2_rts_cts_pins: uart2-rts-cts-pins {
-+				pins = "PD21", "PD22";
-+				function = "uart2";
-+			};
-+
-+			uart3_pins: uart3-pins {
-+				pins = "PD23", "PD24";
-+				function = "uart3";
-+			};
-+
-+			uart3_rts_cts_pins: uart3-rts-cts-pins {
-+				pins = "PD25", "PD26";
-+				function = "uart3";
-+			};
- 		};
- 
- 		mmc0: mmc@4020000 {
-@@ -963,6 +1033,19 @@
- 			};
- 		};
- 
-+		r_uart: serial@7080000 {
-+			compatible = "snps,dw-apb-uart";
-+			reg = <0x07080000 0x400>;
-+			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-+			reg-shift = <2>;
-+			reg-io-width = <4>;
-+			clocks = <&r_ccu CLK_R_APB2_UART>;
-+			resets = <&r_ccu RST_R_APB2_UART>;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&r_uart_pins>;
-+			status = "disabled";
-+		};
-+
- 		rtc: rtc@7000000 {
- 			compatible = "allwinner,sun50i-h6-rtc";
- 			reg = <0x07000000 0x400>;
-@@ -1021,6 +1104,11 @@
- 				pins = "PL9";
- 				function = "s_cir_rx";
- 			};
-+
-+			r_uart_pins: r-uart-pins {
-+				pins = "PL2", "PL3";
-+				function = "s_uart";
-+			};
- 		};
- 
- 		r_ir: ir@7040000 {
diff --git a/0012-arm64-h6-gpu-devfreq-enable.patch b/0012-arm64-h6-gpu-devfreq-enable.patch
index 589a8df898e4..ce34f1e07cef 100644
--- a/0012-arm64-h6-gpu-devfreq-enable.patch
+++ b/0012-arm64-h6-gpu-devfreq-enable.patch
@@ -143,6 +143,6 @@ index 199ab77..db61727 100644
 +	val |= (62 << 8) | BIT(1);
 +	writel(val, reg + SUN50I_H6_PLL_GPU_REG);
 +
- 	return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_h6_ccu_desc);
+ 	return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_h6_ccu_desc);
  }
  
diff --git a/0012-fix-h6-emmc.patch b/0012-fix-h6-emmc.patch
new file mode 100644
index 000000000000..e373b02365b5
--- /dev/null
+++ b/0012-fix-h6-emmc.patch
@@ -0,0 +1,38 @@
+From 9010972a9691d468eb68ab85c73c80bb572a5334 Mon Sep 17 00:00:00 2001
+From: Ukhellfire <afaulkner420@gmail.com>
+Date: Thu, 24 Mar 2022 22:21:00 +0000
+Subject: [PATCH] Fix H6 emmc
+
+We have the wrong MMC CAP voltage for the emmc on this board
+---
+ drivers/mmc/host/sunxi-mmc.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
+index dd1c2a610..9a641c7d2 100644
+--- a/drivers/mmc/host/sunxi-mmc.c
++++ b/drivers/mmc/host/sunxi-mmc.c
+@@ -1221,5 +1221,6 @@ static const struct of_device_id sunxi_mmc_of_match[] = {
+ 	{ .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg },
+ 	{ .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg },
++	{ .compatible = "allwinner,sun50i-h6-emmc", .data = &sun50i_a64_emmc_cfg },
+ 	{ .compatible = "allwinner,sun50i-a100-mmc", .data = &sun50i_a100_cfg },
+ 	{ .compatible = "allwinner,sun50i-a100-emmc", .data = &sun50i_a100_emmc_cfg },
+ 	{ /* sentinel */ }
+@@ -1434,7 +1435,7 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
+ 				  MMC_CAP_SDIO_IRQ;
+ 
+ 	/*
+-	 * Some H5 devices do not have signal traces precise enough to
++	 * Some H5 and H6 devices do not have signal traces precise enough to
+ 	 * use HS DDR mode for their eMMC chips.
+ 	 *
+ 	 * We still enable HS DDR modes for all the other controller
+@@ -1443,4 +1444,6 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
+ 	if ((host->cfg->clk_delays || host->use_new_timings) &&
+ 	    !of_device_is_compatible(pdev->dev.of_node,
+-				     "allwinner,sun50i-h5-emmc"))
++				     "allwinner,sun50i-h5-emmc") &&
++	    !of_device_is_compatible(pdev->dev.of_node,
++				     "allwinner,sun50i-h6-emmc"))
+ 		mmc->caps      |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
diff --git a/0013-x-fix-h6-emmc-dts.patch b/0013-x-fix-h6-emmc-dts.patch
new file mode 100644
index 000000000000..91e8cb9dd9c4
--- /dev/null
+++ b/0013-x-fix-h6-emmc-dts.patch
@@ -0,0 +1,23 @@
+From cfafb3f609842d63de13ccaa356b3861ac52c603 Mon Sep 17 00:00:00 2001
+From: Ukhellfire <afaulkner420@gmail.com>
+Date: Fri, 25 Mar 2022 07:10:57 +0000
+Subject: [PATCH] Fix H6 emmc
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 40be5ad6d..3c6e9e875 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -566,8 +566,7 @@
+ 		};
+ 
+ 		mmc2: mmc@4022000 {
+-			compatible = "allwinner,sun50i-h6-emmc",
+-				     "allwinner,sun50i-a64-emmc";
++			compatible = "allwinner,sun50i-h6-emmc";
+ 			reg = <0x04022000 0x1000>;
+ 			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+ 			clock-names = "ahb", "mmc";
diff --git a/0040-wip-H6-deinterlace.patch b/0040-wip-H6-deinterlace.patch
deleted file mode 100644
index b5bb79679e74..000000000000
--- a/0040-wip-H6-deinterlace.patch
+++ /dev/null
@@ -1,1364 +0,0 @@
-From 91c70ea17b58c9205c35cd43a3dd8266bbe035b1 Mon Sep 17 00:00:00 2001
-From: Jernej Skrabec <jernej.skrabec@siol.net>
-Date: Mon, 25 May 2020 19:06:07 +0200
-Subject: [PATCH 40/44] wip: H6 deinterlace
-
-Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
----
- drivers/media/platform/Kconfig                |   13 +
- drivers/media/platform/sunxi/Makefile         |    1 +
- .../media/platform/sunxi/sun50i-di/Makefile   |    2 +
- .../platform/sunxi/sun50i-di/sun50i-di.c      | 1134 +++++++++++++++++
- .../platform/sunxi/sun50i-di/sun50i-di.h      |  172 +++
- 5 files changed, 1322 insertions(+)
- create mode 100644 drivers/media/platform/sunxi/sun50i-di/Makefile
- create mode 100644 drivers/media/platform/sunxi/sun50i-di/sun50i-di.c
- create mode 100644 drivers/media/platform/sunxi/sun50i-di/sun50i-di.h
-
---- a/drivers/media/platform/Kconfig
-+++ b/drivers/media/platform/Kconfig
-@@ -510,6 +510,19 @@ config VIDEO_QCOM_VENUS
- 	  on various Qualcomm SoCs.
- 	  To compile this driver as a module choose m here.
- 
-+config VIDEO_SUN50I_DEINTERLACE
-+	tristate "Allwinner Deinterlace v2 driver"
-+	depends on VIDEO_DEV && VIDEO_V4L2
-+	depends on ARCH_SUNXI || COMPILE_TEST
-+	depends on COMMON_CLK && OF
-+	depends on PM
-+	select VIDEOBUF2_DMA_CONTIG
-+	select V4L2_MEM2MEM_DEV
-+	help
-+	   Support for the Allwinner deinterlace v2 unit found on
-+	   some SoCs, like H6.
-+	   To compile this driver as a module choose m here.
-+
- config VIDEO_SUN8I_DEINTERLACE
- 	tristate "Allwinner Deinterlace driver"
- 	depends on VIDEO_DEV && VIDEO_V4L2
---- a/drivers/media/platform/sunxi/Makefile
-+++ b/drivers/media/platform/sunxi/Makefile
-@@ -3,4 +3,5 @@
- obj-y		+= sun4i-csi/
- obj-y		+= sun6i-csi/
- obj-y		+= sun8i-di/
-+obj-y		+= sun50i-di/
- obj-y		+= sun8i-rotate/
---- /dev/null
-+++ b/drivers/media/platform/sunxi/sun50i-di/Makefile
-@@ -0,0 +1,2 @@
-+# SPDX-License-Identifier: GPL-2.0
-+obj-$(CONFIG_VIDEO_SUN50I_DEINTERLACE) += sun50i-di.o
---- /dev/null
-+++ b/drivers/media/platform/sunxi/sun50i-di/sun50i-di.c
-@@ -0,0 +1,1134 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Allwinner sun50i deinterlacer driver
-+ *
-+ * Copyright (C) 2020 Jernej Skrabec <jernej.skrabec@siol.net>
-+ *
-+ * Based on vim2m driver.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/iopoll.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/pm_runtime.h>
-+#include <linux/reset.h>
-+
-+#include <media/v4l2-device.h>
-+#include <media/v4l2-ioctl.h>
-+#include <media/v4l2-mem2mem.h>
-+
-+#include "sun50i-di.h"
-+
-+#define FLAG_SIZE (DEINTERLACE_MAX_WIDTH * DEINTERLACE_MAX_HEIGHT / 4)
-+
-+static u32 deinterlace_formats[] = {
-+	V4L2_PIX_FMT_NV12,
-+	V4L2_PIX_FMT_NV21,
-+	V4L2_PIX_FMT_YUV420,
-+	V4L2_PIX_FMT_NV16,
-+	V4L2_PIX_FMT_NV61,
-+	V4L2_PIX_FMT_YUV422P
-+};
-+
-+static inline u32 deinterlace_read(struct deinterlace_dev *dev, u32 reg)
-+{
-+	return readl(dev->base + reg);
-+}
-+
-+static inline void deinterlace_write(struct deinterlace_dev *dev,
-+				     u32 reg, u32 value)
-+{
-+	writel(value, dev->base + reg);
-+}
-+
-+static inline void deinterlace_set_bits(struct deinterlace_dev *dev,
-+					u32 reg, u32 bits)
-+{
-+	u32 val = readl(dev->base + reg);
-+
-+	val |= bits;
-+
-+	writel(val, dev->base + reg);
-+}
-+
-+static inline void deinterlace_clr_set_bits(struct deinterlace_dev *dev,
-+					    u32 reg, u32 clr, u32 set)
-+{
-+	u32 val = readl(dev->base + reg);
-+
-+	val &= ~clr;
-+	val |= set;
-+
-+	writel(val, dev->base + reg);
-+}
-+
-+static void deinterlace_device_run(void *priv)
-+{
-+	u32 width, height, reg, msk, pitch[3], offset[2], fmt;
-+	dma_addr_t buf, prev, curr, next, addr[4][3];
-+	struct deinterlace_ctx *ctx = priv;
-+	struct deinterlace_dev *dev = ctx->dev;
-+	struct vb2_v4l2_buffer *src, *dst;
-+	unsigned int val;
-+	bool motion;
-+
-+	src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
-+	dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
-+
-+	v4l2_m2m_buf_copy_metadata(src, dst, true);
-+
-+	fmt = ctx->src_fmt.pixelformat;
-+
-+	deinterlace_write(dev, DEINTERLACE_IN_FLAG_ADDR, ctx->flag1_buf_dma);
-+	deinterlace_write(dev, DEINTERLACE_OUT_FLAG_ADDR, ctx->flag2_buf_dma);
-+	deinterlace_write(dev, DEINTERLACE_FLAG_ADDRH, 0);
-+	deinterlace_write(dev, DEINTERLACE_FLAG_PITCH, 0x200);
-+
-+	width = ctx->src_fmt.width;
-+	height = ctx->src_fmt.height;
-+
-+	reg = DEINTERLACE_SIZE_WIDTH(width);
-+	reg |= DEINTERLACE_SIZE_HEIGHT(height);
-+	deinterlace_write(dev, DEINTERLACE_SIZE, reg);
-+
-+	switch (fmt) {
-+	case V4L2_PIX_FMT_NV12:
-+	case V4L2_PIX_FMT_NV21:
-+		reg = DEINTERLACE_FORMAT_YUV420SP;
-+		break;
-+	case V4L2_PIX_FMT_YUV420:
-+		reg = DEINTERLACE_FORMAT_YUV420P;
-+		break;
-+	case V4L2_PIX_FMT_NV16:
-+	case V4L2_PIX_FMT_NV61:
-+		reg = DEINTERLACE_FORMAT_YUV422SP;
-+		break;
-+	case V4L2_PIX_FMT_YUV422P:
-+		reg = DEINTERLACE_FORMAT_YUV422P;
-+		break;
-+	}
-+	deinterlace_write(dev, DEINTERLACE_FORMAT, reg);
-+
-+	pitch[0] = ctx->src_fmt.bytesperline;
-+	switch (fmt) {
-+	case V4L2_PIX_FMT_YUV420:
-+	case V4L2_PIX_FMT_YUV422P:
-+		pitch[1] = pitch[0] / 2;
-+		pitch[2] = pitch[1];
-+		break;
-+	case V4L2_PIX_FMT_NV12:
-+	case V4L2_PIX_FMT_NV21:
-+	case V4L2_PIX_FMT_NV16:
-+	case V4L2_PIX_FMT_NV61:
-+		pitch[1] = pitch[0];
-+		pitch[2] = 0;
-+		break;
-+	}
-+
-+	deinterlace_write(dev, DEINTERLACE_IN_PITCH0, pitch[0] * 2);
-+	deinterlace_write(dev, DEINTERLACE_IN_PITCH1, pitch[1] * 2);
-+	deinterlace_write(dev, DEINTERLACE_IN_PITCH2, pitch[2] * 2);
-+	deinterlace_write(dev, DEINTERLACE_OUT_PITCH0, pitch[0]);
-+	deinterlace_write(dev, DEINTERLACE_OUT_PITCH1, pitch[1]);
-+	deinterlace_write(dev, DEINTERLACE_OUT_PITCH2, pitch[2]);
-+
-+	offset[0] = pitch[0] * height;
-+	switch (fmt) {
-+	case V4L2_PIX_FMT_YUV420:
-+		offset[1] = offset[0] + offset[0] / 4;
-+		break;
-+	case V4L2_PIX_FMT_YUV422P:
-+		offset[1] = offset[0] + offset[0] / 2;
-+		break;
-+	default:
-+		offset[1] = 0;
-+		break;
-+	}
-+
-+	buf = vb2_dma_contig_plane_dma_addr(&src->vb2_buf, 0);
-+	next = buf;
-+	if (ctx->prev[0])
-+		buf = vb2_dma_contig_plane_dma_addr(&ctx->prev[0]->vb2_buf, 0);
-+	curr = buf;
-+	if (ctx->prev[1])
-+		buf = vb2_dma_contig_plane_dma_addr(&ctx->prev[1]->vb2_buf, 0);
-+	prev = buf;
-+
-+	if (ctx->first_field == 0) {
-+		if (ctx->field == 0) {
-+			addr[0][0] = prev;
-+			addr[0][1] = prev + offset[0];
-+			addr[0][2] = prev + offset[1];
-+			addr[1][0] = prev + pitch[0];
-+			addr[1][1] = prev + offset[0] + pitch[1];
-+			addr[1][2] = prev + offset[1] + pitch[2];
-+			addr[2][0] = curr;
-+			addr[2][1] = curr + offset[0];
-+			addr[2][2] = curr + offset[1];
-+			addr[3][0] = curr + pitch[0];
-+			addr[3][1] = curr + offset[0] + pitch[1];
-+			addr[3][2] = curr + offset[1] + pitch[2];
-+		} else {
-+			addr[0][0] = prev + pitch[0];
-+			addr[0][1] = prev + offset[0] + pitch[1];
-+			addr[0][2] = prev + offset[1] + pitch[2];
-+			addr[1][0] = curr;
-+			addr[1][1] = curr + offset[0];
-+			addr[1][2] = curr + offset[1];
-+			addr[2][0] = curr + pitch[0];
-+			addr[2][1] = curr + offset[0] + pitch[1];
-+			addr[2][2] = curr + offset[1] + pitch[2];
-+			addr[3][0] = next;
-+			addr[3][1] = next + offset[0];
-+			addr[3][2] = next + offset[1];
-+		}
-+	} else {
-+		if (ctx->field == 0) {
-+			addr[0][0] = prev;
-+			addr[0][1] = prev + offset[0];
-+			addr[0][2] = prev + offset[1];
-+			addr[1][0] = curr + pitch[0];
-+			addr[1][1] = curr + offset[0] + pitch[1];
-+			addr[1][2] = curr + offset[1] + pitch[2];
-+			addr[2][0] = curr;
-+			addr[2][1] = curr + offset[0];
-+			addr[2][2] = curr + offset[1];
-+			addr[3][0] = next + pitch[0];
-+			addr[3][1] = next + offset[0] + pitch[1];
-+			addr[3][2] = next + offset[1] + pitch[2];
-+		} else {
-+			addr[0][0] = prev + pitch[0];
-+			addr[0][1] = prev + offset[0] + pitch[1];
-+			addr[0][2] = prev + offset[1] + pitch[2];
-+			addr[1][0] = prev;
-+			addr[1][1] = prev + offset[0];
-+			addr[1][2] = prev + offset[1];
-+			addr[2][0] = curr + pitch[0];
-+			addr[2][1] = curr + offset[0] + pitch[1];
-+			addr[2][2] = curr + offset[1] + pitch[2];
-+			addr[3][0] = curr;
-+			addr[3][1] = curr + offset[0];
-+			addr[3][2] = curr + offset[1];
-+		}
-+	}
-+
-+	deinterlace_write(dev, DEINTERLACE_IN0_ADDR0, addr[0][0]);
-+	deinterlace_write(dev, DEINTERLACE_IN0_ADDR1, addr[0][1]);
-+	deinterlace_write(dev, DEINTERLACE_IN0_ADDR2, addr[0][2]);
-+
-+	deinterlace_write(dev, DEINTERLACE_IN1_ADDR0, addr[1][0]);
-+	deinterlace_write(dev, DEINTERLACE_IN1_ADDR1, addr[1][1]);
-+	deinterlace_write(dev, DEINTERLACE_IN1_ADDR2, addr[1][2]);
-+
-+	deinterlace_write(dev, DEINTERLACE_IN2_ADDR0, addr[2][0]);
-+	deinterlace_write(dev, DEINTERLACE_IN2_ADDR1, addr[2][1]);
-+	deinterlace_write(dev, DEINTERLACE_IN2_ADDR2, addr[2][2]);
-+
-+	deinterlace_write(dev, DEINTERLACE_IN3_ADDR0, addr[3][0]);
-+	deinterlace_write(dev, DEINTERLACE_IN3_ADDR1, addr[3][1]);
-+	deinterlace_write(dev, DEINTERLACE_IN3_ADDR2, addr[3][2]);
-+
-+	buf = vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0);
-+	deinterlace_write(dev, DEINTERLACE_OUT_ADDR0, buf);
-+	deinterlace_write(dev, DEINTERLACE_OUT_ADDR1, buf + offset[0]);
-+	deinterlace_write(dev, DEINTERLACE_OUT_ADDR2, buf + offset[1]);
-+
-+	if (ctx->first_field == 0)
-+		val = 4;
-+	else
-+		val = 5;
-+
-+	reg = DEINTERLACE_INTP_PARAM0_LUMA_CUR_FAC_MODE(val);
-+	reg |= DEINTERLACE_INTP_PARAM0_CHROMA_CUR_FAC_MODE(val);
-+	msk = DEINTERLACE_INTP_PARAM0_LUMA_CUR_FAC_MODE_MSK;
-+	msk |= DEINTERLACE_INTP_PARAM0_CHROMA_CUR_FAC_MODE_MSK;
-+	deinterlace_clr_set_bits(dev, DEINTERLACE_INTP_PARAM0, msk, reg);
-+
-+	reg = DEINTERLACE_POLAR_FIELD(ctx->field);
-+	deinterlace_write(dev, DEINTERLACE_POLAR, reg);
-+
-+	motion = ctx->prev[0] && ctx->prev[1];
-+	reg = DEINTERLACE_MODE_DEINT_LUMA;
-+	if (motion)
-+		reg |= DEINTERLACE_MODE_MOTION_EN;
-+	reg |= DEINTERLACE_MODE_INTP_EN;
-+	reg |= DEINTERLACE_MODE_AUTO_UPD_MODE(ctx->first_field);
-+	reg |= DEINTERLACE_MODE_DEINT_CHROMA;
-+	if (!motion)
-+		reg |= DEINTERLACE_MODE_FIELD_MODE;
-+	deinterlace_write(dev, DEINTERLACE_MODE, reg);
-+
-+	deinterlace_set_bits(dev, DEINTERLACE_INT_CTRL,
-+			     DEINTERLACE_INT_EN);
-+
-+	deinterlace_set_bits(dev, DEINTERLACE_CTRL,
-+			     DEINTERLACE_CTRL_START);
-+}
-+
-+static int deinterlace_job_ready(void *priv)
-+{
-+	struct deinterlace_ctx *ctx = priv;
-+
-+	return v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) >= 1 &&
-+	       v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) >= 2;
-+}
-+
-+static void deinterlace_job_abort(void *priv)
-+{
-+	struct deinterlace_ctx *ctx = priv;
-+
-+	/* Will cancel the transaction in the next interrupt handler */
-+	ctx->aborting = 1;
-+}
-+
-+static irqreturn_t deinterlace_irq(int irq, void *data)
-+{
-+	struct deinterlace_dev *dev = data;
-+	struct vb2_v4l2_buffer *src, *dst;
-+	struct deinterlace_ctx *ctx;
-+	unsigned int val;
-+
-+	ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
-+	if (!ctx) {
-+		v4l2_err(&dev->v4l2_dev,
-+			 "Instance released before the end of transaction\n");
-+		return IRQ_NONE;
-+	}
-+
-+	val = deinterlace_read(dev, DEINTERLACE_STATUS);
-+	if (!(val & DEINTERLACE_STATUS_FINISHED))
-+		return IRQ_NONE;
-+
-+	deinterlace_write(dev, DEINTERLACE_INT_CTRL, 0);
-+	deinterlace_set_bits(dev, DEINTERLACE_STATUS,
-+			     DEINTERLACE_STATUS_FINISHED);
-+	deinterlace_clr_set_bits(dev, DEINTERLACE_CTRL,
-+				 DEINTERLACE_CTRL_START, 0);
-+
-+	dst = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
-+	v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE);
-+
-+	if (ctx->field != ctx->first_field || ctx->aborting) {
-+		ctx->field = ctx->first_field;
-+
-+		src = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
-+		if (ctx->prev[1])
-+			v4l2_m2m_buf_done(ctx->prev[1], VB2_BUF_STATE_DONE);
-+		ctx->prev[1] = ctx->prev[0];
-+		ctx->prev[0] = src;
-+
-+		v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
-+	} else {
-+		ctx->field = !ctx->first_field;
-+		deinterlace_device_run(ctx);
-+	}
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static void deinterlace_init(struct deinterlace_dev *dev)
-+{
-+	u32 reg;
-+
-+	deinterlace_write(dev, DEINTERLACE_OUT_PATH, 0);
-+
-+	reg = DEINTERLACE_MD_PARAM0_MIN_LUMA_TH(4);
-+	reg |= DEINTERLACE_MD_PARAM0_MAX_LUMA_TH(12);
-+	reg |= DEINTERLACE_MD_PARAM0_AVG_LUMA_SHIFT(6);
-+	reg |= DEINTERLACE_MD_PARAM0_TH_SHIFT(1);
-+	deinterlace_write(dev, DEINTERLACE_MD_PARAM0, reg);
-+
-+	reg = DEINTERLACE_MD_PARAM1_MOV_FAC_NONEDGE(2);
-+	deinterlace_write(dev, DEINTERLACE_MD_PARAM1, reg);
-+
-+	reg = DEINTERLACE_MD_PARAM2_CHROMA_SPATIAL_TH(128);
-+	reg |= DEINTERLACE_MD_PARAM2_CHROMA_DIFF_TH(5);
-+	reg |= DEINTERLACE_MD_PARAM2_PIX_STATIC_TH(3);
-+	deinterlace_write(dev, DEINTERLACE_MD_PARAM2, reg);
-+
-+	reg = DEINTERLACE_INTP_PARAM0_ANGLE_LIMIT(20);
-+	reg |= DEINTERLACE_INTP_PARAM0_ANGLE_CONST_TH(5);
-+	reg |= DEINTERLACE_INTP_PARAM0_LUMA_CUR_FAC_MODE(1);
-+	reg |= DEINTERLACE_INTP_PARAM0_CHROMA_CUR_FAC_MODE(1);
-+	deinterlace_write(dev, DEINTERLACE_INTP_PARAM0, reg);
-+
-+	reg = DEINTERLACE_MD_CH_PARAM_BLEND_MODE(1);
-+	reg |= DEINTERLACE_MD_CH_PARAM_FONT_PRO_EN;
-+	reg |= DEINTERLACE_MD_CH_PARAM_FONT_PRO_TH(48);
-+	reg |= DEINTERLACE_MD_CH_PARAM_FONT_PRO_FAC(4);
-+	deinterlace_write(dev, DEINTERLACE_MD_CH_PARAM, reg);
-+
-+	reg = DEINTERLACE_INTP_PARAM1_A(4);
-+	reg |= DEINTERLACE_INTP_PARAM1_EN;
-+	reg |= DEINTERLACE_INTP_PARAM1_C(10);
-+	reg |= DEINTERLACE_INTP_PARAM1_CMAX(64);
-+	reg |= DEINTERLACE_INTP_PARAM1_MAXRAT(2);
-+	deinterlace_write(dev, DEINTERLACE_INTP_PARAM1, reg);
-+
-+	/* only 32-bit addresses are supported, so high bits are always 0 */
-+	deinterlace_write(dev, DEINTERLACE_IN0_ADDRH, 0);
-+	deinterlace_write(dev, DEINTERLACE_IN1_ADDRH, 0);
-+	deinterlace_write(dev, DEINTERLACE_IN2_ADDRH, 0);
-+	deinterlace_write(dev, DEINTERLACE_IN3_ADDRH, 0);
-+	deinterlace_write(dev, DEINTERLACE_OUT_ADDRH, 0);
-+}
-+
-+static inline struct deinterlace_ctx *deinterlace_file2ctx(struct file *file)
-+{
-+	return container_of(file->private_data, struct deinterlace_ctx, fh);
-+}
-+
-+static bool deinterlace_check_format(u32 pixelformat)
-+{
-+	unsigned int i;
-+
-+	for (i = 0; i < ARRAY_SIZE(deinterlace_formats); i++)
-+		if (deinterlace_formats[i] == pixelformat)
-+			return true;
-+
-+	return false;
-+}
-+
-+static void deinterlace_prepare_format(struct v4l2_pix_format *pix_fmt)
-+{
-+	unsigned int bytesperline = pix_fmt->bytesperline;
-+	unsigned int height = pix_fmt->height;
-+	unsigned int width = pix_fmt->width;
-+	unsigned int sizeimage;
-+
-+	width = clamp(width, DEINTERLACE_MIN_WIDTH,
-+		      DEINTERLACE_MAX_WIDTH);
-+	height = clamp(height, DEINTERLACE_MIN_HEIGHT,
-+		       DEINTERLACE_MAX_HEIGHT);
-+
-+	/* try to respect userspace wishes about pitch */
-+	bytesperline = ALIGN(bytesperline, 2);
-+	if (bytesperline < ALIGN(width, 2))
-+		bytesperline = ALIGN(width, 2);
-+
-+	/* luma */
-+	sizeimage = bytesperline * height;
-+	/* chroma */
-+	switch (pix_fmt->pixelformat) {
-+	case V4L2_PIX_FMT_NV12:
-+	case V4L2_PIX_FMT_NV21:
-+	case V4L2_PIX_FMT_YUV420:
-+		sizeimage += bytesperline * height / 2;
-+		break;
-+	case V4L2_PIX_FMT_NV16:
-+	case V4L2_PIX_FMT_NV61:
-+	case V4L2_PIX_FMT_YUV422P:
-+		sizeimage += bytesperline * height;
-+		break;
-+	}
-+
-+	if (pix_fmt->sizeimage < sizeimage)
-+		pix_fmt->sizeimage = sizeimage;
-+
-+	pix_fmt->width = width;
-+	pix_fmt->height = height;
-+	pix_fmt->bytesperline = bytesperline;
-+}
-+
-+static int deinterlace_querycap(struct file *file, void *priv,
-+				struct v4l2_capability *cap)
-+{
-+	strscpy(cap->driver, DEINTERLACE_NAME, sizeof(cap->driver));
-+	strscpy(cap->card, DEINTERLACE_NAME, sizeof(cap->card));
-+	snprintf(cap->bus_info, sizeof(cap->bus_info),
-+		 "platform:%s", DEINTERLACE_NAME);
-+
-+	return 0;
-+}
-+
-+static int deinterlace_enum_fmt(struct file *file, void *priv,
-+				struct v4l2_fmtdesc *f)
-+{
-+	if (f->index < ARRAY_SIZE(deinterlace_formats)) {
-+		f->pixelformat = deinterlace_formats[f->index];
-+
-+		return 0;
-+	}
-+
-+	return -EINVAL;
-+}
-+
-+static int deinterlace_enum_framesizes(struct file *file, void *priv,
-+				       struct v4l2_frmsizeenum *fsize)
-+{
-+	if (fsize->index != 0)
-+		return -EINVAL;
-+
-+	if (!deinterlace_check_format(fsize->pixel_format))
-+		return -EINVAL;
-+
-+	fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
-+	fsize->stepwise.min_width = DEINTERLACE_MIN_WIDTH;
-+	fsize->stepwise.min_height = DEINTERLACE_MIN_HEIGHT;
-+	fsize->stepwise.max_width = DEINTERLACE_MAX_WIDTH;
-+	fsize->stepwise.max_height = DEINTERLACE_MAX_HEIGHT;
-+	fsize->stepwise.step_width = 2;
-+
-+	switch (fsize->pixel_format) {
-+	case V4L2_PIX_FMT_NV12:
-+	case V4L2_PIX_FMT_NV21:
-+	case V4L2_PIX_FMT_YUV420:
-+		fsize->stepwise.step_height = 2;
-+		break;
-+	case V4L2_PIX_FMT_NV16:
-+	case V4L2_PIX_FMT_NV61:
-+	case V4L2_PIX_FMT_YUV422P:
-+		fsize->stepwise.step_height = 1;
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+static int deinterlace_set_cap_format(struct deinterlace_ctx *ctx,
-+				      struct v4l2_pix_format *f)
-+{
-+	if (!deinterlace_check_format(ctx->src_fmt.pixelformat))
-+		return -EINVAL;
-+
-+	f->pixelformat = ctx->src_fmt.pixelformat;
-+	f->field = V4L2_FIELD_NONE;
-+	f->width = ctx->src_fmt.width;
-+	f->height = ctx->src_fmt.height;
-+
-+	deinterlace_prepare_format(f);
-+
-+	return 0;
-+}
-+
-+static int deinterlace_g_fmt_vid_cap(struct file *file, void *priv,
-+				     struct v4l2_format *f)
-+{
-+	struct deinterlace_ctx *ctx = deinterlace_file2ctx(file);
-+
-+	f->fmt.pix = ctx->dst_fmt;
-+
-+	return 0;
-+}
-+
-+static int deinterlace_g_fmt_vid_out(struct file *file, void *priv,
-+				     struct v4l2_format *f)
-+{
-+	struct deinterlace_ctx *ctx = deinterlace_file2ctx(file);
-+
-+	f->fmt.pix = ctx->src_fmt;
-+
-+	return 0;
-+}
-+
-+static int deinterlace_try_fmt_vid_cap(struct file *file, void *priv,
-+				       struct v4l2_format *f)
-+{
-+	struct deinterlace_ctx *ctx = deinterlace_file2ctx(file);
-+
-+	return deinterlace_set_cap_format(ctx, &f->fmt.pix);
-+}
-+
-+static int deinterlace_try_fmt_vid_out(struct file *file, void *priv,
-+				       struct v4l2_format *f)
-+{
-+	if (!deinterlace_check_format(f->fmt.pix.pixelformat))
-+		f->fmt.pix.pixelformat = deinterlace_formats[0];
-+
-+	if (f->fmt.pix.field != V4L2_FIELD_INTERLACED_TB &&
-+	    f->fmt.pix.field != V4L2_FIELD_INTERLACED_BT &&
-+	    f->fmt.pix.field != V4L2_FIELD_INTERLACED)
-+		f->fmt.pix.field = V4L2_FIELD_INTERLACED;
-+
-+	deinterlace_prepare_format(&f->fmt.pix);
-+
-+	return 0;
-+}
-+
-+static int deinterlace_s_fmt_vid_cap(struct file *file, void *priv,
-+				     struct v4l2_format *f)
-+{
-+	struct deinterlace_ctx *ctx = deinterlace_file2ctx(file);
-+	struct vb2_queue *vq;
-+	int ret;
-+
-+	ret = deinterlace_try_fmt_vid_cap(file, priv, f);
-+	if (ret)
-+		return ret;
-+
-+	vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
-+	if (vb2_is_busy(vq))
-+		return -EBUSY;
-+
-+	ctx->dst_fmt = f->fmt.pix;
-+
-+	return 0;
-+}
-+
-+static int deinterlace_s_fmt_vid_out(struct file *file, void *priv,
-+				     struct v4l2_format *f)
-+{
-+	struct deinterlace_ctx *ctx = deinterlace_file2ctx(file);
-+	struct vb2_queue *vq;
-+	int ret;
-+
-+	ret = deinterlace_try_fmt_vid_out(file, priv, f);
-+	if (ret)
-+		return ret;
-+
-+	vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
-+	if (vb2_is_busy(vq))
-+		return -EBUSY;
-+
-+	/*
-+	 * Capture queue has to be also checked, because format and size
-+	 * depends on output format and size.
-+	 */
-+	vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
-+	if (vb2_is_busy(vq))
-+		return -EBUSY;
-+
-+	ctx->src_fmt = f->fmt.pix;
-+
-+	/* Propagate colorspace information to capture. */
-+	ctx->dst_fmt.colorspace = f->fmt.pix.colorspace;
-+	ctx->dst_fmt.xfer_func = f->fmt.pix.xfer_func;
-+	ctx->dst_fmt.ycbcr_enc = f->fmt.pix.ycbcr_enc;
-+	ctx->dst_fmt.quantization = f->fmt.pix.quantization;
-+
-+	return deinterlace_set_cap_format(ctx, &ctx->dst_fmt);
-+}
-+
-+static const struct v4l2_ioctl_ops deinterlace_ioctl_ops = {
-+	.vidioc_querycap		= deinterlace_querycap,
-+
-+	.vidioc_enum_framesizes		= deinterlace_enum_framesizes,
-+
-+	.vidioc_enum_fmt_vid_cap	= deinterlace_enum_fmt,
-+	.vidioc_g_fmt_vid_cap		= deinterlace_g_fmt_vid_cap,
-+	.vidioc_try_fmt_vid_cap		= deinterlace_try_fmt_vid_cap,
-+	.vidioc_s_fmt_vid_cap		= deinterlace_s_fmt_vid_cap,
-+
-+	.vidioc_enum_fmt_vid_out	= deinterlace_enum_fmt,
-+	.vidioc_g_fmt_vid_out		= deinterlace_g_fmt_vid_out,
-+	.vidioc_try_fmt_vid_out		= deinterlace_try_fmt_vid_out,
-+	.vidioc_s_fmt_vid_out		= deinterlace_s_fmt_vid_out,
-+
-+	.vidioc_reqbufs			= v4l2_m2m_ioctl_reqbufs,
-+	.vidioc_querybuf		= v4l2_m2m_ioctl_querybuf,
-+	.vidioc_qbuf			= v4l2_m2m_ioctl_qbuf,
-+	.vidioc_dqbuf			= v4l2_m2m_ioctl_dqbuf,
-+	.vidioc_prepare_buf		= v4l2_m2m_ioctl_prepare_buf,
-+	.vidioc_create_bufs		= v4l2_m2m_ioctl_create_bufs,
-+	.vidioc_expbuf			= v4l2_m2m_ioctl_expbuf,
-+
-+	.vidioc_streamon		= v4l2_m2m_ioctl_streamon,
-+	.vidioc_streamoff		= v4l2_m2m_ioctl_streamoff,
-+};
-+
-+static int deinterlace_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers,
-+				   unsigned int *nplanes, unsigned int sizes[],
-+				   struct device *alloc_devs[])
-+{
-+	struct deinterlace_ctx *ctx = vb2_get_drv_priv(vq);
-+	struct v4l2_pix_format *pix_fmt;
-+
-+	if (V4L2_TYPE_IS_OUTPUT(vq->type))
-+		pix_fmt = &ctx->src_fmt;
-+	else
-+		pix_fmt = &ctx->dst_fmt;
-+
-+	if (*nplanes) {
-+		if (sizes[0] < pix_fmt->sizeimage)
-+			return -EINVAL;
-+	} else {
-+		sizes[0] = pix_fmt->sizeimage;
-+		*nplanes = 1;
-+	}
-+
-+	return 0;
-+}
-+
-+static int deinterlace_buf_prepare(struct vb2_buffer *vb)
-+{
-+	struct vb2_queue *vq = vb->vb2_queue;
-+	struct deinterlace_ctx *ctx = vb2_get_drv_priv(vq);
-+	struct v4l2_pix_format *pix_fmt;
-+
-+	if (V4L2_TYPE_IS_OUTPUT(vq->type))
-+		pix_fmt = &ctx->src_fmt;
-+	else
-+		pix_fmt = &ctx->dst_fmt;
-+
-+	if (vb2_plane_size(vb, 0) < pix_fmt->sizeimage)
-+		return -EINVAL;
-+
-+	vb2_set_plane_payload(vb, 0, pix_fmt->sizeimage);
-+
-+	return 0;
-+}
-+
-+static void deinterlace_buf_queue(struct vb2_buffer *vb)
-+{
-+	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
-+	struct deinterlace_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
-+
-+	v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
-+}
-+
-+static void deinterlace_queue_cleanup(struct vb2_queue *vq, u32 state)
-+{
-+	struct deinterlace_ctx *ctx = vb2_get_drv_priv(vq);
-+	struct vb2_v4l2_buffer *vbuf;
-+
-+	do {
-+		if (V4L2_TYPE_IS_OUTPUT(vq->type))
-+			vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
-+		else
-+			vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
-+
-+		if (vbuf)
-+			v4l2_m2m_buf_done(vbuf, state);
-+	} while (vbuf);
-+
-+	if (V4L2_TYPE_IS_OUTPUT(vq->type)) {
-+		if (ctx->prev[0])
-+			v4l2_m2m_buf_done(ctx->prev[0], state);
-+		if (ctx->prev[1])
-+			v4l2_m2m_buf_done(ctx->prev[1], state);
-+	}
-+}
-+
-+static int deinterlace_start_streaming(struct vb2_queue *vq, unsigned int count)
-+{
-+	struct deinterlace_ctx *ctx = vb2_get_drv_priv(vq);
-+	struct device *dev = ctx->dev->dev;
-+	int ret;
-+
-+	if (V4L2_TYPE_IS_OUTPUT(vq->type)) {
-+		ret = pm_runtime_get_sync(dev);
-+		if (ret < 0) {
-+			dev_err(dev, "Failed to enable module\n");
-+
-+			goto err_runtime_get;
-+		}
-+
-+		ctx->first_field =
-+			ctx->src_fmt.field == V4L2_FIELD_INTERLACED_BT;
-+		ctx->field = ctx->first_field;
-+
-+		ctx->prev[0] = NULL;
-+		ctx->prev[1] = NULL;
-+		ctx->aborting = 0;
-+
-+		ctx->flag1_buf = dma_alloc_coherent(dev, FLAG_SIZE,
-+						    &ctx->flag1_buf_dma,
-+						    GFP_KERNEL);
-+		if (!ctx->flag1_buf) {
-+			ret = -ENOMEM;
-+
-+			goto err_no_mem1;
-+		}
-+
-+		ctx->flag2_buf = dma_alloc_coherent(dev, FLAG_SIZE,
-+						    &ctx->flag2_buf_dma,
-+						    GFP_KERNEL);
-+		if (!ctx->flag2_buf) {
-+			ret = -ENOMEM;
-+
-+			goto err_no_mem2;
-+		}
-+	}
-+
-+	return 0;
-+
-+err_no_mem2:
-+	dma_free_coherent(dev, FLAG_SIZE, ctx->flag1_buf,
-+			  ctx->flag1_buf_dma);
-+err_no_mem1:
-+	pm_runtime_put(dev);
-+err_runtime_get:
-+	deinterlace_queue_cleanup(vq, VB2_BUF_STATE_QUEUED);
-+
-+	return ret;
-+}
-+
-+static void deinterlace_stop_streaming(struct vb2_queue *vq)
-+{
-+	struct deinterlace_ctx *ctx = vb2_get_drv_priv(vq);
-+
-+	if (V4L2_TYPE_IS_OUTPUT(vq->type)) {
-+		struct device *dev = ctx->dev->dev;
-+
-+		dma_free_coherent(dev, FLAG_SIZE, ctx->flag1_buf,
-+				  ctx->flag1_buf_dma);
-+		dma_free_coherent(dev, FLAG_SIZE, ctx->flag2_buf,
-+				  ctx->flag2_buf_dma);
-+
-+		pm_runtime_put(dev);
-+	}
-+
-+	deinterlace_queue_cleanup(vq, VB2_BUF_STATE_ERROR);
-+}
-+
-+static const struct vb2_ops deinterlace_qops = {
-+	.queue_setup		= deinterlace_queue_setup,
-+	.buf_prepare		= deinterlace_buf_prepare,
-+	.buf_queue		= deinterlace_buf_queue,
-+	.start_streaming	= deinterlace_start_streaming,
-+	.stop_streaming		= deinterlace_stop_streaming,
-+	.wait_prepare		= vb2_ops_wait_prepare,
-+	.wait_finish		= vb2_ops_wait_finish,
-+};
-+
-+static int deinterlace_queue_init(void *priv, struct vb2_queue *src_vq,
-+				  struct vb2_queue *dst_vq)
-+{
-+	struct deinterlace_ctx *ctx = priv;
-+	int ret;
-+
-+	src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
-+	src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
-+	src_vq->drv_priv = ctx;
-+	src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
-+	src_vq->min_buffers_needed = 1;
-+	src_vq->ops = &deinterlace_qops;
-+	src_vq->mem_ops = &vb2_dma_contig_memops;
-+	src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
-+	src_vq->lock = &ctx->dev->dev_mutex;
-+	src_vq->dev = ctx->dev->dev;
-+
-+	ret = vb2_queue_init(src_vq);
-+	if (ret)
-+		return ret;
-+
-+	dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
-+	dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
-+	dst_vq->drv_priv = ctx;
-+	dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
-+	dst_vq->min_buffers_needed = 2;
-+	dst_vq->ops = &deinterlace_qops;
-+	dst_vq->mem_ops = &vb2_dma_contig_memops;
-+	dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
-+	dst_vq->lock = &ctx->dev->dev_mutex;
-+	dst_vq->dev = ctx->dev->dev;
-+
-+	ret = vb2_queue_init(dst_vq);
-+	if (ret)
-+		return ret;
-+
-+	return 0;
-+}
-+
-+static int deinterlace_open(struct file *file)
-+{
-+	struct deinterlace_dev *dev = video_drvdata(file);
-+	struct deinterlace_ctx *ctx = NULL;
-+	int ret;
-+
-+	if (mutex_lock_interruptible(&dev->dev_mutex))
-+		return -ERESTARTSYS;
-+
-+	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
-+	if (!ctx) {
-+		mutex_unlock(&dev->dev_mutex);
-+		return -ENOMEM;
-+	}
-+
-+	/* default output format */
-+	ctx->src_fmt.pixelformat = deinterlace_formats[0];
-+	ctx->src_fmt.field = V4L2_FIELD_INTERLACED;
-+	ctx->src_fmt.width = 640;
-+	ctx->src_fmt.height = 480;
-+	deinterlace_prepare_format(&ctx->src_fmt);
-+
-+	/* default capture format */
-+	ctx->dst_fmt.pixelformat = deinterlace_formats[0];
-+	ctx->dst_fmt.field = V4L2_FIELD_NONE;
-+	ctx->dst_fmt.width = 640;
-+	ctx->dst_fmt.height = 480;
-+	deinterlace_prepare_format(&ctx->dst_fmt);
-+
-+	v4l2_fh_init(&ctx->fh, video_devdata(file));
-+	file->private_data = &ctx->fh;
-+	ctx->dev = dev;
-+
-+	ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx,
-+					    &deinterlace_queue_init);
-+	if (IS_ERR(ctx->fh.m2m_ctx)) {
-+		ret = PTR_ERR(ctx->fh.m2m_ctx);
-+		goto err_free;
-+	}
-+
-+	v4l2_fh_add(&ctx->fh);
-+
-+	mutex_unlock(&dev->dev_mutex);
-+
-+	return 0;
-+
-+err_free:
-+	kfree(ctx);
-+	mutex_unlock(&dev->dev_mutex);
-+
-+	return ret;
-+}
-+
-+static int deinterlace_release(struct file *file)
-+{
-+	struct deinterlace_dev *dev = video_drvdata(file);
-+	struct deinterlace_ctx *ctx = container_of(file->private_data,
-+						   struct deinterlace_ctx, fh);
-+
-+	mutex_lock(&dev->dev_mutex);
-+
-+	v4l2_fh_del(&ctx->fh);
-+	v4l2_fh_exit(&ctx->fh);
-+	v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
-+
-+	kfree(ctx);
-+
-+	mutex_unlock(&dev->dev_mutex);
-+
-+	return 0;
-+}
-+
-+static const struct v4l2_file_operations deinterlace_fops = {
-+	.owner		= THIS_MODULE,
-+	.open		= deinterlace_open,
-+	.release	= deinterlace_release,
-+	.poll		= v4l2_m2m_fop_poll,
-+	.unlocked_ioctl	= video_ioctl2,
-+	.mmap		= v4l2_m2m_fop_mmap,
-+};
-+
-+static const struct video_device deinterlace_video_device = {
-+	.name		= DEINTERLACE_NAME,
-+	.vfl_dir	= VFL_DIR_M2M,
-+	.fops		= &deinterlace_fops,
-+	.ioctl_ops	= &deinterlace_ioctl_ops,
-+	.minor		= -1,
-+	.release	= video_device_release_empty,
-+	.device_caps	= V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,
-+};
-+
-+static const struct v4l2_m2m_ops deinterlace_m2m_ops = {
-+	.device_run	= deinterlace_device_run,
-+	.job_ready	= deinterlace_job_ready,
-+	.job_abort	= deinterlace_job_abort,
-+};
-+
-+static int deinterlace_probe(struct platform_device *pdev)
-+{
-+	struct deinterlace_dev *dev;
-+	struct video_device *vfd;
-+	struct resource *res;
-+	int irq, ret;
-+
-+	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
-+	if (!dev)
-+		return -ENOMEM;
-+
-+	dev->vfd = deinterlace_video_device;
-+	dev->dev = &pdev->dev;
-+
-+	irq = platform_get_irq(pdev, 0);
-+	if (irq <= 0)
-+		return irq;
-+
-+	ret = devm_request_irq(dev->dev, irq, deinterlace_irq,
-+			       0, dev_name(dev->dev), dev);
-+	if (ret) {
-+		dev_err(dev->dev, "Failed to request IRQ\n");
-+
-+		return ret;
-+	}
-+
-+	ret = of_dma_configure(dev->dev, dev->dev->of_node, true);
-+	if (ret)
-+		return ret;
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	dev->base = devm_ioremap_resource(&pdev->dev, res);
-+	if (IS_ERR(dev->base))
-+		return PTR_ERR(dev->base);
-+
-+	dev->bus_clk = devm_clk_get(dev->dev, "bus");
-+	if (IS_ERR(dev->bus_clk)) {
-+		dev_err(dev->dev, "Failed to get bus clock\n");
-+
-+		return PTR_ERR(dev->bus_clk);
-+	}
-+
-+	dev->mod_clk = devm_clk_get(dev->dev, "mod");
-+	if (IS_ERR(dev->mod_clk)) {
-+		dev_err(dev->dev, "Failed to get mod clock\n");
-+
-+		return PTR_ERR(dev->mod_clk);
-+	}
-+
-+	dev->ram_clk = devm_clk_get(dev->dev, "ram");
-+	if (IS_ERR(dev->ram_clk)) {
-+		dev_err(dev->dev, "Failed to get ram clock\n");
-+
-+		return PTR_ERR(dev->ram_clk);
-+	}
-+
-+	dev->rstc = devm_reset_control_get(dev->dev, NULL);
-+	if (IS_ERR(dev->rstc)) {
-+		dev_err(dev->dev, "Failed to get reset control\n");
-+
-+		return PTR_ERR(dev->rstc);
-+	}
-+
-+	mutex_init(&dev->dev_mutex);
-+
-+	ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
-+	if (ret) {
-+		dev_err(dev->dev, "Failed to register V4L2 device\n");
-+
-+		return ret;
-+	}
-+
-+	vfd = &dev->vfd;
-+	vfd->lock = &dev->dev_mutex;
-+	vfd->v4l2_dev = &dev->v4l2_dev;
-+
-+	snprintf(vfd->name, sizeof(vfd->name), "%s",
-+		 deinterlace_video_device.name);
-+	video_set_drvdata(vfd, dev);
-+
-+	ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0);
-+	if (ret) {
-+		v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
-+
-+		goto err_v4l2;
-+	}
-+
-+	v4l2_info(&dev->v4l2_dev,
-+		  "Device registered as /dev/video%d\n", vfd->num);
-+
-+	dev->m2m_dev = v4l2_m2m_init(&deinterlace_m2m_ops);
-+	if (IS_ERR(dev->m2m_dev)) {
-+		v4l2_err(&dev->v4l2_dev,
-+			 "Failed to initialize V4L2 M2M device\n");
-+		ret = PTR_ERR(dev->m2m_dev);
-+
-+		goto err_video;
-+	}
-+
-+	platform_set_drvdata(pdev, dev);
-+
-+	pm_runtime_enable(dev->dev);
-+
-+	return 0;
-+
-+err_video:
-+	video_unregister_device(&dev->vfd);
-+err_v4l2:
-+	v4l2_device_unregister(&dev->v4l2_dev);
-+
-+	return ret;
-+}
-+
-+static int deinterlace_remove(struct platform_device *pdev)
-+{
-+	struct deinterlace_dev *dev = platform_get_drvdata(pdev);
-+
-+	v4l2_m2m_release(dev->m2m_dev);
-+	video_unregister_device(&dev->vfd);
-+	v4l2_device_unregister(&dev->v4l2_dev);
-+
-+	pm_runtime_force_suspend(&pdev->dev);
-+
-+	return 0;
-+}
-+
-+static int deinterlace_runtime_resume(struct device *device)
-+{
-+	struct deinterlace_dev *dev = dev_get_drvdata(device);
-+	int ret;
-+
-+	ret = clk_prepare_enable(dev->bus_clk);
-+	if (ret) {
-+		dev_err(dev->dev, "Failed to enable bus clock\n");
-+
-+		return ret;
-+	}
-+
-+	ret = clk_prepare_enable(dev->mod_clk);
-+	if (ret) {
-+		dev_err(dev->dev, "Failed to enable mod clock\n");
-+
-+		goto err_bus_clk;
-+	}
-+
-+	ret = clk_prepare_enable(dev->ram_clk);
-+	if (ret) {
-+		dev_err(dev->dev, "Failed to enable ram clock\n");
-+
-+		goto err_mod_clk;
-+	}
-+
-+	ret = reset_control_deassert(dev->rstc);
-+	if (ret) {
-+		dev_err(dev->dev, "Failed to apply reset\n");
-+
-+		goto err_ram_clk;
-+	}
-+
-+	deinterlace_init(dev);
-+
-+	return 0;
-+
-+err_ram_clk:
-+	clk_disable_unprepare(dev->ram_clk);
-+err_mod_clk:
-+	clk_disable_unprepare(dev->mod_clk);
-+err_bus_clk:
-+	clk_disable_unprepare(dev->bus_clk);
-+
-+	return ret;
-+}
-+
-+static int deinterlace_runtime_suspend(struct device *device)
-+{
-+	struct deinterlace_dev *dev = dev_get_drvdata(device);
-+
-+	reset_control_assert(dev->rstc);
-+
-+	clk_disable_unprepare(dev->ram_clk);
-+	clk_disable_unprepare(dev->mod_clk);
-+	clk_disable_unprepare(dev->bus_clk);
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id deinterlace_dt_match[] = {
-+	{ .compatible = "allwinner,sun50i-h6-deinterlace" },
-+	{ /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, deinterlace_dt_match);
-+
-+static const struct dev_pm_ops deinterlace_pm_ops = {
-+	.runtime_resume		= deinterlace_runtime_resume,
-+	.runtime_suspend	= deinterlace_runtime_suspend,
-+};
-+
-+static struct platform_driver deinterlace_driver = {
-+	.probe		= deinterlace_probe,
-+	.remove		= deinterlace_remove,
-+	.driver		= {
-+		.name		= DEINTERLACE_NAME,
-+		.of_match_table	= deinterlace_dt_match,
-+		.pm		= &deinterlace_pm_ops,
-+	},
-+};
-+module_platform_driver(deinterlace_driver);
-+
-+MODULE_LICENSE("GPL v2");
-+MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>");
-+MODULE_DESCRIPTION("Allwinner Deinterlace driver");
---- /dev/null
-+++ b/drivers/media/platform/sunxi/sun50i-di/sun50i-di.h
-@@ -0,0 +1,172 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Allwinner Deinterlace driver
-+ *
-+ * Copyright (C) 2020 Jernej Skrabec <jernej.skrabec@siol.net>
-+ */
-+
-+#ifndef _SUN8I_DEINTERLACE_H_
-+#define _SUN8I_DEINTERLACE_H_
-+
-+#include <media/v4l2-device.h>
-+#include <media/v4l2-mem2mem.h>
-+#include <media/videobuf2-v4l2.h>
-+#include <media/videobuf2-dma-contig.h>
-+
-+#include <linux/platform_device.h>
-+
-+#define DEINTERLACE_NAME		"sun50i-di"
-+
-+#define DEINTERLACE_CTRL			0x00
-+#define DEINTERLACE_CTRL_START				BIT(0)
-+#define DEINTERLACE_CTRL_IOMMU_EN			BIT(16)
-+#define DEINTERLACE_CTRL_RESET				BIT(31)
-+
-+#define DEINTERLACE_INT_CTRL			0x04
-+#define DEINTERLACE_INT_EN				BIT(0)
-+
-+#define DEINTERLACE_STATUS			0x08
-+#define DEINTERLACE_STATUS_FINISHED			BIT(0)
-+#define DEINTERLACE_STATUS_BUSY				BIT(8)
-+
-+#define DEINTERLACE_SIZE			0x10
-+#define DEINTERLACE_SIZE_WIDTH(w) \
-+	(((w) - 1) & 0x7ff)
-+#define DEINTERLACE_SIZE_HEIGHT(h) \
-+	((((h) - 1) & 0x7ff) << 16)
-+
-+#define DEINTERLACE_FORMAT			0x14
-+#define DEINTERLACE_FORMAT_YUV420P			0
-+#define DEINTERLACE_FORMAT_YUV420SP			1
-+#define DEINTERLACE_FORMAT_YUV422P			2
-+#define DEINTERLACE_FORMAT_YUV422SP			3
-+
-+#define DEINTERLACE_POLAR			0x18
-+#define DEINTERLACE_POLAR_FIELD(x)			((x) & 1)
-+
-+/* all pitch registers accept 16-bit values */
-+#define DEINTERLACE_IN_PITCH0			0x20
-+#define DEINTERLACE_IN_PITCH1			0x24
-+#define DEINTERLACE_IN_PITCH2			0x28
-+#define DEINTERLACE_OUT_PITCH0			0x30
-+#define DEINTERLACE_OUT_PITCH1			0x34
-+#define DEINTERLACE_OUT_PITCH2			0x38
-+#define DEINTERLACE_FLAG_PITCH			0x40
-+#define DEINTERLACE_IN0_ADDR0			0x50
-+#define DEINTERLACE_IN0_ADDR1			0x54
-+#define DEINTERLACE_IN0_ADDR2			0x58
-+#define DEINTERLACE_IN0_ADDRH			0x5c
-+#define DEINTERLACE_IN1_ADDR0			0x60
-+#define DEINTERLACE_IN1_ADDR1			0x64
-+#define DEINTERLACE_IN1_ADDR2			0x68
-+#define DEINTERLACE_IN1_ADDRH			0x6c
-+#define DEINTERLACE_IN2_ADDR0			0x70
-+#define DEINTERLACE_IN2_ADDR1			0x74
-+#define DEINTERLACE_IN2_ADDR2			0x78
-+#define DEINTERLACE_IN2_ADDRH			0x7c
-+#define DEINTERLACE_IN3_ADDR0			0x80
-+#define DEINTERLACE_IN3_ADDR1			0x84
-+#define DEINTERLACE_IN3_ADDR2			0x88
-+#define DEINTERLACE_IN3_ADDRH			0x8c
-+#define DEINTERLACE_OUT_ADDR0			0x90
-+#define DEINTERLACE_OUT_ADDR1			0x94
-+#define DEINTERLACE_OUT_ADDR2			0x98
-+#define DEINTERLACE_OUT_ADDRH			0x9c
-+#define DEINTERLACE_IN_FLAG_ADDR		0xa0
-+#define DEINTERLACE_OUT_FLAG_ADDR		0xa4
-+#define DEINTERLACE_FLAG_ADDRH			0xa8
-+
-+#define DEINTERLACE_ADDRH0(x)				((x) & 0xff)
-+#define DEINTERLACE_ADDRH1(x)				(((x) & 0xff) << 8)
-+#define DEINTERLACE_ADDRH2(x)				(((x) & 0xff) << 16)
-+
-+#define DEINTERLACE_MODE			0xb0
-+#define DEINTERLACE_MODE_DEINT_LUMA			BIT(0)
-+#define DEINTERLACE_MODE_MOTION_EN			BIT(4)
-+#define DEINTERLACE_MODE_INTP_EN			BIT(5)
-+#define DEINTERLACE_MODE_AUTO_UPD_MODE(x)		(((x) & 3) << 12)
-+#define DEINTERLACE_MODE_DEINT_CHROMA			BIT(16)
-+#define DEINTERLACE_MODE_FIELD_MODE			BIT(31)
-+
-+#define DEINTERLACE_MD_PARAM0			0xb4
-+#define DEINTERLACE_MD_PARAM0_MIN_LUMA_TH(x)		((x) & 0xff)
-+#define DEINTERLACE_MD_PARAM0_MAX_LUMA_TH(x)		(((x) & 0xff) << 8)
-+#define DEINTERLACE_MD_PARAM0_AVG_LUMA_SHIFT(x)		(((x) & 0xf) << 16)
-+#define DEINTERLACE_MD_PARAM0_TH_SHIFT(x)		(((x) & 0xf) << 24)
-+
-+#define DEINTERLACE_MD_PARAM1			0xb8
-+#define DEINTERLACE_MD_PARAM1_MOV_FAC_NONEDGE(x)	(((x) & 0x3) << 28)
-+
-+#define DEINTERLACE_MD_PARAM2			0xbc
-+#define DEINTERLACE_MD_PARAM2_CHROMA_SPATIAL_TH(x)	(((x) & 0xff) << 8)
-+#define DEINTERLACE_MD_PARAM2_CHROMA_DIFF_TH(x)		(((x) & 0xff) << 16)
-+#define DEINTERLACE_MD_PARAM2_PIX_STATIC_TH(x)		(((x) & 0x3) << 28)
-+
-+#define DEINTERLACE_INTP_PARAM0			0xc0
-+#define DEINTERLACE_INTP_PARAM0_ANGLE_LIMIT(x)		((x) & 0x1f)
-+#define DEINTERLACE_INTP_PARAM0_ANGLE_CONST_TH(x)	(((x) & 7) << 8)
-+#define DEINTERLACE_INTP_PARAM0_LUMA_CUR_FAC_MODE(x)	(((x) & 7) << 16)
-+#define DEINTERLACE_INTP_PARAM0_LUMA_CUR_FAC_MODE_MSK	(7 << 16)
-+#define DEINTERLACE_INTP_PARAM0_CHROMA_CUR_FAC_MODE(x)	(((x) & 7) << 20)
-+#define DEINTERLACE_INTP_PARAM0_CHROMA_CUR_FAC_MODE_MSK	(7 << 20)
-+
-+#define DEINTERLACE_MD_CH_PARAM			0xc4
-+#define DEINTERLACE_MD_CH_PARAM_BLEND_MODE(x)		((x) & 0xf)
-+#define DEINTERLACE_MD_CH_PARAM_FONT_PRO_EN		BIT(8)
-+#define DEINTERLACE_MD_CH_PARAM_FONT_PRO_TH(x)		(((x) & 0xff) << 16)
-+#define DEINTERLACE_MD_CH_PARAM_FONT_PRO_FAC(x)		(((x) & 0x1f) << 24)
-+
-+#define DEINTERLACE_INTP_PARAM1			0xc8
-+#define DEINTERLACE_INTP_PARAM1_A(x)			((x) & 7)
-+#define DEINTERLACE_INTP_PARAM1_EN			BIT(3)
-+#define DEINTERLACE_INTP_PARAM1_C(x)			(((x) & 0xf) << 4)
-+#define DEINTERLACE_INTP_PARAM1_CMAX(x)			(((x) & 0xff) << 8)
-+#define DEINTERLACE_INTP_PARAM1_MAXRAT(x)		(((x) & 3) << 16)
-+
-+#define DEINTERLACE_OUT_PATH			0x200
-+
-+#define DEINTERLACE_MIN_WIDTH	2U
-+#define DEINTERLACE_MIN_HEIGHT	2U
-+#define DEINTERLACE_MAX_WIDTH	2048U
-+#define DEINTERLACE_MAX_HEIGHT	1100U
-+
-+struct deinterlace_ctx {
-+	struct v4l2_fh		fh;
-+	struct deinterlace_dev	*dev;
-+
-+	struct v4l2_pix_format	src_fmt;
-+	struct v4l2_pix_format	dst_fmt;
-+
-+	void			*flag1_buf;
-+	dma_addr_t		flag1_buf_dma;
-+
-+	void			*flag2_buf;
-+	dma_addr_t		flag2_buf_dma;
-+
-+	struct vb2_v4l2_buffer	*prev[2];
-+
-+	unsigned int		first_field;
-+	unsigned int		field;
-+
-+	int			aborting;
-+};
-+
-+struct deinterlace_dev {
-+	struct v4l2_device	v4l2_dev;
-+	struct video_device	vfd;
-+	struct device		*dev;
-+	struct v4l2_m2m_dev	*m2m_dev;
-+
-+	/* Device file mutex */
-+	struct mutex		dev_mutex;
-+
-+	void __iomem		*base;
-+
-+	struct clk		*bus_clk;
-+	struct clk		*mod_clk;
-+	struct clk		*ram_clk;
-+
-+	struct reset_control	*rstc;
-+};
-+
-+#endif
diff --git a/0041-arm64-dts-h6-deinterlace.patch b/0041-arm64-dts-h6-deinterlace.patch
deleted file mode 100644
index 265437c41923..000000000000
--- a/0041-arm64-dts-h6-deinterlace.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From c009b3b707bbde30fa6ff49ca3075160524ea7b9 Mon Sep 17 00:00:00 2001
-From: Jernej Skrabec <jernej.skrabec@siol.net>
-Date: Tue, 26 May 2020 20:08:27 +0200
-Subject: [PATCH 41/44] arm64: dts: h6 deinterlace
-
-Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
----
- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 11 +++++++++++
- 1 file changed, 11 insertions(+)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
-@@ -153,6 +153,17 @@
- 			};
- 		};
- 
-+		deinterlace: deinterlace@1420000 {
-+			compatible = "allwinner,sun50i-h6-deinterlace";
-+			reg = <0x01420000 0x2000>;
-+			clocks = <&ccu CLK_BUS_DEINTERLACE>,
-+				 <&ccu CLK_DEINTERLACE>,
-+				 <&ccu CLK_MBUS_DEINTERLACE>;
-+			clock-names = "bus", "mod", "ram";
-+			resets = <&ccu RST_BUS_DEINTERLACE>;
-+			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-+		};
-+
- 		video-codec@1c0e000 {
- 			compatible = "allwinner,sun50i-h6-video-engine";
- 			reg = <0x01c0e000 0x2000>;
-
-
diff --git a/HACK-media-uapi-hevc-tiles-and-num_slices.patch b/HACK-media-uapi-hevc-tiles-and-num_slices.patch
new file mode 100644
index 000000000000..65dc37f12816
--- /dev/null
+++ b/HACK-media-uapi-hevc-tiles-and-num_slices.patch
@@ -0,0 +1,37 @@
+From 59b72897a905b8254ac5ff697465bc02e2d0e87e Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sat, 23 May 2020 15:07:15 +0000
+Subject: [PATCH 055/101] HACK: media: uapi: hevc: tiles and num_slices
+
+---
+ include/media/hevc-ctrls.h | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h
+index a808894e8..f1b875652 100644
+--- a/include/media/hevc-ctrls.h
++++ b/include/media/hevc-ctrls.h
+@@ -83,7 +83,8 @@ struct v4l2_ctrl_hevc_sps {
+ 	__u8	chroma_format_idc;
+ 	__u8	sps_max_sub_layers_minus1;
+ 
+-	__u8	padding[6];
++	__u8	num_slices;
++	__u8	padding[5];
+ 
+ 	__u64	flags;
+ };
+@@ -210,7 +211,9 @@ struct v4l2_ctrl_hevc_slice_params {
+ 	__u16	short_term_ref_pic_set_size;
+ 	__u16	long_term_ref_pic_set_size;
+ 
+-	__u8	padding[4];
++	__u32	num_entry_point_offsets;
++	__u32	entry_point_offset_minus1[256];
++	__u8	padding[8];
+ 
+ 	/* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */
+ 	struct v4l2_hevc_pred_weight_table pred_weight_table;
+-- 
+2.31.1
+
diff --git a/PKGBUILD b/PKGBUILD
index effca06d51f2..9d08ea47f716 100644
--- a/PKGBUILD
+++ b/PKGBUILD
@@ -6,63 +6,96 @@
 # https://github.com/armbian/build/tree/master/patch/kernel/archive/sunxi-5.11
 
 pkgbase=linux-tqc-a01
-_srcname=linux-5.14
+_srcname=linux-5.17
 _kernelname=${pkgbase#linux}
 _desc="AArch64 kernel for TQC A01"
-pkgver=5.14.8
+pkgver=5.17.7
 pkgrel=1
 arch=('aarch64')
 url="http://www.kernel.org/"
 license=('GPL2')
 makedepends=('xmlto' 'docbook-xsl' 'kmod' 'inetutils' 'bc' 'git' 'uboot-tools' 'vboot-utils' 'dtc')
 options=('!strip')
-source=("http://cdn.kernel.org/pub/linux/kernel/v5.x/${_srcname}.tar.xz"
+source=(
+        # "http://cdn.kernel.org/pub/linux/kernel/v5.x/${_srcname}.tar.xz"
+        "https://mirror.bjtu.edu.cn/kernel/linux/kernel/v5.x/${_srcname}.tar.xz"
         'sun50i-h6-tqc-a01.dts'
-        '0001-mfd-Add-support-for-AC200.patch'
-        '0001-HACK-h6-Add-HDMI-sound-card.patch'
-	'0001-make-proc-cpuinfo-consistent-on-arm64-and-arm.patch'
-        '0002-net-phy-Add-support-for-AC200-EPHY.patch'
-        '0002-net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regu.patch'
-        '0003-net-stmmac-sun8i-Rename-PHY-regulator-variable-to-re.patch'
-        '0003-arm64-dts-allwinner-h6-Add-AC200-EPHY-related-nodes.patch'
-        '0004-net-stmmac-sun8i-Add-support-for-enabling-a-regulato.patch'
-        '0005-drm-gem-cma-Export-with-handle-allocator.patch'
-        '0006-drm-sun4i-Add-GEM-allocator.patch'
-        '0010-general-h6-add-dma-i2c-ir-spi-uart.patch'
-	'0011-dts-h6-tqc-a01-cpu-opp-2ghz.patch'
-	'0012-arm64-h6-gpu-devfreq-enable.patch'
-	'0040-wip-H6-deinterlace.patch'
-	'0041-arm64-dts-h6-deinterlace.patch'
+        # custom
+        '0001-make-proc-cpuinfo-consistent-on-arm64-and-arm.patch'
+        '0011-dts-h6-tqc-a01-cpu-opp-2ghz.patch'
+        '0012-arm64-h6-gpu-devfreq-enable.patch'
+        # emmc
+        '0012-fix-h6-emmc.patch'
+        '0013-x-fix-h6-emmc-dts.patch'
+        # ethernet
+        'arm64-dts-sun50i-h6-Add-AC200-EPHY-related-nodes.patch'
+        'drv-net-phy-Add-support-for-AC200-EPHY.patch'
+        'drv-mfd-Add-support-for-AC200.patch'
+        'net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch'
+        'net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch'
+        'net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch'
+        # hdmi sound
+        'arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch'
+        # audio codec
+        '0009-allwinner-h6-support-ac200-audio-codec.patch'
+        # misc
+        '0010-allwinner-add-sunxi_get_soc_chipid-and-sunxi_get_ser.patch'
+        'arm64-dts-sun50i-h6.dtsi-improve-thermals.patch'
+        'arm64-dts-allwinner-h6-Add-SCPI-protocol.patch'
+        'arm64-dts-allwinner-h6-Protect-SCP-clocks.patch'
+        'drv-pinctrl-sunxi-pinctrl-sun50i-h6.c-GPIO-disable_strict_mode.patch'
+        # cedrus
+        'WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch'
+        'HACK-media-uapi-hevc-tiles-and-num_slices.patch'
+        'Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch'
+        'drv-media-cedrus-10-bit-HEVC-support.patch'
+        'drv-media-cedrus-Add-callback-for-buffer-cleanup.patch'
+        'drv-media-cedrus-h264-Improve-buffer-management.patch'
+        'drv-media-cedrus-hevc-Improve-buffer-management.patch'
+        'drv-media-cedrus-hevc-tiles-hack.patch'
+
         'config'
         'linux.preset'
         '60-linux.hook'
         '90-linux.hook')
 
 [[ ${pkgver##*.} != 0 ]] && \
-source+=("https://cdn.kernel.org/pub/linux/kernel/v5.x/patch-${pkgver}.xz")
+# source+=("https://cdn.kernel.org/pub/linux/kernel/v5.x/patch-${pkgver}.xz")
+source+=("https://mirror.bjtu.edu.cn/kernel/linux/kernel/v5.x/patch-${pkgver}.xz")
 
-md5sums=('a082ef5748b813abca0649dab8be5f52'
-         '46d921dba031a9f397955a787c71911e'
-         '17aa0c69176c68cd98b4522740a1b747'
-         '2285d81ec6fb859d34b7abfd46a59550'
+md5sums=('07321a70a48d062cebd0358132f11771'
+         '5dc58208abd2ad11ad2aa67fadf1c66f'
          '7a18066683f3351b2bbd2653db783f80'
-         'bc7904920675ba8d38f21d46ffac33b5'
-         '94a69594f90309c50c83a5cc8579fb54'
-         'e1868e41094baff9eceba481fc097c79'
-         '2d2de8db5e0c7d8f51a05fd33000c19a'
-         '5d42a68276c8f9e8b3de040fa2579b84'
-         '335382823f6dc2aae2f6038b7aee339e'
-         'cb38b30491472097c3b9b475de39127f'
-         'bc65c0b9e4d6fb2fe3a81b8358886885'
          '74baf0cb243b3abd5e38f0131c95408f'
-         '05c4d9cbe622d5ff15e6b84b1c5c1a70'
-         'd1543c205b4faf9be4552d4308228217'
-         'e4ef0ae46cdfb23abb11d729452f68b2'
-         '80fec552244267a059d06399c1a3c931'
+         '947f64e1c0eec0564cb683940a5af51f'
+         '6c58c6697e1275038acf579251c69d31'
+         '2d7918618ec227b65d35078b3c7862ce'
+         '5cf059c6de6dbee8d20041dcb735f5b1'
+         'f0826f12d7b1f597fba32913e8580543'
+         '714a3df875f3a05aee07c7c464ad3fe0'
+         'c6bb7c8ce8d41c93d5c2b70f4110135f'
+         'abe164c89da5fb50bb4c866c1d5fe03b'
+         '72a95b87caccf7f36dff15ed1e4a6df9'
+         'f8aa3197a5c1e6d01cb1809c31cc2d92'
+         'eda5ceb6d7f63318bba5ec63c601ae93'
+         'a709f3089148690f41c739275e66e9b0'
+         '99368425ced226332796b7f69fda3a2b'
+         '6ab19f7244b9f82f56edabeb7e1e1004'
+         'a95bab65e3009909138c0982ab7234aa'
+         '113ec102b9b94a8c8c44dbde7e9b8d59'
+         '196331c28fc1c77f78d7c6378cfb9e9e'
+         'ec38509f11f44b412f4de990502a3fb7'
+         '52d4ddae2d47320b97ce311106b407af'
+         '2eb1edf94864c3c0b2a6f82463f84d67'
+         '28ce48cd57b8776a75f4fed54569ffd1'
+         'f5e2e35d9f0955cef5cf2332f901ff09'
+         'b36af4f711a0aeb3f0edeb522a9e97bf'
+         'dafb6c0da0e1c6be55c18fc50c850fab'
+         'ce726485a1ab9c726037aa02fdfa15f1'
          '66e0ae63183426b28c0ec0c7e10b5e16'
          'ce6c81ad1ad1f8b333fd6077d47abdaf'
          '3dc88030a8f2f5a5f97266d99b149f77'
-         '767e2bd13b4f1497f7500877792cbff2')
+         'c942f79b0f310ca6e8d5828fad539a7f')
 
 prepare() {
   cd ${_srcname}
@@ -76,22 +109,39 @@ prepare() {
   echo "dtb-\$(CONFIG_ARCH_SUNXI) += ${target_dts//dts/dtb}" >> "./arch/arm64/boot/dts/allwinner/Makefile"
   cat "${srcdir}/${target_dts}" > "./arch/arm64/boot/dts/allwinner/${target_dts}"
 
-  # patches for TQC A01
-  patch -p1 < ../0001-mfd-Add-support-for-AC200.patch
-  patch -p1 < ../0001-HACK-h6-Add-HDMI-sound-card.patch
+  # patches
   patch -p1 < ../0001-make-proc-cpuinfo-consistent-on-arm64-and-arm.patch
-  patch -p1 < ../0002-net-phy-Add-support-for-AC200-EPHY.patch
-  patch -p1 < ../0002-net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regu.patch
-  patch -p1 < ../0003-net-stmmac-sun8i-Rename-PHY-regulator-variable-to-re.patch
-  patch -p1 < ../0003-arm64-dts-allwinner-h6-Add-AC200-EPHY-related-nodes.patch
-  patch -p1 < ../0004-net-stmmac-sun8i-Add-support-for-enabling-a-regulato.patch
-  patch -p1 < ../0005-drm-gem-cma-Export-with-handle-allocator.patch
-  patch -p1 < ../0006-drm-sun4i-Add-GEM-allocator.patch
-  patch -p1 < ../0010-general-h6-add-dma-i2c-ir-spi-uart.patch
   patch -p1 < ../0011-dts-h6-tqc-a01-cpu-opp-2ghz.patch
   patch -p1 < ../0012-arm64-h6-gpu-devfreq-enable.patch
-  patch -p1 < ../0040-wip-H6-deinterlace.patch
-  patch -p1 < ../0041-arm64-dts-h6-deinterlace.patch
+
+  patch -p1 < ../0012-fix-h6-emmc.patch
+  patch -p1 < ../0013-x-fix-h6-emmc-dts.patch
+  
+  patch -p1 < ../arm64-dts-sun50i-h6-Add-AC200-EPHY-related-nodes.patch
+  patch -p1 < ../drv-net-phy-Add-support-for-AC200-EPHY.patch
+  patch -p1 < ../drv-mfd-Add-support-for-AC200.patch
+  patch -p1 < ../net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch
+  patch -p1 < ../net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch
+  patch -p1 < ../net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch
+
+  patch -p1 < ../arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch
+  
+  patch -p1 < ../0009-allwinner-h6-support-ac200-audio-codec.patch
+
+  patch -p1 < ../0010-allwinner-add-sunxi_get_soc_chipid-and-sunxi_get_ser.patch
+  patch -p1 < ../arm64-dts-sun50i-h6.dtsi-improve-thermals.patch
+  patch -p1 < ../arm64-dts-allwinner-h6-Add-SCPI-protocol.patch
+  patch -p1 < ../arm64-dts-allwinner-h6-Protect-SCP-clocks.patch
+  patch -p1 < ../drv-pinctrl-sunxi-pinctrl-sun50i-h6.c-GPIO-disable_strict_mode.patch
+
+  patch -p1 < ../WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch
+  patch -p1 < ../HACK-media-uapi-hevc-tiles-and-num_slices.patch
+  patch -p1 < ../Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch
+  patch -p1 < ../drv-media-cedrus-10-bit-HEVC-support.patch
+  patch -p1 < ../drv-media-cedrus-Add-callback-for-buffer-cleanup.patch
+  patch -p1 < ../drv-media-cedrus-h264-Improve-buffer-management.patch
+  patch -p1 < ../drv-media-cedrus-hevc-Improve-buffer-management.patch
+  patch -p1 < ../drv-media-cedrus-hevc-tiles-hack.patch
 
   cat "${srcdir}/config" > ./.config
 
diff --git a/Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch b/Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch
new file mode 100644
index 000000000000..63d36cae38ec
--- /dev/null
+++ b/Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch
@@ -0,0 +1,287 @@
+From e3e9a55245fcadd5658cf783a3c273b4b4835b9e Mon Sep 17 00:00:00 2001
+From: Igor Pecovnik <igor.pecovnik@gmail.com>
+Date: Sat, 6 Nov 2021 19:15:23 +0100
+Subject: [PATCH 003/101] Revert "net: Remove net/ipx.h and uapi/linux/ipx.h
+ header files"
+
+This reverts commit 6c9b40844751ea30c72f7a2f92f4d704bc6b2927.
+---
+ include/net/ipx.h        | 171 +++++++++++++++++++++++++++++++++++++++
+ include/uapi/linux/ipx.h |  87 ++++++++++++++++++++
+ 2 files changed, 258 insertions(+)
+ create mode 100644 include/net/ipx.h
+ create mode 100644 include/uapi/linux/ipx.h
+
+diff --git a/include/net/ipx.h b/include/net/ipx.h
+new file mode 100644
+index 000000000..9d1342807
+--- /dev/null
++++ b/include/net/ipx.h
+@@ -0,0 +1,171 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++#ifndef _NET_INET_IPX_H_
++#define _NET_INET_IPX_H_
++/*
++ *	The following information is in its entirety obtained from:
++ *
++ *	Novell 'IPX Router Specification' Version 1.10 
++ *		Part No. 107-000029-001
++ *
++ *	Which is available from ftp.novell.com
++ */
++
++#include <linux/netdevice.h>
++#include <net/datalink.h>
++#include <linux/ipx.h>
++#include <linux/list.h>
++#include <linux/slab.h>
++#include <linux/refcount.h>
++
++struct ipx_address {
++	__be32  net;
++	__u8    node[IPX_NODE_LEN]; 
++	__be16  sock;
++};
++
++#define ipx_broadcast_node	"\377\377\377\377\377\377"
++#define ipx_this_node           "\0\0\0\0\0\0"
++
++#define IPX_MAX_PPROP_HOPS 8
++
++struct ipxhdr {
++	__be16			ipx_checksum __packed;
++#define IPX_NO_CHECKSUM	cpu_to_be16(0xFFFF)
++	__be16			ipx_pktsize __packed;
++	__u8			ipx_tctrl;
++	__u8			ipx_type;
++#define IPX_TYPE_UNKNOWN	0x00
++#define IPX_TYPE_RIP		0x01	/* may also be 0 */
++#define IPX_TYPE_SAP		0x04	/* may also be 0 */
++#define IPX_TYPE_SPX		0x05	/* SPX protocol */
++#define IPX_TYPE_NCP		0x11	/* $lots for docs on this (SPIT) */
++#define IPX_TYPE_PPROP		0x14	/* complicated flood fill brdcast */
++	struct ipx_address	ipx_dest __packed;
++	struct ipx_address	ipx_source __packed;
++};
++
++/* From af_ipx.c */
++extern int sysctl_ipx_pprop_broadcasting;
++
++struct ipx_interface {
++	/* IPX address */
++	__be32			if_netnum;
++	unsigned char		if_node[IPX_NODE_LEN];
++	refcount_t		refcnt;
++
++	/* physical device info */
++	struct net_device	*if_dev;
++	struct datalink_proto	*if_dlink;
++	__be16			if_dlink_type;
++
++	/* socket support */
++	unsigned short		if_sknum;
++	struct hlist_head	if_sklist;
++	spinlock_t		if_sklist_lock;
++
++	/* administrative overhead */
++	int			if_ipx_offset;
++	unsigned char		if_internal;
++	unsigned char		if_primary;
++	
++	struct list_head	node; /* node in ipx_interfaces list */
++};
++
++struct ipx_route {
++	__be32			ir_net;
++	struct ipx_interface	*ir_intrfc;
++	unsigned char		ir_routed;
++	unsigned char		ir_router_node[IPX_NODE_LEN];
++	struct list_head	node; /* node in ipx_routes list */
++	refcount_t		refcnt;
++};
++
++struct ipx_cb {
++	u8	ipx_tctrl;
++	__be32	ipx_dest_net;
++	__be32	ipx_source_net;
++	struct {
++		__be32 netnum;
++		int index;
++	} last_hop;
++};
++
++#include <net/sock.h>
++
++struct ipx_sock {
++	/* struct sock has to be the first member of ipx_sock */
++	struct sock		sk;
++	struct ipx_address	dest_addr;
++	struct ipx_interface	*intrfc;
++	__be16			port;
++#ifdef CONFIG_IPX_INTERN
++	unsigned char		node[IPX_NODE_LEN];
++#endif
++	unsigned short		type;
++	/*
++	 * To handle special ncp connection-handling sockets for mars_nwe,
++ 	 * the connection number must be stored in the socket.
++	 */
++	unsigned short		ipx_ncp_conn;
++};
++
++static inline struct ipx_sock *ipx_sk(struct sock *sk)
++{
++	return (struct ipx_sock *)sk;
++}
++
++#define IPX_SKB_CB(__skb) ((struct ipx_cb *)&((__skb)->cb[0]))
++
++#define IPX_MIN_EPHEMERAL_SOCKET	0x4000
++#define IPX_MAX_EPHEMERAL_SOCKET	0x7fff
++
++extern struct list_head ipx_routes;
++extern rwlock_t ipx_routes_lock;
++
++extern struct list_head ipx_interfaces;
++struct ipx_interface *ipx_interfaces_head(void);
++extern spinlock_t ipx_interfaces_lock;
++
++extern struct ipx_interface *ipx_primary_net;
++
++int ipx_proc_init(void);
++void ipx_proc_exit(void);
++
++const char *ipx_frame_name(__be16);
++const char *ipx_device_name(struct ipx_interface *intrfc);
++
++static __inline__ void ipxitf_hold(struct ipx_interface *intrfc)
++{
++	refcount_inc(&intrfc->refcnt);
++}
++
++void ipxitf_down(struct ipx_interface *intrfc);
++struct ipx_interface *ipxitf_find_using_net(__be32 net);
++int ipxitf_send(struct ipx_interface *intrfc, struct sk_buff *skb, char *node);
++__be16 ipx_cksum(struct ipxhdr *packet, int length);
++int ipxrtr_add_route(__be32 network, struct ipx_interface *intrfc,
++		     unsigned char *node);
++void ipxrtr_del_routes(struct ipx_interface *intrfc);
++int ipxrtr_route_packet(struct sock *sk, struct sockaddr_ipx *usipx,
++			struct msghdr *msg, size_t len, int noblock);
++int ipxrtr_route_skb(struct sk_buff *skb);
++struct ipx_route *ipxrtr_lookup(__be32 net);
++int ipxrtr_ioctl(unsigned int cmd, void __user *arg);
++
++static __inline__ void ipxitf_put(struct ipx_interface *intrfc)
++{
++	if (refcount_dec_and_test(&intrfc->refcnt))
++		ipxitf_down(intrfc);
++}
++
++static __inline__ void ipxrtr_hold(struct ipx_route *rt)
++{
++	        refcount_inc(&rt->refcnt);
++}
++
++static __inline__ void ipxrtr_put(struct ipx_route *rt)
++{
++	        if (refcount_dec_and_test(&rt->refcnt))
++			                kfree(rt);
++}
++#endif /* _NET_INET_IPX_H_ */
+diff --git a/include/uapi/linux/ipx.h b/include/uapi/linux/ipx.h
+new file mode 100644
+index 000000000..3168137ad
+--- /dev/null
++++ b/include/uapi/linux/ipx.h
+@@ -0,0 +1,87 @@
++/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
++#ifndef _IPX_H_
++#define _IPX_H_
++#include <linux/libc-compat.h>	/* for compatibility with glibc netipx/ipx.h */
++#include <linux/types.h>
++#include <linux/sockios.h>
++#include <linux/socket.h>
++#define IPX_NODE_LEN	6
++#define IPX_MTU		576
++
++#if __UAPI_DEF_SOCKADDR_IPX
++struct sockaddr_ipx {
++	__kernel_sa_family_t sipx_family;
++	__be16		sipx_port;
++	__be32		sipx_network;
++	unsigned char 	sipx_node[IPX_NODE_LEN];
++	__u8		sipx_type;
++	unsigned char	sipx_zero;	/* 16 byte fill */
++};
++#endif /* __UAPI_DEF_SOCKADDR_IPX */
++
++/*
++ * So we can fit the extra info for SIOCSIFADDR into the address nicely
++ */
++#define sipx_special	sipx_port
++#define sipx_action	sipx_zero
++#define IPX_DLTITF	0
++#define IPX_CRTITF	1
++
++#if __UAPI_DEF_IPX_ROUTE_DEFINITION
++struct ipx_route_definition {
++	__be32        ipx_network;
++	__be32        ipx_router_network;
++	unsigned char ipx_router_node[IPX_NODE_LEN];
++};
++#endif /* __UAPI_DEF_IPX_ROUTE_DEFINITION */
++
++#if __UAPI_DEF_IPX_INTERFACE_DEFINITION
++struct ipx_interface_definition {
++	__be32        ipx_network;
++	unsigned char ipx_device[16];
++	unsigned char ipx_dlink_type;
++#define IPX_FRAME_NONE		0
++#define IPX_FRAME_SNAP		1
++#define IPX_FRAME_8022		2
++#define IPX_FRAME_ETHERII	3
++#define IPX_FRAME_8023		4
++#define IPX_FRAME_TR_8022       5 /* obsolete */
++	unsigned char ipx_special;
++#define IPX_SPECIAL_NONE	0
++#define IPX_PRIMARY		1
++#define IPX_INTERNAL		2
++	unsigned char ipx_node[IPX_NODE_LEN];
++};
++#endif /* __UAPI_DEF_IPX_INTERFACE_DEFINITION */
++
++#if __UAPI_DEF_IPX_CONFIG_DATA
++struct ipx_config_data {
++	unsigned char	ipxcfg_auto_select_primary;
++	unsigned char	ipxcfg_auto_create_interfaces;
++};
++#endif /* __UAPI_DEF_IPX_CONFIG_DATA */
++
++/*
++ * OLD Route Definition for backward compatibility.
++ */
++
++#if __UAPI_DEF_IPX_ROUTE_DEF
++struct ipx_route_def {
++	__be32		ipx_network;
++	__be32		ipx_router_network;
++#define IPX_ROUTE_NO_ROUTER	0
++	unsigned char	ipx_router_node[IPX_NODE_LEN];
++	unsigned char	ipx_device[16];
++	unsigned short	ipx_flags;
++#define IPX_RT_SNAP		8
++#define IPX_RT_8022		4
++#define IPX_RT_BLUEBOOK		2
++#define IPX_RT_ROUTED		1
++};
++#endif /* __UAPI_DEF_IPX_ROUTE_DEF */
++
++#define SIOCAIPXITFCRT		(SIOCPROTOPRIVATE)
++#define SIOCAIPXPRISLT		(SIOCPROTOPRIVATE + 1)
++#define SIOCIPXCFGDATA		(SIOCPROTOPRIVATE + 2)
++#define SIOCIPXNCPCONN		(SIOCPROTOPRIVATE + 3)
++#endif /* _IPX_H_ */
+-- 
+2.31.1
+
diff --git a/WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch b/WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch
new file mode 100644
index 000000000000..5d99721b10fa
--- /dev/null
+++ b/WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch
@@ -0,0 +1,66 @@
+From b47ff0ab5ea204f3db72e8ab1c1b4a69679e6441 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sat, 23 May 2020 15:03:46 +0000
+Subject: [PATCH 054/101] WIP: media: uapi: hevc: add fields needed for rkvdec
+
+NOTE: these fields are used by rkvdec hevc backend
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ include/media/hevc-ctrls.h | 12 ++++++++++--
+ 1 file changed, 10 insertions(+), 2 deletions(-)
+
+diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h
+index ef63bc205..a808894e8 100644
+--- a/include/media/hevc-ctrls.h
++++ b/include/media/hevc-ctrls.h
+@@ -58,6 +58,8 @@ enum v4l2_mpeg_video_hevc_start_code {
+ /* The controls are not stable at the moment and will likely be reworked. */
+ struct v4l2_ctrl_hevc_sps {
+ 	/* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */
++	__u8	video_parameter_set_id;
++	__u8	seq_parameter_set_id;
+ 	__u16	pic_width_in_luma_samples;
+ 	__u16	pic_height_in_luma_samples;
+ 	__u8	bit_depth_luma_minus8;
+@@ -81,6 +83,8 @@ struct v4l2_ctrl_hevc_sps {
+ 	__u8	chroma_format_idc;
+ 	__u8	sps_max_sub_layers_minus1;
+ 
++	__u8	padding[6];
++
+ 	__u64	flags;
+ };
+ 
+@@ -108,6 +112,7 @@ struct v4l2_ctrl_hevc_sps {
+ 
+ struct v4l2_ctrl_hevc_pps {
+ 	/* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */
++	__u8	pic_parameter_set_id;
+ 	__u8	num_extra_slice_header_bits;
+ 	__u8	num_ref_idx_l0_default_active_minus1;
+ 	__u8	num_ref_idx_l1_default_active_minus1;
+@@ -123,7 +128,7 @@ struct v4l2_ctrl_hevc_pps {
+ 	__s8	pps_tc_offset_div2;
+ 	__u8	log2_parallel_merge_level_minus2;
+ 
+-	__u8	padding[4];
++	__u8	padding;
+ 	__u64	flags;
+ };
+ 
+@@ -202,7 +207,10 @@ struct v4l2_ctrl_hevc_slice_params {
+ 	__u8	ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
+ 	__u8	ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
+ 
+-	__u8	padding;
++	__u16	short_term_ref_pic_set_size;
++	__u16	long_term_ref_pic_set_size;
++
++	__u8	padding[4];
+ 
+ 	/* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */
+ 	struct v4l2_hevc_pred_weight_table pred_weight_table;
+-- 
+2.31.1
+
diff --git a/arm64-dts-allwinner-h6-Add-SCPI-protocol.patch b/arm64-dts-allwinner-h6-Add-SCPI-protocol.patch
new file mode 100644
index 000000000000..684e2328e44a
--- /dev/null
+++ b/arm64-dts-allwinner-h6-Add-SCPI-protocol.patch
@@ -0,0 +1,51 @@
+From 02c2f2e87095289bce9f122db8e7381cd8d73585 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 14 Dec 2019 20:54:40 -0600
+Subject: [PATCH 161/456] arm64: dts: allwinner: h6: Add SCPI protocol
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 15decf102be2..6182ac2c1a68 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -88,6 +88,13 @@ psci {
+ 		method = "smc";
+ 	};
+ 
++	scpi_protocol: scpi {
++		compatible = "arm,scpi";
++		mboxes = <&msgbox 2>, <&msgbox 3>;
++		mbox-names = "tx", "rx";
++		shmem = <&scpi_sram>;
++	};
++
+ 	timer {
+ 		compatible = "arm,armv8-timer";
+ 		arm,no-tick-in-suspend;
+@@ -205,6 +212,19 @@ syscon: syscon@3000000 {
+ 			#size-cells = <1>;
+ 			ranges;
+ 
++			sram_a2: sram@100000 {
++				compatible = "mmio-sram";
++				reg = <0x00100000 0x18000>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++				ranges = <0 0x00100000 0x18000>;
++
++				scpi_sram: scp-shmem@17c00 {
++					compatible = "arm,scp-shmem";
++					reg = <0x17c00 0x200>;
++				};
++			};
++
+ 			sram_c: sram@28000 {
+ 				compatible = "mmio-sram";
+ 				reg = <0x00028000 0x1e000>;
+-- 
+2.34.1
+
diff --git a/arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch b/arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch
new file mode 100644
index 000000000000..603522ba0505
--- /dev/null
+++ b/arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch
@@ -0,0 +1,48 @@
+From adb0ca8feafa851620a83071a51864bcd4f420dc Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Tue, 10 Nov 2020 20:43:28 +0100
+Subject: [PATCH 243/456] arm64: dts: allwinner: h6: Add hdmi sound card
+
+H6 supports HDMI audio. Add a sound card node for it.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index fbe94abbb1f9..60d7ee645c31 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -101,6 +101,20 @@ scpi_protocol: scpi {
+ 		shmem = <&scpi_sram>;
+ 	};
+ 
++	sound_hdmi: sound_hdmi {
++		compatible = "allwinner,sun9i-a80-hdmi-audio",
++			     "allwinner,sun50i-h6-hdmi-audio";
++		status = "disabled";
++
++		codec {
++			sound-dai = <&hdmi>;
++		};
++
++		cpu {
++			sound-dai = <&i2s1>;
++		};
++	};
++
+ 	timer {
+ 		compatible = "arm,armv8-timer";
+ 		arm,no-tick-in-suspend;
+@@ -805,6 +819,7 @@ ohci3: usb@5311400 {
+ 		};
+ 
+ 		hdmi: hdmi@6000000 {
++			#sound-dai-cells = <0>;
+ 			compatible = "allwinner,sun50i-h6-dw-hdmi";
+ 			reg = <0x06000000 0x10000>;
+ 			reg-io-width = <1>;
+-- 
+2.34.1
+
diff --git a/arm64-dts-allwinner-h6-Protect-SCP-clocks.patch b/arm64-dts-allwinner-h6-Protect-SCP-clocks.patch
new file mode 100644
index 000000000000..c295a76ef556
--- /dev/null
+++ b/arm64-dts-allwinner-h6-Protect-SCP-clocks.patch
@@ -0,0 +1,33 @@
+From d484d4f4a31aadfeebaaa40924467d9a482e883e Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 1 Jan 2020 16:04:01 -0600
+Subject: [PATCH 147/456] arm64: dts: allwinner: h6: Protect SCP clocks
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index fbe94abbb1f9..15decf102be2 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -239,6 +239,7 @@ ccu: clock@3001000 {
+ 			reg = <0x03001000 0x1000>;
+ 			clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
+ 			clock-names = "hosc", "losc", "iosc";
++			protected-clocks = <CLK_BUS_MSGBOX>;
+ 			#clock-cells = <1>;
+ 			#reset-cells = <1>;
+ 		};
+@@ -934,6 +935,7 @@ r_ccu: clock@7010000 {
+ 			clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
+ 				 <&ccu CLK_PLL_PERIPH0>;
+ 			clock-names = "hosc", "losc", "iosc", "pll-periph";
++			protected-clocks = <CLK_R_APB1_TWD>;
+ 			#clock-cells = <1>;
+ 			#reset-cells = <1>;
+ 		};
+-- 
+2.34.1
+
diff --git a/0003-arm64-dts-allwinner-h6-Add-AC200-EPHY-related-nodes.patch b/arm64-dts-sun50i-h6-Add-AC200-EPHY-related-nodes.patch
index 6cb3c33c0ef7..c83054d5b144 100644
--- a/0003-arm64-dts-allwinner-h6-Add-AC200-EPHY-related-nodes.patch
+++ b/arm64-dts-sun50i-h6-Add-AC200-EPHY-related-nodes.patch
@@ -1,7 +1,7 @@
-From 1b08baab634bebd4ef94ca449b81d7550c91abf0 Mon Sep 17 00:00:00 2001
+From c843cbfb9d8c5b68ed2fedfd2d6905ec852f2873 Mon Sep 17 00:00:00 2001
 From: Jernej Skrabec <jernej.skrabec@siol.net>
 Date: Sun, 12 Jan 2020 12:09:12 +0100
-Subject: [PATCH 3/4] arm64: dts: allwinner: h6: Add AC200 EPHY related nodes
+Subject: [PATCH 011/101] arm64:dts: sun50i-h6: Add AC200 EPHY related nodes
 
 Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
 ---
@@ -9,12 +9,12 @@ Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
  1 file changed, 63 insertions(+)
 
 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
-index 3329283e38ab..81caf1e96407 100644
+index 6cdebbbff..7c17076d9 100644
 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
 +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
-@@ -16,6 +16,16 @@
- 	#address-cells = <1>;
- 	#size-cells = <1>;
+@@ -22,6 +22,16 @@ aliases {
+ 		mmc2 = &mmc2;
+ 	};
  
 +	ac200_pwm_clk: ac200_clk {
 +		compatible = "pwm-clock";
@@ -29,21 +29,21 @@ index 3329283e38ab..81caf1e96407 100644
  	cpus {
  		#address-cells = <1>;
  		#size-cells = <0>;
-@@ -248,5 +258,9 @@
- 			ths_calibration: thermal-sensor-calibration@14 {
+@@ -307,6 +317,10 @@ ths_calibration: thermal-sensor-calibration@14 {
  				reg = <0x14 0x8>;
  			};
-+
+ 
 +			ephy_calibration: ephy-calibration@2c {
 +				reg = <0x2c 0x2>;
 +			};
- 
++
  			cpu_speed_grade: cpu-speed-grade@1c {
-@@ -291,6 +305,14 @@
- 				function = "emac";
+ 				reg = <0x1c 0x4>;
+ 			};
+@@ -364,6 +378,14 @@ ext_rgmii_pins: rgmii-pins {
  				drive-strength = <40>;
  			};
-+			
+ 
 +			/omit-if-no-ref/
 +			ext_rmii_pins: rmii_pins {
 +				pins = "PA0", "PA1", "PA2", "PA3", "PA4",
@@ -51,22 +51,23 @@ index 3329283e38ab..81caf1e96407 100644
 +				function = "emac";
 +				drive-strength = <40>;
 +			};
- 
++
  			hdmi_pins: hdmi-pins {
  				pins = "PH8", "PH9", "PH10";
-@@ -311,6 +333,11 @@
- 				pins = "PD23", "PD24";
+ 				function = "hdmi";
+@@ -384,6 +406,11 @@ i2c2_pins: i2c2-pins {
  				function = "i2c2";
  			};
-+			
+ 
 +			i2c3_pins: i2c3-pins {
 +				pins = "PB17", "PB18";
 +				function = "i2c3";
 +			};
- 
++
  			mmc0_pins: mmc0-pins {
  				pins = "PF0", "PF1", "PF2", "PF3",
-@@ -329,6 +356,11 @@
+ 				       "PF4", "PF5";
+@@ -401,6 +428,11 @@ mmc1_pins: mmc1-pins {
  				bias-pull-up;
  			};
  
@@ -78,7 +79,7 @@ index 3329283e38ab..81caf1e96407 100644
  			mmc2_pins: mmc2-pins {
  				pins = "PC1", "PC4", "PC5", "PC6",
  				       "PC7", "PC8", "PC9", "PC10",
-@@ -504,6 +536,37 @@
+@@ -643,6 +675,38 @@ spi1: spi@5011000 {
  			#size-cells = <0>;
  		};
  
@@ -98,6 +99,7 @@ index 3329283e38ab..81caf1e96407 100644
 +			ac200: mfd@10 {
 +				compatible = "x-powers,ac200";
 +				reg = <0x10>;
++				clocks = <&ac200_pwm_clk>;
 +				interrupt-parent = <&pio>;
 +				interrupts = <1 20 IRQ_TYPE_LEVEL_LOW>;
 +				interrupt-controller;
@@ -117,5 +119,5 @@ index 3329283e38ab..81caf1e96407 100644
  			compatible = "allwinner,sun50i-h6-emac",
  				     "allwinner,sun50i-a64-emac";
 -- 
-2.20.1
+2.31.1
 
diff --git a/arm64-dts-sun50i-h6.dtsi-improve-thermals.patch b/arm64-dts-sun50i-h6.dtsi-improve-thermals.patch
new file mode 100644
index 000000000000..7638e8dd0449
--- /dev/null
+++ b/arm64-dts-sun50i-h6.dtsi-improve-thermals.patch
@@ -0,0 +1,111 @@
+From 9eac817d9c58eee57d287e09e1ff1b5e62746342 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 25 Jan 2022 17:02:30 +0300
+Subject: [PATCH 093/101] arm64:dts: sun50i-h6.dtsi improve thermals
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 68 ++++++++++++++++----
+ 1 file changed, 55 insertions(+), 13 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index ceda702d6..35279469c 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -1,5 +1,6 @@
+ // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ // Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
++// Copyright (C) 2020 Igor Pecovnik <igor@armbian.com>
+ 
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/sun50i-h6-ccu.h>
+@@ -1177,33 +1178,74 @@ ths: thermal-sensor@5070400 {
+ 
+ 	thermal-zones {
+ 		cpu-thermal {
+-			polling-delay-passive = <0>;
+-			polling-delay = <0>;
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
+ 			thermal-sensors = <&ths 0>;
+ 
+ 			trips {
+-				cpu_alert: cpu-alert {
++				cpu_warm: cpu_warm {
++					temperature = <75000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_hot_pre: cpu_hot_pre {
++					temperature = <80000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_hot: cpu_hot {
+ 					temperature = <85000>;
+ 					hysteresis = <2000>;
+ 					type = "passive";
+ 				};
+ 
+-				cpu-crit {
+-					temperature = <100000>;
+-					hysteresis = <0>;
++				cpu_very_hot_pre: cpu_very_hot_pre {
++					temperature = <90000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_very_hot: cpu_very_hot {
++					temperature = <95000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_crit: cpu_crit {
++					temperature = <105000>;
++					hysteresis = <2000>;
+ 					type = "critical";
+ 				};
+ 			};
+ 
+ 			cooling-maps {
+-				map0 {
+-					trip = <&cpu_alert>;
+-					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+-							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+-							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+-							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++				cpu_warm_limit_cpu {
++					trip = <&cpu_warm>;
++					cooling-device = <&cpu0 THERMAL_NO_LIMIT 2>;
+ 				};
+-			};
++
++				cpu_hot_pre_limit_cpu {
++					trip = <&cpu_hot_pre>;
++					cooling-device = <&cpu0 2 3>;
++				};
++
++				cpu_hot_limit_cpu {
++					trip = <&cpu_hot>;
++					cooling-device = <&cpu0 3 4>;
++				};
++
++				cpu_very_hot_pre_limit_cpu {
++					trip = <&cpu_very_hot_pre>;
++					cooling-device = <&cpu0 5 6>;
++				};
++
++				cpu_very_hot_limit_cpu {
++					trip = <&cpu_very_hot>;
++					cooling-device = <&cpu0 7 THERMAL_NO_LIMIT>;
++				};
++		       };
+ 		};
+ 
+ 		gpu-thermal {
+-- 
+2.31.1
+
diff --git a/config b/config
index 8aeec1b77607..8bd3f3270f49 100644
--- a/config
+++ b/config
@@ -1,19 +1,20 @@
 #
 # Automatically generated file; DO NOT EDIT.
-# Linux/arm64 5.14.8-1 Kernel Configuration
+# Linux/arm64 5.17.7-1 Kernel Configuration
 #
-CONFIG_CC_VERSION_TEXT="gcc (GCC) 10.2.0"
+CONFIG_CC_VERSION_TEXT="gcc (GCC) 11.2.0"
 CONFIG_CC_IS_GCC=y
-CONFIG_GCC_VERSION=100200
+CONFIG_GCC_VERSION=110200
 CONFIG_CLANG_VERSION=0
 CONFIG_AS_IS_GNU=y
-CONFIG_AS_VERSION=23500
+CONFIG_AS_VERSION=23800
 CONFIG_LD_IS_BFD=y
-CONFIG_LD_VERSION=23500
+CONFIG_LD_VERSION=23800
 CONFIG_LLD_VERSION=0
 CONFIG_CC_CAN_LINK=y
 CONFIG_CC_CAN_LINK_STATIC=y
 CONFIG_CC_HAS_ASM_GOTO=y
+CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
 CONFIG_CC_HAS_ASM_INLINE=y
 CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
 CONFIG_IRQ_WORK=y
@@ -25,6 +26,7 @@ CONFIG_THREAD_INFO_IN_TASK=y
 #
 CONFIG_INIT_ENV_ARG_LIMIT=32
 # CONFIG_COMPILE_TEST is not set
+# CONFIG_WERROR is not set
 CONFIG_LOCALVERSION="-ARCH"
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_BUILD_SALT=""
@@ -60,7 +62,6 @@ CONFIG_GENERIC_IRQ_IPI=y
 CONFIG_GENERIC_MSI_IRQ=y
 CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
 CONFIG_IRQ_MSI_IOMMU=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
 CONFIG_IRQ_FORCED_THREADING=y
 CONFIG_SPARSE_IRQ=y
 # CONFIG_GENERIC_IRQ_DEBUGFS is not set
@@ -70,6 +71,8 @@ CONFIG_GENERIC_TIME_VSYSCALL=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_ARCH_HAS_TICK_BROADCAST=y
 CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
 
 #
 # Timers subsystem
@@ -99,6 +102,7 @@ CONFIG_USERMODE_DRIVER=y
 # CONFIG_BPF_PRELOAD is not set
 # end of BPF subsystem
 
+CONFIG_PREEMPT_VOLUNTARY_BUILD=y
 # CONFIG_PREEMPT_NONE is not set
 CONFIG_PREEMPT_VOLUNTARY=y
 # CONFIG_PREEMPT is not set
@@ -145,6 +149,7 @@ CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=18
 CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
+# CONFIG_PRINTK_INDEX is not set
 CONFIG_GENERIC_SCHED_CLOCK=y
 
 #
@@ -155,6 +160,7 @@ CONFIG_GENERIC_SCHED_CLOCK=y
 
 CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
 CONFIG_CC_HAS_INT128=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
 CONFIG_ARCH_SUPPORTS_INT128=y
 CONFIG_CGROUPS=y
 CONFIG_PAGE_COUNTER=y
@@ -215,13 +221,11 @@ CONFIG_SYSFS_SYSCALL=y
 CONFIG_FHANDLE=y
 CONFIG_POSIX_TIMERS=y
 CONFIG_PRINTK=y
-CONFIG_PRINTK_NMI=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_FUTEX_PI=y
-CONFIG_HAVE_FUTEX_CMPXCHG=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
@@ -241,6 +245,7 @@ CONFIG_RSEQ=y
 # CONFIG_DEBUG_RSEQ is not set
 # CONFIG_EMBEDDED is not set
 CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_GUEST_PERF_EVENTS=y
 # CONFIG_PC104 is not set
 
 #
@@ -278,7 +283,6 @@ CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
 CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
 CONFIG_GENERIC_HWEIGHT=y
@@ -363,6 +367,11 @@ CONFIG_ARM64_ERRATUM_1286807=y
 CONFIG_ARM64_ERRATUM_1463225=y
 CONFIG_ARM64_ERRATUM_1542419=y
 CONFIG_ARM64_ERRATUM_1508412=y
+CONFIG_ARM64_ERRATUM_2051678=y
+CONFIG_ARM64_ERRATUM_2077057=y
+CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
+CONFIG_ARM64_ERRATUM_2054223=y
+CONFIG_ARM64_ERRATUM_2067961=y
 CONFIG_CAVIUM_ERRATUM_22375=y
 CONFIG_CAVIUM_ERRATUM_23154=y
 CONFIG_CAVIUM_ERRATUM_27456=y
@@ -389,6 +398,7 @@ CONFIG_ARM64_PA_BITS=48
 # CONFIG_CPU_BIG_ENDIAN is not set
 CONFIG_CPU_LITTLE_ENDIAN=y
 CONFIG_SCHED_MC=y
+# CONFIG_SCHED_CLUSTER is not set
 CONFIG_SCHED_SMT=y
 CONFIG_NR_CPUS=8
 CONFIG_HOTPLUG_CPU=y
@@ -401,7 +411,6 @@ CONFIG_HZ=100
 CONFIG_SCHED_HRTICK=y
 CONFIG_ARCH_SPARSEMEM_ENABLE=y
 CONFIG_HW_PERF_EVENTS=y
-CONFIG_ARCH_HAS_FILTER_PGPROT=y
 CONFIG_PARAVIRT=y
 CONFIG_PARAVIRT_TIME_ACCOUNTING=y
 CONFIG_KEXEC=y
@@ -412,6 +421,7 @@ CONFIG_TRANS_TABLE=y
 # CONFIG_XEN is not set
 CONFIG_FORCE_MAX_ZONEORDER=11
 CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y
 CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
 # CONFIG_ARM64_SW_TTBR0_PAN is not set
 CONFIG_ARM64_TAGGED_ADDR_ABI=y
@@ -436,6 +446,8 @@ CONFIG_ARM64_USE_LSE_ATOMICS=y
 #
 # ARMv8.2 architectural features
 #
+CONFIG_AS_HAS_ARMV8_2=y
+CONFIG_AS_HAS_SHA3=y
 # CONFIG_ARM64_PMEM is not set
 CONFIG_ARM64_RAS_EXTN=y
 CONFIG_ARM64_CNP=y
@@ -591,55 +603,6 @@ CONFIG_QORIQ_CPUFREQ=m
 # end of CPU Frequency scaling
 # end of CPU Power Management
 
-#
-# Firmware Drivers
-#
-CONFIG_ARM_SCMI_PROTOCOL=y
-CONFIG_ARM_SCMI_POWER_DOMAIN=y
-CONFIG_ARM_SCPI_PROTOCOL=y
-CONFIG_ARM_SCPI_POWER_DOMAIN=y
-# CONFIG_ARM_SDE_INTERFACE is not set
-# CONFIG_FIRMWARE_MEMMAP is not set
-CONFIG_DMIID=y
-CONFIG_DMI_SYSFS=y
-# CONFIG_ISCSI_IBFT is not set
-# CONFIG_FW_CFG_SYSFS is not set
-CONFIG_ARM_FFA_TRANSPORT=m
-CONFIG_ARM_FFA_SMCCC=y
-# CONFIG_GOOGLE_FIRMWARE is not set
-
-#
-# EFI (Extensible Firmware Interface) Support
-#
-CONFIG_EFI_ESRT=y
-CONFIG_EFI_VARS_PSTORE=y
-CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y
-CONFIG_EFI_PARAMS_FROM_FDT=y
-CONFIG_EFI_RUNTIME_WRAPPERS=y
-CONFIG_EFI_GENERIC_STUB=y
-# CONFIG_EFI_ARMSTUB_DTB_LOADER is not set
-CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
-CONFIG_EFI_BOOTLOADER_CONTROL=y
-# CONFIG_EFI_CAPSULE_LOADER is not set
-# CONFIG_EFI_TEST is not set
-# CONFIG_RESET_ATTACK_MITIGATION is not set
-# CONFIG_EFI_DISABLE_PCI_DMA is not set
-# end of EFI (Extensible Firmware Interface) Support
-
-CONFIG_EFI_EARLYCON=y
-CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
-CONFIG_ARM_PSCI_FW=y
-# CONFIG_ARM_PSCI_CHECKER is not set
-CONFIG_HAVE_ARM_SMCCC=y
-CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
-CONFIG_ARM_SMCCC_SOC_ID=y
-
-#
-# Tegra firmware driver
-#
-# end of Tegra firmware driver
-# end of Firmware Drivers
-
 CONFIG_ARCH_SUPPORTS_ACPI=y
 CONFIG_ACPI=y
 CONFIG_ACPI_GENERIC_GSI=y
@@ -672,13 +635,14 @@ CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
 CONFIG_HAVE_ACPI_APEI=y
 # CONFIG_ACPI_APEI is not set
 CONFIG_ACPI_CONFIGFS=m
+# CONFIG_ACPI_PFRUT is not set
 CONFIG_ACPI_IORT=y
 CONFIG_ACPI_GTDT=y
 CONFIG_ACPI_PPTT=y
+CONFIG_ACPI_PCC=y
 CONFIG_PMIC_OPREGION=y
 CONFIG_IRQ_BYPASS_MANAGER=y
-CONFIG_VIRTUALIZATION=y
-CONFIG_KVM=y
+CONFIG_HAVE_KVM=y
 CONFIG_HAVE_KVM_IRQCHIP=y
 CONFIG_HAVE_KVM_IRQFD=y
 CONFIG_HAVE_KVM_IRQ_ROUTING=y
@@ -691,6 +655,10 @@ CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y
 CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
 CONFIG_HAVE_KVM_IRQ_BYPASS=y
 CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y
+CONFIG_KVM_XFER_TO_GUEST_WORK=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_KVM=y
+# CONFIG_NVHE_EL2_DEBUG is not set
 CONFIG_ARM64_CRYPTO=y
 CONFIG_CRYPTO_SHA256_ARM64=y
 CONFIG_CRYPTO_SHA512_ARM64=y
@@ -724,8 +692,10 @@ CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
 CONFIG_KRETPROBES=y
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
+CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
 CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
 CONFIG_HAVE_NMI=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HAVE_ARCH_TRACEHOOK=y
 CONFIG_HAVE_DMA_CONTIGUOUS=y
 CONFIG_GENERIC_SMP_IDLE_THREAD=y
@@ -780,6 +750,8 @@ CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
 CONFIG_ARCH_MMAP_RND_BITS=18
 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
 CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
 CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
 CONFIG_CLONE_BACKWARDS=y
 CONFIG_OLD_SIGSUSPEND3=y
@@ -799,7 +771,6 @@ CONFIG_ARCH_USE_MEMREMAP_PROT=y
 # CONFIG_LOCK_EVENT_COUNTS is not set
 CONFIG_ARCH_HAS_RELR=y
 CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
 CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
 
 #
@@ -811,7 +782,6 @@ CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
 
 CONFIG_HAVE_GCC_PLUGINS=y
 CONFIG_GCC_PLUGINS=y
-# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set
 # CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
 # CONFIG_GCC_PLUGIN_RANDSTRUCT is not set
 # end of General architecture-dependent options
@@ -829,21 +799,21 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_COMPRESS_GZIP=y
 # CONFIG_MODULE_COMPRESS_XZ is not set
 # CONFIG_MODULE_COMPRESS_ZSTD is not set
+# CONFIG_MODULE_DECOMPRESS is not set
 # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
 CONFIG_MODPROBE_PATH="/sbin/modprobe"
 # CONFIG_TRIM_UNUSED_KSYMS is not set
 CONFIG_MODULES_TREE_LOOKUP=y
 CONFIG_BLOCK=y
-CONFIG_BLK_SCSI_REQUEST=y
 CONFIG_BLK_CGROUP_RWSTAT=y
-CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_ICQ=y
 CONFIG_BLK_DEV_BSGLIB=y
 CONFIG_BLK_DEV_INTEGRITY=y
 CONFIG_BLK_DEV_INTEGRITY_T10=y
 CONFIG_BLK_DEV_ZONED=y
 CONFIG_BLK_DEV_THROTTLING=y
 # CONFIG_BLK_DEV_THROTTLING_LOW is not set
-CONFIG_BLK_CMDLINE_PARSER=y
 CONFIG_BLK_WBT=y
 CONFIG_BLK_WBT_MQ=y
 # CONFIG_BLK_CGROUP_IOLATENCY is not set
@@ -884,6 +854,7 @@ CONFIG_BLOCK_COMPAT=y
 CONFIG_BLK_MQ_PCI=y
 CONFIG_BLK_MQ_VIRTIO=y
 CONFIG_BLK_PM=y
+CONFIG_BLOCK_HOLDER_DEPRECATED=y
 
 #
 # IO Schedulers
@@ -986,6 +957,7 @@ CONFIG_SPARSEMEM_VMEMMAP=y
 CONFIG_HAVE_FAST_GUP=y
 CONFIG_ARCH_KEEP_MEMBLOCK=y
 CONFIG_MEMORY_ISOLATION=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
 CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
 # CONFIG_MEMORY_HOTPLUG is not set
 CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
@@ -1005,7 +977,6 @@ CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
 # CONFIG_MEMORY_FAILURE is not set
 # CONFIG_TRANSPARENT_HUGEPAGE is not set
-CONFIG_CLEANCACHE=y
 CONFIG_FRONTSWAP=y
 CONFIG_CMA=y
 # CONFIG_CMA_DEBUG is not set
@@ -1043,6 +1014,13 @@ CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
 # CONFIG_GUP_TEST is not set
 CONFIG_ARCH_HAS_PTE_SPECIAL=y
 CONFIG_SECRETMEM=y
+# CONFIG_ANON_VMA_NAME is not set
+
+#
+# Data Access Monitoring
+#
+# CONFIG_DAMON is not set
+# end of Data Access Monitoring
 # end of Memory Management options
 
 CONFIG_NET=y
@@ -1059,6 +1037,7 @@ CONFIG_PACKET=y
 CONFIG_PACKET_DIAG=m
 CONFIG_UNIX=y
 CONFIG_UNIX_SCM=y
+CONFIG_AF_UNIX_OOB=y
 CONFIG_UNIX_DIAG=m
 CONFIG_TLS=m
 # CONFIG_TLS_DEVICE is not set
@@ -1163,6 +1142,7 @@ CONFIG_IPV6_SEG6_LWTUNNEL=y
 CONFIG_IPV6_SEG6_HMAC=y
 CONFIG_IPV6_SEG6_BPF=y
 # CONFIG_IPV6_RPL_LWTUNNEL is not set
+# CONFIG_IPV6_IOAM6_LWTUNNEL is not set
 CONFIG_NETLABEL=y
 CONFIG_MPTCP=y
 CONFIG_INET_MPTCP_DIAG=m
@@ -1178,6 +1158,8 @@ CONFIG_BRIDGE_NETFILTER=m
 # Core Netfilter Configuration
 #
 CONFIG_NETFILTER_INGRESS=y
+CONFIG_NETFILTER_EGRESS=y
+CONFIG_NETFILTER_SKIP_EGRESS=y
 CONFIG_NETFILTER_NETLINK=m
 CONFIG_NETFILTER_FAMILY_BRIDGE=y
 CONFIG_NETFILTER_FAMILY_ARP=y
@@ -1230,7 +1212,6 @@ CONFIG_NF_TABLES_NETDEV=y
 CONFIG_NFT_NUMGEN=m
 CONFIG_NFT_CT=m
 CONFIG_NFT_FLOW_OFFLOAD=m
-CONFIG_NFT_COUNTER=m
 CONFIG_NFT_CONNLIMIT=m
 CONFIG_NFT_LOG=m
 CONFIG_NFT_LIMIT=m
@@ -1428,7 +1409,6 @@ CONFIG_NFT_REJECT_IPV4=m
 CONFIG_NFT_DUP_IPV4=m
 CONFIG_NFT_FIB_IPV4=m
 CONFIG_NF_TABLES_ARP=y
-CONFIG_NF_FLOW_TABLE_IPV4=m
 CONFIG_NF_DUP_IPV4=m
 CONFIG_NF_LOG_ARP=m
 CONFIG_NF_LOG_IPV4=m
@@ -1468,7 +1448,6 @@ CONFIG_NF_TABLES_IPV6=y
 CONFIG_NFT_REJECT_IPV6=m
 CONFIG_NFT_DUP_IPV6=m
 CONFIG_NFT_FIB_IPV6=m
-CONFIG_NF_FLOW_TABLE_IPV6=m
 CONFIG_NF_DUP_IPV6=m
 CONFIG_NF_REJECT_IPV6=m
 CONFIG_NF_LOG_IPV6=m
@@ -1589,8 +1568,11 @@ CONFIG_NET_DSA_TAG_DSA=m
 CONFIG_NET_DSA_TAG_EDSA=m
 # CONFIG_NET_DSA_TAG_MTK is not set
 # CONFIG_NET_DSA_TAG_KSZ is not set
-# CONFIG_NET_DSA_TAG_RTL4_A is not set
+# CONFIG_NET_DSA_TAG_OCELOT is not set
+# CONFIG_NET_DSA_TAG_OCELOT_8021Q is not set
 CONFIG_NET_DSA_TAG_QCA=m
+# CONFIG_NET_DSA_TAG_RTL4_A is not set
+# CONFIG_NET_DSA_TAG_RTL8_4 is not set
 # CONFIG_NET_DSA_TAG_LAN9303 is not set
 # CONFIG_NET_DSA_TAG_SJA1105 is not set
 CONFIG_NET_DSA_TAG_TRAILER=m
@@ -1921,6 +1903,7 @@ CONFIG_BT_HCIRSI=m
 # CONFIG_AF_RXRPC is not set
 # CONFIG_AF_KCM is not set
 CONFIG_STREAM_PARSER=y
+# CONFIG_MCTP is not set
 CONFIG_FIB_RULES=y
 CONFIG_WIRELESS=y
 CONFIG_WIRELESS_EXT=y
@@ -1960,6 +1943,7 @@ CONFIG_RFKILL_LEDS=y
 CONFIG_RFKILL_INPUT=y
 CONFIG_RFKILL_GPIO=m
 CONFIG_NET_9P=m
+CONFIG_NET_9P_FD=m
 CONFIG_NET_9P_VIRTIO=m
 # CONFIG_NET_9P_DEBUG is not set
 # CONFIG_CAIF is not set
@@ -2127,6 +2111,7 @@ CONFIG_AUXILIARY_BUS=y
 # CONFIG_UEVENT_HELPER is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_DEVTMPFS_SAFE is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 
@@ -2170,7 +2155,6 @@ CONFIG_ARM_CCI=y
 CONFIG_ARM_CCI400_COMMON=y
 # CONFIG_BRCMSTB_GISB_ARB is not set
 # CONFIG_MOXTET is not set
-CONFIG_SIMPLE_PM_BUS=y
 CONFIG_SUN50I_DE2_BUS=y
 CONFIG_SUNXI_RSB=y
 CONFIG_VEXPRESS_CONFIG=y
@@ -2181,11 +2165,75 @@ CONFIG_FSL_MC_BUS=y
 
 CONFIG_CONNECTOR=y
 CONFIG_PROC_EVENTS=y
+
+#
+# Firmware Drivers
+#
+
+#
+# ARM System Control and Management Interface Protocol
+#
+CONFIG_ARM_SCMI_PROTOCOL=y
+CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
+CONFIG_ARM_SCMI_HAVE_SHMEM=y
+CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC=y
+# CONFIG_ARM_SCMI_TRANSPORT_VIRTIO is not set
+CONFIG_ARM_SCMI_POWER_DOMAIN=y
+# end of ARM System Control and Management Interface Protocol
+
+CONFIG_ARM_SCPI_PROTOCOL=y
+CONFIG_ARM_SCPI_POWER_DOMAIN=y
+# CONFIG_ARM_SDE_INTERFACE is not set
+# CONFIG_FIRMWARE_MEMMAP is not set
+CONFIG_DMIID=y
+CONFIG_DMI_SYSFS=y
+# CONFIG_ISCSI_IBFT is not set
+# CONFIG_FW_CFG_SYSFS is not set
+CONFIG_SYSFB=y
+# CONFIG_SYSFB_SIMPLEFB is not set
+CONFIG_ARM_FFA_TRANSPORT=m
+CONFIG_ARM_FFA_SMCCC=y
+# CONFIG_GOOGLE_FIRMWARE is not set
+
+#
+# EFI (Extensible Firmware Interface) Support
+#
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_VARS_PSTORE=y
+CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y
+CONFIG_EFI_PARAMS_FROM_FDT=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_GENERIC_STUB=y
+# CONFIG_EFI_ARMSTUB_DTB_LOADER is not set
+CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
+CONFIG_EFI_BOOTLOADER_CONTROL=y
+# CONFIG_EFI_CAPSULE_LOADER is not set
+# CONFIG_EFI_TEST is not set
+# CONFIG_RESET_ATTACK_MITIGATION is not set
+# CONFIG_EFI_DISABLE_PCI_DMA is not set
+# end of EFI (Extensible Firmware Interface) Support
+
+CONFIG_EFI_EARLYCON=y
+CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
+CONFIG_ARM_PSCI_FW=y
+# CONFIG_ARM_PSCI_CHECKER is not set
+CONFIG_HAVE_ARM_SMCCC=y
+CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
+CONFIG_ARM_SMCCC_SOC_ID=y
+
+#
+# Tegra firmware driver
+#
+# end of Tegra firmware driver
+# end of Firmware Drivers
+
 CONFIG_GNSS=m
 CONFIG_GNSS_SERIAL=m
 CONFIG_GNSS_MTK_SERIAL=m
 # CONFIG_GNSS_SIRF_SERIAL is not set
 # CONFIG_GNSS_UBX_SERIAL is not set
+# CONFIG_GNSS_USB is not set
 CONFIG_MTD=y
 # CONFIG_MTD_TESTS is not set
 
@@ -2205,6 +2253,10 @@ CONFIG_MTD_OF_PARTS=m
 CONFIG_MTD_BLKDEVS=m
 CONFIG_MTD_BLOCK=m
 # CONFIG_MTD_BLOCK_RO is not set
+
+#
+# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK.
+#
 # CONFIG_FTL is not set
 # CONFIG_NFTL is not set
 # CONFIG_INFTL is not set
@@ -2336,7 +2388,6 @@ CONFIG_OF_KOBJ=y
 CONFIG_OF_DYNAMIC=y
 CONFIG_OF_ADDRESS=y
 CONFIG_OF_IRQ=y
-CONFIG_OF_NET=y
 CONFIG_OF_RESERVED_MEM=y
 CONFIG_OF_RESOLVE=y
 CONFIG_OF_OVERLAY=y
@@ -2364,7 +2415,6 @@ CONFIG_ZRAM_DEF_COMP="lzo-rle"
 # CONFIG_ZRAM_MEMORY_TRACKING is not set
 CONFIG_BLK_DEV_LOOP=m
 CONFIG_BLK_DEV_LOOP_MIN_COUNT=0
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
 CONFIG_BLK_DEV_DRBD=m
 # CONFIG_DRBD_FAULT_INJECTION is not set
 CONFIG_BLK_DEV_NBD=m
@@ -2378,7 +2428,6 @@ CONFIG_CDROM_PKTCDVD_BUFFERS=8
 CONFIG_ATA_OVER_ETH=m
 CONFIG_VIRTIO_BLK=y
 CONFIG_BLK_DEV_RBD=m
-# CONFIG_BLK_DEV_RSXX is not set
 
 #
 # NVME Support
@@ -2403,6 +2452,7 @@ CONFIG_TIFM_CORE=y
 CONFIG_TIFM_7XX1=m
 # CONFIG_ICS932S401 is not set
 CONFIG_ENCLOSURE_SERVICES=m
+# CONFIG_HI6421V600_IRQ is not set
 # CONFIG_HP_ILO is not set
 CONFIG_APDS9802ALS=m
 CONFIG_ISL29003=m
@@ -2461,6 +2511,7 @@ CONFIG_UACCE=m
 #
 CONFIG_SCSI_MOD=y
 CONFIG_RAID_ATTRS=m
+CONFIG_SCSI_COMMON=y
 CONFIG_SCSI=y
 CONFIG_SCSI_DMA=y
 CONFIG_SCSI_NETLINK=y
@@ -2473,6 +2524,7 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_CHR_DEV_ST=m
 CONFIG_BLK_DEV_SR=y
 CONFIG_CHR_DEV_SG=y
+CONFIG_BLK_DEV_BSG=y
 CONFIG_CHR_DEV_SCH=m
 CONFIG_SCSI_ENCLOSURE=m
 CONFIG_SCSI_CONSTANTS=y
@@ -2535,6 +2587,8 @@ CONFIG_SCSI_UFSHCD_PLATFORM=y
 # CONFIG_SCSI_UFS_CDNS_PLATFORM is not set
 # CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set
 # CONFIG_SCSI_UFS_BSG is not set
+# CONFIG_SCSI_UFS_HPB is not set
+# CONFIG_SCSI_UFS_HWMON is not set
 CONFIG_SCSI_HPTIOP=m
 # CONFIG_SCSI_MYRB is not set
 # CONFIG_SCSI_MYRS is not set
@@ -2736,6 +2790,7 @@ CONFIG_DM_SWITCH=m
 CONFIG_DM_LOG_WRITES=m
 CONFIG_DM_INTEGRITY=m
 CONFIG_DM_ZONED=m
+CONFIG_DM_AUDIT=y
 CONFIG_TARGET_CORE=m
 CONFIG_TCM_IBLOCK=m
 CONFIG_TCM_FILEIO=m
@@ -2778,6 +2833,7 @@ CONFIG_VXLAN=m
 CONFIG_GENEVE=m
 # CONFIG_BAREUDP is not set
 # CONFIG_GTP is not set
+# CONFIG_AMT is not set
 # CONFIG_MACSEC is not set
 CONFIG_NETCONSOLE=m
 CONFIG_NETCONSOLE_DYNAMIC=y
@@ -2820,7 +2876,7 @@ CONFIG_NET_DSA_MV88E6XXX_PTP=y
 # CONFIG_NET_DSA_XRS700X_I2C is not set
 # CONFIG_NET_DSA_XRS700X_MDIO is not set
 CONFIG_NET_DSA_QCA8K=m
-# CONFIG_NET_DSA_REALTEK_SMI is not set
+# CONFIG_NET_DSA_REALTEK is not set
 # CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set
 # CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set
 # CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set
@@ -2851,6 +2907,8 @@ CONFIG_AMD_XGBE=m
 CONFIG_NET_VENDOR_AQUANTIA=y
 CONFIG_AQTION=m
 CONFIG_NET_VENDOR_ARC=y
+CONFIG_NET_VENDOR_ASIX=y
+# CONFIG_SPI_AX88796C is not set
 CONFIG_NET_VENDOR_ATHEROS=y
 CONFIG_ATL2=m
 CONFIG_ATL1=m
@@ -2871,7 +2929,6 @@ CONFIG_BNX2X=m
 CONFIG_BNX2X_SRIOV=y
 # CONFIG_SYSTEMPORT is not set
 # CONFIG_BNXT is not set
-# CONFIG_NET_VENDOR_BROCADE is not set
 CONFIG_NET_VENDOR_CADENCE=y
 CONFIG_MACB=m
 CONFIG_MACB_USE_HWSTAMP=y
@@ -2888,6 +2945,8 @@ CONFIG_DL2K=m
 CONFIG_SUNDANCE=m
 # CONFIG_SUNDANCE_MMIO is not set
 # CONFIG_NET_VENDOR_EMULEX is not set
+CONFIG_NET_VENDOR_ENGLEDER=y
+# CONFIG_TSNEP is not set
 # CONFIG_NET_VENDOR_EZCHIP is not set
 CONFIG_NET_VENDOR_FREESCALE=y
 CONFIG_FSL_FMAN=m
@@ -2938,8 +2997,9 @@ CONFIG_I40EVF=m
 # CONFIG_ICE is not set
 CONFIG_FM10K=m
 # CONFIG_IGC is not set
-CONFIG_NET_VENDOR_MICROSOFT=y
 CONFIG_JME=m
+CONFIG_NET_VENDOR_LITEX=y
+# CONFIG_LITEX_LITEETH is not set
 CONFIG_NET_VENDOR_MARVELL=y
 CONFIG_MVMDIO=m
 CONFIG_SKGE=m
@@ -2978,11 +3038,15 @@ CONFIG_NET_VENDOR_MICROCHIP=y
 # CONFIG_ENC28J60 is not set
 # CONFIG_ENCX24J600 is not set
 # CONFIG_LAN743X is not set
+# CONFIG_LAN966X_SWITCH is not set
 CONFIG_NET_VENDOR_MICROSEMI=y
 # CONFIG_MSCC_OCELOT_SWITCH is not set
+CONFIG_NET_VENDOR_MICROSOFT=y
 CONFIG_NET_VENDOR_MYRI=y
 CONFIG_MYRI10GE=m
 CONFIG_FEALNX=m
+CONFIG_NET_VENDOR_NI=y
+# CONFIG_NI_XGE_MANAGEMENT_ENET is not set
 CONFIG_NET_VENDOR_NATSEMI=y
 CONFIG_NATSEMI=m
 CONFIG_NS83820=m
@@ -2991,8 +3055,6 @@ CONFIG_NET_VENDOR_NETERION=y
 # CONFIG_VXGE is not set
 CONFIG_NET_VENDOR_NETRONOME=y
 # CONFIG_NFP is not set
-CONFIG_NET_VENDOR_NI=y
-# CONFIG_NI_XGE_MANAGEMENT_ENET is not set
 CONFIG_NET_VENDOR_8390=y
 CONFIG_NE2K_PCI=m
 CONFIG_NET_VENDOR_NVIDIA=y
@@ -3005,6 +3067,7 @@ CONFIG_YELLOWFIN=m
 CONFIG_NET_VENDOR_PENSANDO=y
 # CONFIG_IONIC is not set
 # CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
 CONFIG_NET_VENDOR_QUALCOMM=y
 # CONFIG_QCA7000_SPI is not set
 # CONFIG_QCA7000_UART is not set
@@ -3025,14 +3088,14 @@ CONFIG_NET_VENDOR_ROCKER=y
 CONFIG_ROCKER=m
 # CONFIG_NET_VENDOR_SAMSUNG is not set
 # CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_NET_VENDOR_SOLARFLARE=y
-# CONFIG_SFC is not set
-# CONFIG_SFC_FALCON is not set
 CONFIG_NET_VENDOR_SILAN=y
 CONFIG_SC92031=m
 CONFIG_NET_VENDOR_SIS=y
 CONFIG_SIS900=m
 CONFIG_SIS190=m
+CONFIG_NET_VENDOR_SOLARFLARE=y
+# CONFIG_SFC is not set
+# CONFIG_SFC_FALCON is not set
 CONFIG_NET_VENDOR_SMSC=y
 CONFIG_SMC91X=m
 CONFIG_EPIC100=m
@@ -3058,6 +3121,8 @@ CONFIG_TEHUTI=m
 CONFIG_NET_VENDOR_TI=y
 # CONFIG_TI_CPSW_PHY_SEL is not set
 # CONFIG_TLAN is not set
+CONFIG_NET_VENDOR_VERTEXCOM=y
+# CONFIG_MSE102X is not set
 CONFIG_NET_VENDOR_VIA=y
 CONFIG_VIA_RHINE=m
 CONFIG_VIA_RHINE_MMIO=y
@@ -3101,6 +3166,7 @@ CONFIG_LSI_ET1011C_PHY=m
 CONFIG_MARVELL_PHY=m
 CONFIG_MARVELL_10G_PHY=m
 # CONFIG_MARVELL_88X2222_PHY is not set
+# CONFIG_MAXLINEAR_GPHY is not set
 # CONFIG_MEDIATEK_GE_PHY is not set
 CONFIG_MICREL_PHY=m
 CONFIG_MICROCHIP_PHY=m
@@ -3311,6 +3377,7 @@ CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
 # CONFIG_B43LEGACY_PIO_MODE is not set
 CONFIG_BRCMUTIL=m
 CONFIG_BRCMSMAC=m
+CONFIG_BRCMSMAC_LEDS=y
 CONFIG_BRCMFMAC=m
 CONFIG_BRCMFMAC_PROTO_BCDC=y
 CONFIG_BRCMFMAC_PROTO_MSGBUF=y
@@ -3348,7 +3415,6 @@ CONFIG_IWLWIFI_LEDS=y
 CONFIG_IWLDVM=m
 CONFIG_IWLMVM=m
 CONFIG_IWLWIFI_OPMODE_MODULAR=y
-# CONFIG_IWLWIFI_BCAST_FILTERING is not set
 
 #
 # Debugging Options
@@ -3376,7 +3442,6 @@ CONFIG_P54_USB=m
 CONFIG_P54_PCI=m
 # CONFIG_P54_SPI is not set
 CONFIG_P54_LEDS=y
-CONFIG_PRISM54=m
 CONFIG_WLAN_VENDOR_MARVELL=y
 CONFIG_LIBERTAS=m
 CONFIG_LIBERTAS_USB=m
@@ -3413,6 +3478,7 @@ CONFIG_MT7615E=m
 # CONFIG_MT7663S is not set
 # CONFIG_MT7915E is not set
 # CONFIG_MT7921E is not set
+# CONFIG_MT7921S is not set
 CONFIG_WLAN_VENDOR_MICROCHIP=y
 # CONFIG_WILC1000_SDIO is not set
 # CONFIG_WILC1000_SPI is not set
@@ -3470,6 +3536,7 @@ CONFIG_RTLBTCOEXIST=m
 CONFIG_RTL8XXXU=m
 # CONFIG_RTL8XXXU_UNTESTED is not set
 # CONFIG_RTW88 is not set
+# CONFIG_RTW89 is not set
 CONFIG_WLAN_VENDOR_RSI=y
 CONFIG_RSI_91X=m
 CONFIG_RSI_DEBUGFS=y
@@ -3523,7 +3590,6 @@ CONFIG_IEEE802154_ATUSB=m
 # CONFIG_NETDEVSIM is not set
 CONFIG_NET_FAILOVER=m
 # CONFIG_ISDN is not set
-# CONFIG_NVM is not set
 
 #
 # Input device support
@@ -3580,6 +3646,7 @@ CONFIG_KEYBOARD_GPIO_POLLED=m
 CONFIG_KEYBOARD_CROS_EC=y
 # CONFIG_KEYBOARD_CAP11XX is not set
 # CONFIG_KEYBOARD_BCM is not set
+# CONFIG_KEYBOARD_CYPRESS_SF is not set
 CONFIG_INPUT_MOUSE=y
 CONFIG_MOUSE_PS2=y
 CONFIG_MOUSE_PS2_ALPS=y
@@ -3845,6 +3912,7 @@ CONFIG_SERIAL_8250_DWLIB=y
 CONFIG_SERIAL_8250_FSL=y
 CONFIG_SERIAL_8250_DW=y
 # CONFIG_SERIAL_8250_RT288X is not set
+CONFIG_SERIAL_8250_PERICOM=y
 CONFIG_SERIAL_OF_PLATFORM=y
 
 #
@@ -3891,6 +3959,7 @@ CONFIG_NOZOMI=m
 # CONFIG_NULL_TTY is not set
 CONFIG_HVC_DRIVER=y
 # CONFIG_HVC_DCC is not set
+# CONFIG_RPMSG_TTY is not set
 CONFIG_SERIAL_DEV_BUS=y
 CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
 # CONFIG_TTY_PRINTK is not set
@@ -3902,6 +3971,7 @@ CONFIG_IPMI_PLAT_DATA=y
 CONFIG_IPMI_DEVICE_INTERFACE=m
 CONFIG_IPMI_SI=m
 CONFIG_IPMI_SSIF=m
+# CONFIG_IPMI_IPMB is not set
 CONFIG_IPMI_WATCHDOG=m
 CONFIG_IPMI_POWEROFF=m
 # CONFIG_IPMB_DEVICE_INTERFACE is not set
@@ -3909,9 +3979,10 @@ CONFIG_HW_RANDOM=y
 CONFIG_HW_RANDOM_TIMERIOMEM=m
 # CONFIG_HW_RANDOM_BA431 is not set
 CONFIG_HW_RANDOM_VIRTIO=m
-CONFIG_HW_RANDOM_CAVIUM=y
 # CONFIG_HW_RANDOM_CCTRNG is not set
 # CONFIG_HW_RANDOM_XIPHERA is not set
+CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=y
+CONFIG_HW_RANDOM_CN10K=y
 # CONFIG_APPLICOM is not set
 CONFIG_DEVMEM=y
 CONFIG_DEVPORT=y
@@ -3931,10 +4002,9 @@ CONFIG_TCG_ATMEL=m
 # CONFIG_TCG_TIS_ST33ZP24_SPI is not set
 # CONFIG_XILLYBUS is not set
 # CONFIG_XILLYUSB is not set
-# end of Character devices
-
 # CONFIG_RANDOM_TRUST_CPU is not set
 # CONFIG_RANDOM_TRUST_BOOTLOADER is not set
+# end of Character devices
 
 #
 # I2C support
@@ -4033,6 +4103,7 @@ CONFIG_I2C_VIPERBOARD=m
 # Other I2C/SMBus bus drivers
 #
 CONFIG_I2C_CROS_EC_TUNNEL=y
+# CONFIG_I2C_VIRTIO is not set
 # end of I2C Hardware Bus support
 
 CONFIG_I2C_STUB=m
@@ -4058,6 +4129,7 @@ CONFIG_SPI_MEM=y
 CONFIG_SPI_BITBANG=y
 # CONFIG_SPI_CADENCE is not set
 # CONFIG_SPI_CADENCE_QUADSPI is not set
+# CONFIG_SPI_CADENCE_XSPI is not set
 # CONFIG_SPI_DESIGNWARE is not set
 # CONFIG_SPI_FSL_QUADSPI is not set
 # CONFIG_SPI_HISI_KUNPENG is not set
@@ -4115,6 +4187,7 @@ CONFIG_PPS_CLIENT_GPIO=m
 # PTP clock support
 #
 CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
 CONFIG_PTP_1588_CLOCK_QORIQ=m
 CONFIG_DP83640_PHY=m
 # CONFIG_PTP_1588_CLOCK_INES is not set
@@ -4131,16 +4204,16 @@ CONFIG_GENERIC_PINMUX_FUNCTIONS=y
 CONFIG_PINCONF=y
 CONFIG_GENERIC_PINCONF=y
 # CONFIG_DEBUG_PINCTRL is not set
-CONFIG_PINCTRL_AXP209=y
 CONFIG_PINCTRL_AMD=y
+CONFIG_PINCTRL_AXP209=y
+CONFIG_PINCTRL_MAX77620=y
 # CONFIG_PINCTRL_MCP23S08 is not set
+# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
+# CONFIG_PINCTRL_OCELOT is not set
+CONFIG_PINCTRL_RK805=y
 CONFIG_PINCTRL_SINGLE=y
-# CONFIG_PINCTRL_SX150X is not set
 # CONFIG_PINCTRL_STMFX is not set
-CONFIG_PINCTRL_MAX77620=y
-CONFIG_PINCTRL_RK805=y
-# CONFIG_PINCTRL_OCELOT is not set
-# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
+# CONFIG_PINCTRL_SX150X is not set
 
 #
 # Renesas pinctrl drivers
@@ -4263,6 +4336,8 @@ CONFIG_GPIO_VIPERBOARD=m
 #
 # CONFIG_GPIO_AGGREGATOR is not set
 # CONFIG_GPIO_MOCKUP is not set
+# CONFIG_GPIO_VIRTIO is not set
+# CONFIG_GPIO_SIM is not set
 # end of Virtual GPIO drivers
 
 CONFIG_W1=m
@@ -4336,7 +4411,6 @@ CONFIG_MANAGER_SBS=m
 CONFIG_CHARGER_AXP20X=m
 CONFIG_BATTERY_AXP20X=m
 CONFIG_AXP20X_POWER=m
-# CONFIG_AXP288_FUEL_GAUGE is not set
 # CONFIG_BATTERY_MAX17040 is not set
 CONFIG_BATTERY_MAX17042=m
 # CONFIG_BATTERY_MAX1721X is not set
@@ -4348,6 +4422,7 @@ CONFIG_BATTERY_MAX17042=m
 # CONFIG_CHARGER_LT3651 is not set
 # CONFIG_CHARGER_LTC4162L is not set
 # CONFIG_CHARGER_DETECTOR_MAX14656 is not set
+# CONFIG_CHARGER_MAX77976 is not set
 # CONFIG_CHARGER_BQ2415X is not set
 # CONFIG_CHARGER_BQ24190 is not set
 # CONFIG_CHARGER_BQ24257 is not set
@@ -4362,6 +4437,7 @@ CONFIG_CHARGER_SMB347=m
 # CONFIG_BATTERY_RT5033 is not set
 # CONFIG_CHARGER_RT9455 is not set
 CONFIG_CHARGER_CROS_USBPD=m
+CONFIG_CHARGER_CROS_PCHG=y
 # CONFIG_CHARGER_UCS1002 is not set
 # CONFIG_CHARGER_BD99954 is not set
 CONFIG_HWMON=y
@@ -4389,6 +4465,7 @@ CONFIG_SENSORS_ADT7462=m
 CONFIG_SENSORS_ADT7470=m
 CONFIG_SENSORS_ADT7475=m
 # CONFIG_SENSORS_AHT10 is not set
+# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set
 # CONFIG_SENSORS_AS370 is not set
 CONFIG_SENSORS_ASC7621=m
 # CONFIG_SENSORS_AXI_FAN_CONTROL is not set
@@ -4438,6 +4515,7 @@ CONFIG_SENSORS_MAX1668=m
 CONFIG_SENSORS_MAX197=m
 # CONFIG_SENSORS_MAX31722 is not set
 # CONFIG_SENSORS_MAX31730 is not set
+# CONFIG_SENSORS_MAX6620 is not set
 # CONFIG_SENSORS_MAX6621 is not set
 CONFIG_SENSORS_MAX6639=m
 CONFIG_SENSORS_MAX6642=m
@@ -4474,6 +4552,7 @@ CONFIG_SENSORS_NCT7802=m
 CONFIG_SENSORS_NCT7904=m
 # CONFIG_SENSORS_NPCM7XX is not set
 # CONFIG_SENSORS_NZXT_KRAKEN2 is not set
+# CONFIG_SENSORS_NZXT_SMART2 is not set
 # CONFIG_SENSORS_OCC_P8_I2C is not set
 CONFIG_SENSORS_PCF8591=m
 CONFIG_PMBUS=m
@@ -4482,6 +4561,7 @@ CONFIG_SENSORS_PMBUS=m
 CONFIG_SENSORS_ADM1275=m
 # CONFIG_SENSORS_BEL_PFE is not set
 # CONFIG_SENSORS_BPA_RS600 is not set
+# CONFIG_SENSORS_DELTA_AHE50DC_FAN is not set
 # CONFIG_SENSORS_FSP_3Y is not set
 # CONFIG_SENSORS_IBM_CFFPS is not set
 # CONFIG_SENSORS_DPS920AB is not set
@@ -4505,6 +4585,7 @@ CONFIG_SENSORS_MAX34440=m
 CONFIG_SENSORS_MAX8688=m
 # CONFIG_SENSORS_MP2888 is not set
 # CONFIG_SENSORS_MP2975 is not set
+# CONFIG_SENSORS_MP5023 is not set
 # CONFIG_SENSORS_PIM4328 is not set
 # CONFIG_SENSORS_PM6764TR is not set
 # CONFIG_SENSORS_PXE1610 is not set
@@ -4519,6 +4600,7 @@ CONFIG_SENSORS_ZL6100=m
 CONFIG_SENSORS_PWM_FAN=m
 CONFIG_SENSORS_SL28CPLD=m
 # CONFIG_SENSORS_SBTSI is not set
+# CONFIG_SENSORS_SBRMI is not set
 CONFIG_SENSORS_SHT15=m
 CONFIG_SENSORS_SHT21=m
 CONFIG_SENSORS_SHT3x=m
@@ -4543,6 +4625,7 @@ CONFIG_SENSORS_ADS7828=m
 CONFIG_SENSORS_AMC6821=m
 CONFIG_SENSORS_INA209=m
 CONFIG_SENSORS_INA2XX=m
+# CONFIG_SENSORS_INA238 is not set
 CONFIG_SENSORS_INA3221=m
 CONFIG_SENSORS_TC74=m
 CONFIG_SENSORS_THMC50=m
@@ -4700,11 +4783,11 @@ CONFIG_MFD_CROS_EC_DEV=y
 # CONFIG_MFD_MC13XXX_I2C is not set
 # CONFIG_MFD_MP2629 is not set
 # CONFIG_MFD_HI6421_PMIC is not set
+# CONFIG_MFD_HI6421_SPMI is not set
 # CONFIG_HTC_PASIC3 is not set
 # CONFIG_HTC_I2CPLD is not set
 # CONFIG_LPC_ICH is not set
 # CONFIG_LPC_SCH is not set
-# CONFIG_MFD_INTEL_PMT is not set
 # CONFIG_MFD_IQS62X is not set
 # CONFIG_MFD_JANZ_CMODIO is not set
 # CONFIG_MFD_KEMPLD is not set
@@ -4765,7 +4848,6 @@ CONFIG_MFD_SYSCON=y
 # CONFIG_MFD_TPS65910 is not set
 # CONFIG_MFD_TPS65912_I2C is not set
 # CONFIG_MFD_TPS65912_SPI is not set
-# CONFIG_MFD_TPS80031 is not set
 # CONFIG_TWL4030_CORE is not set
 # CONFIG_TWL6040_CORE is not set
 CONFIG_MFD_WL1273_CORE=m
@@ -4782,7 +4864,6 @@ CONFIG_MFD_VX855=m
 # CONFIG_MFD_WM8350_I2C is not set
 # CONFIG_MFD_WM8994 is not set
 CONFIG_MFD_ROHM_BD718XX=y
-# CONFIG_MFD_ROHM_BD70528 is not set
 # CONFIG_MFD_ROHM_BD71828 is not set
 # CONFIG_MFD_ROHM_BD957XMUF is not set
 # CONFIG_MFD_STPMIC1 is not set
@@ -4793,6 +4874,8 @@ CONFIG_MFD_WCD934X=m
 CONFIG_MFD_VEXPRESS_SYSREG=y
 # CONFIG_RAVE_SP_CORE is not set
 # CONFIG_MFD_INTEL_M10_BMC is not set
+# CONFIG_MFD_RSMU_I2C is not set
+# CONFIG_MFD_RSMU_SPI is not set
 # end of Multifunction device drivers
 
 CONFIG_REGULATOR=y
@@ -4828,6 +4911,7 @@ CONFIG_REGULATOR_MAX77620=y
 # CONFIG_REGULATOR_MAX8893 is not set
 # CONFIG_REGULATOR_MAX8952 is not set
 # CONFIG_REGULATOR_MAX8973 is not set
+# CONFIG_REGULATOR_MAX20086 is not set
 # CONFIG_REGULATOR_MAX77826 is not set
 # CONFIG_REGULATOR_MCP16502 is not set
 # CONFIG_REGULATOR_MP5416 is not set
@@ -4851,7 +4935,9 @@ CONFIG_REGULATOR_ROHM=y
 # CONFIG_REGULATOR_RT4801 is not set
 # CONFIG_REGULATOR_RT6160 is not set
 # CONFIG_REGULATOR_RT6245 is not set
+# CONFIG_REGULATOR_RTQ2134 is not set
 # CONFIG_REGULATOR_RTMV20 is not set
+# CONFIG_REGULATOR_RTQ6752 is not set
 # CONFIG_REGULATOR_S2MPA01 is not set
 CONFIG_REGULATOR_S2MPS11=y
 # CONFIG_REGULATOR_S5M8767 is not set
@@ -4906,12 +4992,15 @@ CONFIG_IR_PWM_TX=m
 CONFIG_IR_SUNXI=m
 CONFIG_IR_SERIAL=m
 CONFIG_IR_SERIAL_TRANSMITTER=y
-CONFIG_IR_SIR=m
 # CONFIG_RC_XBOX_DVD is not set
 CONFIG_IR_TOY=m
 CONFIG_CEC_CORE=m
 CONFIG_CEC_NOTIFIER=y
 CONFIG_CEC_PIN=y
+
+#
+# CEC support
+#
 CONFIG_MEDIA_CEC_RC=y
 # CONFIG_CEC_PIN_ERROR_INJ is not set
 CONFIG_MEDIA_CEC_SUPPORT=y
@@ -4919,6 +5008,8 @@ CONFIG_CEC_CH7322=m
 CONFIG_CEC_CROS_EC=m
 CONFIG_USB_PULSE8_CEC=m
 CONFIG_USB_RAINSHADOW_CEC=m
+# end of CEC support
+
 CONFIG_MEDIA_SUPPORT=m
 # CONFIG_MEDIA_SUPPORT_FILTER is not set
 CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
@@ -4952,6 +5043,8 @@ CONFIG_VIDEO_V4L2_SUBDEV_API=y
 # CONFIG_VIDEO_ADV_DEBUG is not set
 # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
 CONFIG_VIDEO_TUNER=m
+CONFIG_V4L2_H264=m
+CONFIG_V4L2_VP9=m
 CONFIG_V4L2_MEM2MEM_DEV=m
 # CONFIG_V4L2_FLASH_LED_CLASS is not set
 CONFIG_V4L2_FWNODE=m
@@ -4966,10 +5059,6 @@ CONFIG_VIDEOBUF_VMALLOC=m
 #
 CONFIG_MEDIA_CONTROLLER_DVB=y
 CONFIG_MEDIA_CONTROLLER_REQUEST_API=y
-
-#
-# Please notice that the enabled Media controller Request API is EXPERIMENTAL
-#
 # end of Media controller options
 
 #
@@ -5268,7 +5357,6 @@ CONFIG_V4L_PLATFORM_DRIVERS=y
 CONFIG_VIDEO_SUN6I_CSI=m
 CONFIG_V4L_MEM2MEM_DRIVERS=y
 # CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set
-CONFIG_VIDEO_SUN50I_DEINTERLACE=m
 CONFIG_VIDEO_SUN8I_DEINTERLACE=m
 # CONFIG_VIDEO_SUN8I_ROTATE is not set
 # CONFIG_DVB_PLATFORM_DRIVERS is not set
@@ -5398,6 +5486,7 @@ CONFIG_VIDEO_M52790=m
 # Camera sensor devices
 #
 # CONFIG_VIDEO_HI556 is not set
+# CONFIG_VIDEO_HI846 is not set
 # CONFIG_VIDEO_IMX208 is not set
 # CONFIG_VIDEO_IMX214 is not set
 CONFIG_VIDEO_IMX219=m
@@ -5406,7 +5495,9 @@ CONFIG_VIDEO_IMX219=m
 # CONFIG_VIDEO_IMX290 is not set
 # CONFIG_VIDEO_IMX319 is not set
 # CONFIG_VIDEO_IMX334 is not set
+# CONFIG_VIDEO_IMX335 is not set
 # CONFIG_VIDEO_IMX355 is not set
+# CONFIG_VIDEO_IMX412 is not set
 # CONFIG_VIDEO_OV02A10 is not set
 CONFIG_VIDEO_OV2640=m
 # CONFIG_VIDEO_OV2659 is not set
@@ -5420,6 +5511,7 @@ CONFIG_VIDEO_OV5645=m
 # CONFIG_VIDEO_OV6650 is not set
 # CONFIG_VIDEO_OV5670 is not set
 # CONFIG_VIDEO_OV5675 is not set
+# CONFIG_VIDEO_OV5693 is not set
 # CONFIG_VIDEO_OV5695 is not set
 # CONFIG_VIDEO_OV7251 is not set
 # CONFIG_VIDEO_OV772X is not set
@@ -5428,10 +5520,12 @@ CONFIG_VIDEO_OV7640=m
 # CONFIG_VIDEO_OV7740 is not set
 # CONFIG_VIDEO_OV8856 is not set
 # CONFIG_VIDEO_OV8865 is not set
+# CONFIG_VIDEO_OV9282 is not set
 # CONFIG_VIDEO_OV9640 is not set
 # CONFIG_VIDEO_OV9650 is not set
 # CONFIG_VIDEO_OV9734 is not set
 # CONFIG_VIDEO_OV13858 is not set
+# CONFIG_VIDEO_OV13B10 is not set
 # CONFIG_VIDEO_VS6624 is not set
 # CONFIG_VIDEO_MT9M001 is not set
 # CONFIG_VIDEO_MT9M032 is not set
@@ -5709,10 +5803,12 @@ CONFIG_VGA_ARB=y
 CONFIG_VGA_ARB_MAX_GPUS=16
 CONFIG_DRM=m
 CONFIG_DRM_MIPI_DSI=y
+CONFIG_DRM_DP_AUX_BUS=m
 # CONFIG_DRM_DP_AUX_CHARDEV is not set
 # CONFIG_DRM_DEBUG_SELFTEST is not set
 CONFIG_DRM_KMS_HELPER=m
 # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
+# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
 CONFIG_DRM_FBDEV_EMULATION=y
 CONFIG_DRM_FBDEV_OVERALLOC=100
 # CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
@@ -5721,9 +5817,8 @@ CONFIG_DRM_LOAD_EDID_FIRMWARE=y
 CONFIG_DRM_TTM=m
 CONFIG_DRM_VRAM_HELPER=m
 CONFIG_DRM_TTM_HELPER=m
-CONFIG_DRM_GEM_CMA_HELPER=y
-CONFIG_DRM_KMS_CMA_HELPER=y
-CONFIG_DRM_GEM_SHMEM_HELPER=y
+CONFIG_DRM_GEM_CMA_HELPER=m
+CONFIG_DRM_GEM_SHMEM_HELPER=m
 CONFIG_DRM_SCHED=m
 
 #
@@ -5755,7 +5850,8 @@ CONFIG_DRM_UDL=m
 CONFIG_DRM_AST=m
 CONFIG_DRM_MGAG200=m
 # CONFIG_DRM_RCAR_DW_HDMI is not set
-# CONFIG_DRM_RCAR_LVDS is not set
+# CONFIG_DRM_RCAR_USE_LVDS is not set
+# CONFIG_DRM_RCAR_MIPI_DSI is not set
 CONFIG_DRM_SUN4I=m
 CONFIG_DRM_SUN4I_HDMI=m
 CONFIG_DRM_SUN4I_HDMI_CEC=y
@@ -5765,7 +5861,6 @@ CONFIG_DRM_SUN8I_DW_HDMI=m
 CONFIG_DRM_SUN8I_MIXER=m
 CONFIG_DRM_SUN8I_TCON_TOP=m
 CONFIG_DRM_QXL=m
-CONFIG_DRM_BOCHS=m
 CONFIG_DRM_VIRTIO_GPU=m
 CONFIG_DRM_PANEL=y
 
@@ -5775,18 +5870,23 @@ CONFIG_DRM_PANEL=y
 # CONFIG_DRM_PANEL_ABT_Y030XX067A is not set
 # CONFIG_DRM_PANEL_ARM_VERSATILE is not set
 # CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set
+# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set
 # CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set
 # CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set
 # CONFIG_DRM_PANEL_DSI_CM is not set
 # CONFIG_DRM_PANEL_LVDS is not set
 CONFIG_DRM_PANEL_SIMPLE=m
+# CONFIG_DRM_PANEL_EDP is not set
 # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set
 # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set
 # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set
 # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
+# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set
 # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set
+# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set
 # CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set
 # CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
+# CONFIG_DRM_PANEL_JDI_R63452 is not set
 # CONFIG_DRM_PANEL_KHADAS_TS050 is not set
 # CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set
 # CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set
@@ -5796,6 +5896,7 @@ CONFIG_DRM_PANEL_SIMPLE=m
 # CONFIG_DRM_PANEL_LG_LG4573 is not set
 # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
 # CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set
 # CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set
 # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
 CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
@@ -5807,7 +5908,10 @@ CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
 CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
 # CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set
 # CONFIG_DRM_PANEL_RONBO_RB070D30 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set
 # CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set
 # CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set
 # CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set
 # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
@@ -5818,17 +5922,20 @@ CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
 # CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set
 # CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
 # CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set
+# CONFIG_DRM_PANEL_SHARP_LS060T1SX01 is not set
 # CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set
 CONFIG_DRM_PANEL_SITRONIX_ST7703=m
 # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
 # CONFIG_DRM_PANEL_SONY_ACX424AKP is not set
 # CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
+# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set
 # CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set
 # CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
 # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
 # CONFIG_DRM_PANEL_TPO_TPG110 is not set
 CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
 # CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set
+# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set
 # CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set
 # end of Display Panels
 
@@ -5888,10 +5995,12 @@ CONFIG_DRM_ETNAVIV_THERMAL=y
 CONFIG_DRM_MXS=y
 CONFIG_DRM_MXSFB=m
 # CONFIG_DRM_ARCPGU is not set
+CONFIG_DRM_BOCHS=m
 CONFIG_DRM_CIRRUS_QEMU=m
 # CONFIG_DRM_GM12U320 is not set
 # CONFIG_DRM_SIMPLEDRM is not set
 # CONFIG_TINYDRM_HX8357D is not set
+# CONFIG_TINYDRM_ILI9163 is not set
 # CONFIG_TINYDRM_ILI9225 is not set
 # CONFIG_TINYDRM_ILI9341 is not set
 # CONFIG_TINYDRM_ILI9486 is not set
@@ -5911,6 +6020,7 @@ CONFIG_DRM_LEGACY=y
 # CONFIG_DRM_VIA is not set
 # CONFIG_DRM_SAVAGE is not set
 CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_NOMODESET=y
 
 #
 # Frame buffer Devices
@@ -6018,6 +6128,7 @@ CONFIG_DUMMY_CONSOLE=y
 CONFIG_DUMMY_CONSOLE_COLUMNS=80
 CONFIG_DUMMY_CONSOLE_ROWS=25
 CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
 CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
 CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
 # CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
@@ -6159,12 +6270,15 @@ CONFIG_SND_HDA_RECONFIG=y
 CONFIG_SND_HDA_INPUT_BEEP=y
 CONFIG_SND_HDA_INPUT_BEEP_MODE=0
 CONFIG_SND_HDA_PATCH_LOADER=y
+# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
+# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
 CONFIG_SND_HDA_CODEC_REALTEK=m
 CONFIG_SND_HDA_CODEC_ANALOG=m
 CONFIG_SND_HDA_CODEC_SIGMATEL=m
 CONFIG_SND_HDA_CODEC_VIA=m
 CONFIG_SND_HDA_CODEC_HDMI=m
 CONFIG_SND_HDA_CODEC_CIRRUS=m
+# CONFIG_SND_HDA_CODEC_CS8409 is not set
 CONFIG_SND_HDA_CODEC_CONEXANT=m
 CONFIG_SND_HDA_CODEC_CA0110=m
 CONFIG_SND_HDA_CODEC_CA0132=m
@@ -6203,6 +6317,7 @@ CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
 CONFIG_SND_SOC_AMD_ACP=m
 # CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH is not set
 # CONFIG_SND_SOC_AMD_CZ_RT5645_MACH is not set
+# CONFIG_SND_AMD_ACP_CONFIG is not set
 # CONFIG_SND_ATMEL_SOC is not set
 # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
 # CONFIG_SND_DESIGNWARE_I2S is not set
@@ -6270,6 +6385,7 @@ CONFIG_SND_SOC_I2C_AND_SPI=y
 # CONFIG_SND_SOC_ADAU7118_I2C is not set
 # CONFIG_SND_SOC_AK4104 is not set
 # CONFIG_SND_SOC_AK4118 is not set
+# CONFIG_SND_SOC_AK4375 is not set
 # CONFIG_SND_SOC_AK4458 is not set
 # CONFIG_SND_SOC_AK4554 is not set
 # CONFIG_SND_SOC_AK4613 is not set
@@ -6285,6 +6401,8 @@ CONFIG_SND_SOC_CROS_EC_CODEC=m
 # CONFIG_SND_SOC_CS35L34 is not set
 # CONFIG_SND_SOC_CS35L35 is not set
 # CONFIG_SND_SOC_CS35L36 is not set
+# CONFIG_SND_SOC_CS35L41_SPI is not set
+# CONFIG_SND_SOC_CS35L41_I2C is not set
 # CONFIG_SND_SOC_CS42L42 is not set
 # CONFIG_SND_SOC_CS42L51_I2C is not set
 # CONFIG_SND_SOC_CS42L52 is not set
@@ -6311,12 +6429,14 @@ CONFIG_SND_SOC_ES8328=m
 CONFIG_SND_SOC_ES8328_I2C=m
 CONFIG_SND_SOC_ES8328_SPI=m
 # CONFIG_SND_SOC_GTM601 is not set
+# CONFIG_SND_SOC_ICS43432 is not set
 # CONFIG_SND_SOC_INNO_RK3036 is not set
 # CONFIG_SND_SOC_MAX98088 is not set
 CONFIG_SND_SOC_MAX98357A=m
 # CONFIG_SND_SOC_MAX98504 is not set
 # CONFIG_SND_SOC_MAX9867 is not set
 CONFIG_SND_SOC_MAX98927=m
+# CONFIG_SND_SOC_MAX98520 is not set
 # CONFIG_SND_SOC_MAX98373_I2C is not set
 # CONFIG_SND_SOC_MAX98373_SDW is not set
 # CONFIG_SND_SOC_MAX98390 is not set
@@ -6351,6 +6471,8 @@ CONFIG_SND_SOC_RK3328=m
 # CONFIG_SND_SOC_RT711_SDCA_SDW is not set
 # CONFIG_SND_SOC_RT715_SDW is not set
 # CONFIG_SND_SOC_RT715_SDCA_SDW is not set
+# CONFIG_SND_SOC_RT9120 is not set
+# CONFIG_SND_SOC_SDW_MOCKUP is not set
 # CONFIG_SND_SOC_SGTL5000 is not set
 CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
 # CONFIG_SND_SOC_SIMPLE_MUX is not set
@@ -6374,6 +6496,7 @@ CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
 # CONFIG_SND_SOC_TDA7419 is not set
 # CONFIG_SND_SOC_TFA9879 is not set
 # CONFIG_SND_SOC_TFA989X is not set
+# CONFIG_SND_SOC_TLV320ADC3XXX is not set
 # CONFIG_SND_SOC_TLV320AIC23_I2C is not set
 # CONFIG_SND_SOC_TLV320AIC23_SPI is not set
 # CONFIG_SND_SOC_TLV320AIC31XX is not set
@@ -6422,6 +6545,7 @@ CONFIG_SND_SOC_WSA881X=m
 # CONFIG_SND_SOC_NAU8315 is not set
 # CONFIG_SND_SOC_NAU8540 is not set
 # CONFIG_SND_SOC_NAU8810 is not set
+# CONFIG_SND_SOC_NAU8821 is not set
 # CONFIG_SND_SOC_NAU8822 is not set
 # CONFIG_SND_SOC_NAU8824 is not set
 # CONFIG_SND_SOC_TPA6130A2 is not set
@@ -6429,11 +6553,14 @@ CONFIG_SND_SOC_WSA881X=m
 # CONFIG_SND_SOC_LPASS_VA_MACRO is not set
 # CONFIG_SND_SOC_LPASS_RX_MACRO is not set
 # CONFIG_SND_SOC_LPASS_TX_MACRO is not set
+# CONFIG_SND_SOC_ACX00 is not set
 # end of CODEC drivers
 
 CONFIG_SND_SIMPLE_CARD_UTILS=m
 CONFIG_SND_SIMPLE_CARD=m
 CONFIG_SND_AUDIO_GRAPH_CARD=m
+# CONFIG_SND_AUDIO_GRAPH_CARD2 is not set
+# CONFIG_SND_TEST_COMPONENT is not set
 # CONFIG_SND_VIRTIO is not set
 CONFIG_AC97_BUS=m
 
@@ -6491,6 +6618,7 @@ CONFIG_HID_KYE=m
 CONFIG_HID_UCLOGIC=m
 CONFIG_HID_WALTOP=m
 CONFIG_HID_VIEWSONIC=m
+# CONFIG_HID_XIAOMI is not set
 CONFIG_HID_GYRATION=m
 CONFIG_HID_ICADE=m
 CONFIG_HID_ITE=m
@@ -6500,6 +6628,7 @@ CONFIG_HID_KENSINGTON=m
 CONFIG_HID_LCPOWER=m
 CONFIG_HID_LED=m
 CONFIG_HID_LENOVO=m
+# CONFIG_HID_LETSKETCH is not set
 CONFIG_HID_LOGITECH=m
 CONFIG_HID_LOGITECH_DJ=m
 CONFIG_HID_LOGITECH_HIDPP=m
@@ -6514,6 +6643,7 @@ CONFIG_HID_REDRAGON=m
 CONFIG_HID_MICROSOFT=m
 CONFIG_HID_MONTEREY=m
 CONFIG_HID_MULTITOUCH=m
+# CONFIG_HID_NINTENDO is not set
 CONFIG_HID_NTI=m
 CONFIG_HID_NTRIG=m
 CONFIG_HID_ORTEK=m
@@ -6528,7 +6658,6 @@ CONFIG_HID_PICOLCD_LCD=y
 CONFIG_HID_PICOLCD_LEDS=y
 CONFIG_HID_PICOLCD_CIR=y
 CONFIG_HID_PLANTRONICS=m
-# CONFIG_HID_PLAYSTATION is not set
 CONFIG_HID_PRIMAX=m
 CONFIG_HID_RETRODE=m
 CONFIG_HID_ROCCAT=m
@@ -7047,9 +7176,7 @@ CONFIG_LEDS_CLASS_FLASH=m
 #
 # LED drivers
 #
-# CONFIG_LEDS_AAT1290 is not set
 # CONFIG_LEDS_AN30259A is not set
-# CONFIG_LEDS_AS3645A is not set
 # CONFIG_LEDS_AW2013 is not set
 # CONFIG_LEDS_BCM6328 is not set
 # CONFIG_LEDS_BCM6358 is not set
@@ -7059,7 +7186,6 @@ CONFIG_LEDS_LM3530=m
 # CONFIG_LEDS_LM3532 is not set
 # CONFIG_LEDS_LM3642 is not set
 CONFIG_LEDS_LM3692X=m
-# CONFIG_LEDS_LM3601X is not set
 # CONFIG_LEDS_PCA9532 is not set
 CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_LP3944=m
@@ -7078,7 +7204,6 @@ CONFIG_LEDS_LT3593=m
 # CONFIG_LEDS_TCA6507 is not set
 # CONFIG_LEDS_TLC591XX is not set
 # CONFIG_LEDS_LM355x is not set
-# CONFIG_LEDS_KTD2692 is not set
 # CONFIG_LEDS_IS31FL319X is not set
 # CONFIG_LEDS_IS31FL32XX is not set
 
@@ -7091,13 +7216,17 @@ CONFIG_LEDS_SYSCON=y
 CONFIG_LEDS_USER=m
 # CONFIG_LEDS_SPI_BYTE is not set
 # CONFIG_LEDS_TI_LMU_COMMON is not set
-# CONFIG_LEDS_SGM3140 is not set
 
 #
 # Flash and Torch LED drivers
 #
+# CONFIG_LEDS_AAT1290 is not set
+# CONFIG_LEDS_AS3645A is not set
+# CONFIG_LEDS_KTD2692 is not set
+# CONFIG_LEDS_LM3601X is not set
 # CONFIG_LEDS_RT4505 is not set
 # CONFIG_LEDS_RT8515 is not set
+# CONFIG_LEDS_SGM3140 is not set
 
 #
 # LED Triggers
@@ -7124,6 +7253,10 @@ CONFIG_LEDS_TRIGGER_NETDEV=y
 CONFIG_LEDS_TRIGGER_PATTERN=m
 CONFIG_LEDS_TRIGGER_AUDIO=m
 # CONFIG_LEDS_TRIGGER_TTY is not set
+
+#
+# Simple LED drivers
+#
 CONFIG_ACCESSIBILITY=y
 CONFIG_A11Y_BRAILLE_CONSOLE=y
 
@@ -7323,6 +7456,7 @@ CONFIG_SYNC_FILE=y
 # CONFIG_DMABUF_DEBUG is not set
 # CONFIG_DMABUF_SELFTESTS is not set
 # CONFIG_DMABUF_HEAPS is not set
+# CONFIG_DMABUF_SYSFS_STATS is not set
 # end of DMABUF options
 
 CONFIG_AUXDISPLAY=y
@@ -7343,13 +7477,14 @@ CONFIG_UIO_PCI_GENERIC=m
 # CONFIG_UIO_NETX is not set
 # CONFIG_UIO_PRUSS is not set
 # CONFIG_UIO_MF624 is not set
+CONFIG_VFIO=m
 CONFIG_VFIO_IOMMU_TYPE1=m
 CONFIG_VFIO_VIRQFD=m
-CONFIG_VFIO=m
 # CONFIG_VFIO_NOIOMMU is not set
-CONFIG_VFIO_PCI=m
+CONFIG_VFIO_PCI_CORE=m
 CONFIG_VFIO_PCI_MMAP=y
 CONFIG_VFIO_PCI_INTX=y
+CONFIG_VFIO_PCI=m
 CONFIG_VFIO_PLATFORM=m
 CONFIG_VFIO_AMBA=m
 CONFIG_VFIO_PLATFORM_CALXEDAXGMAC_RESET=m
@@ -7359,6 +7494,7 @@ CONFIG_VFIO_FSL_MC=m
 # CONFIG_VIRT_DRIVERS is not set
 CONFIG_VIRTIO=y
 CONFIG_VIRTIO_PCI_LIB=y
+CONFIG_VIRTIO_PCI_LIB_LEGACY=y
 CONFIG_VIRTIO_MENU=y
 CONFIG_VIRTIO_PCI=y
 CONFIG_VIRTIO_PCI_LEGACY=y
@@ -7380,6 +7516,7 @@ CONFIG_VHOST_VSOCK=m
 #
 # Microsoft Hyper-V guest support
 #
+# CONFIG_HYPERV is not set
 # end of Microsoft Hyper-V guest support
 
 # CONFIG_GREYBUS is not set
@@ -7395,7 +7532,6 @@ CONFIG_RTL8192E=m
 # CONFIG_RTL8723BS is not set
 CONFIG_R8712U=m
 CONFIG_R8188EU=m
-CONFIG_88EU_AP_MODE=y
 # CONFIG_RTS5208 is not set
 # CONFIG_VT6655 is not set
 # CONFIG_VT6656 is not set
@@ -7462,6 +7598,9 @@ CONFIG_AD2S1210=m
 
 # CONFIG_FB_SM750 is not set
 CONFIG_STAGING_MEDIA=y
+CONFIG_VIDEO_HANTRO=m
+CONFIG_VIDEO_HANTRO_SUNXI=y
+# CONFIG_VIDEO_MAX96712 is not set
 CONFIG_VIDEO_SUNXI=y
 CONFIG_VIDEO_SUNXI_CEDRUS=m
 # CONFIG_VIDEO_ZORAN is not set
@@ -7513,14 +7652,12 @@ CONFIG_FB_TFT_TLS8204=m
 CONFIG_FB_TFT_UC1611=m
 CONFIG_FB_TFT_UC1701=m
 CONFIG_FB_TFT_UPD161704=m
-CONFIG_FB_TFT_WATTEROTT=m
 # CONFIG_KS7010 is not set
 # CONFIG_PI433 is not set
 # CONFIG_XIL_AXIS_FIFO is not set
 # CONFIG_FIELDBUS_DEV is not set
 # CONFIG_QLGE is not set
 # CONFIG_WFX is not set
-# CONFIG_MFD_HI6421_SPMI is not set
 # CONFIG_GOLDFISH is not set
 CONFIG_CHROME_PLATFORMS=y
 CONFIG_CHROMEOS_TBMC=m
@@ -7548,7 +7685,7 @@ CONFIG_COMMON_CLK=y
 #
 # Clock driver for ARM Reference designs
 #
-# CONFIG_ICST is not set
+# CONFIG_CLK_ICST is not set
 CONFIG_CLK_SP810=y
 CONFIG_CLK_VEXPRESS_OSC=y
 # end of Clock driver for ARM Reference designs
@@ -7569,6 +7706,7 @@ CONFIG_COMMON_CLK_SCPI=y
 # CONFIG_COMMON_CLK_CS2000_CP is not set
 CONFIG_COMMON_CLK_FSL_FLEXSPI=m
 # CONFIG_COMMON_CLK_FSL_SAI is not set
+# CONFIG_COMMON_CLK_LAN966X is not set
 # CONFIG_COMMON_CLK_S2MPS11 is not set
 # CONFIG_COMMON_CLK_AXI_CLKGEN is not set
 CONFIG_CLK_QORIQ=y
@@ -7590,7 +7728,6 @@ CONFIG_SUN50I_A100_R_CCU=y
 CONFIG_SUN50I_H6_CCU=y
 CONFIG_SUN50I_H616_CCU=y
 CONFIG_SUN50I_H6_R_CCU=y
-# CONFIG_SUN8I_A83T_CCU is not set
 CONFIG_SUN8I_H3_CCU=y
 CONFIG_SUN8I_DE2_CCU=y
 CONFIG_SUN8I_R_CCU=y
@@ -7640,6 +7777,8 @@ CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
 # end of Generic IOMMU Pagetable Support
 
 # CONFIG_IOMMU_DEBUGFS is not set
+CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
+# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
 # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
 CONFIG_OF_IOMMU=y
 CONFIG_IOMMU_DMA=y
@@ -7745,6 +7884,7 @@ CONFIG_DEVFREQ_GOV_PASSIVE=y
 #
 # DEVFREQ Drivers
 #
+CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=m
 CONFIG_PM_DEVFREQ_EVENT=y
 CONFIG_EXTCON=y
 
@@ -7783,9 +7923,13 @@ CONFIG_IIO_TRIGGERED_EVENT=m
 #
 CONFIG_ADIS16201=m
 CONFIG_ADIS16209=m
+# CONFIG_ADXL313_I2C is not set
+# CONFIG_ADXL313_SPI is not set
 CONFIG_ADXL345=m
 CONFIG_ADXL345_I2C=m
 CONFIG_ADXL345_SPI=m
+# CONFIG_ADXL355_I2C is not set
+# CONFIG_ADXL355_SPI is not set
 CONFIG_ADXL372=m
 CONFIG_ADXL372_SPI=m
 CONFIG_ADXL372_I2C=m
@@ -7904,6 +8048,12 @@ CONFIG_VIPERBOARD_ADC=m
 # end of Analog to digital converters
 
 #
+# Analog to digital and digital to analog converters
+#
+# CONFIG_AD74413R is not set
+# end of Analog to digital and digital to analog converters
+
+#
 # Analog Front Ends
 #
 CONFIG_IIO_RESCALE=m
@@ -7936,9 +8086,12 @@ CONFIG_PMS7003=m
 CONFIG_SCD30_CORE=m
 CONFIG_SCD30_I2C=m
 CONFIG_SCD30_SERIAL=m
+# CONFIG_SCD4X is not set
 CONFIG_SENSIRION_SGP30=m
+# CONFIG_SENSIRION_SGP40 is not set
 # CONFIG_SPS30_I2C is not set
 # CONFIG_SPS30_SERIAL is not set
+# CONFIG_SENSEAIR_SUNRISE_CO2 is not set
 CONFIG_VZ89X=m
 # end of Chemical Sensors
 
@@ -7974,6 +8127,7 @@ CONFIG_IIO_ST_SENSORS_CORE=m
 #
 # Digital to analog converters
 #
+# CONFIG_AD3552R is not set
 CONFIG_AD5064=m
 CONFIG_AD5360=m
 CONFIG_AD5380=m
@@ -7995,6 +8149,7 @@ CONFIG_AD5764=m
 # CONFIG_AD5766 is not set
 CONFIG_AD5770R=m
 CONFIG_AD5791=m
+# CONFIG_AD7293 is not set
 CONFIG_AD7303=m
 CONFIG_AD8801=m
 CONFIG_DPOT_DAC=m
@@ -8020,6 +8175,12 @@ CONFIG_VF610_DAC=m
 # end of IIO dummy driver
 
 #
+# Filters
+#
+# CONFIG_ADMV8818 is not set
+# end of Filters
+
+#
 # Frequency Synthesizers DDS/PLL
 #
 
@@ -8034,6 +8195,8 @@ CONFIG_AD9523=m
 #
 CONFIG_ADF4350=m
 CONFIG_ADF4371=m
+# CONFIG_ADMV1013 is not set
+# CONFIG_ADRF6780 is not set
 # end of Phase-Locked Loop (PLL) frequency synthesizers
 # end of Frequency Synthesizers DDS/PLL
 
@@ -8232,6 +8395,7 @@ CONFIG_IIO_SYSFS_TRIGGER=m
 #
 # Digital potentiometers
 #
+# CONFIG_AD5110 is not set
 CONFIG_AD5272=m
 CONFIG_DS1803=m
 CONFIG_MAX5432=m
@@ -8325,6 +8489,7 @@ CONFIG_TMP007=m
 CONFIG_TSYS01=m
 CONFIG_TSYS02D=m
 CONFIG_MAX31856=m
+# CONFIG_MAX31865 is not set
 # end of Temperature sensors
 
 # CONFIG_NTB is not set
@@ -8376,15 +8541,23 @@ CONFIG_PHY_SUN4I_USB=y
 CONFIG_PHY_SUN6I_MIPI_DPHY=m
 # CONFIG_PHY_SUN9I_USB is not set
 CONFIG_PHY_SUN50I_USB3=y
+
+#
+# PHY drivers for Broadcom platforms
+#
 # CONFIG_BCM_KONA_USB2_PHY is not set
+# end of PHY drivers for Broadcom platforms
+
 # CONFIG_PHY_CADENCE_TORRENT is not set
 # CONFIG_PHY_CADENCE_DPHY is not set
 # CONFIG_PHY_CADENCE_SIERRA is not set
 # CONFIG_PHY_CADENCE_SALVO is not set
 # CONFIG_PHY_FSL_IMX8MQ_USB is not set
 CONFIG_PHY_MIXEL_MIPI_DPHY=m
+# CONFIG_PHY_FSL_IMX8M_PCIE is not set
 # CONFIG_PHY_PXA_28NM_HSIC is not set
 # CONFIG_PHY_PXA_28NM_USB2 is not set
+# CONFIG_PHY_LAN966X_SERDES is not set
 # CONFIG_PHY_CPCAP_USB is not set
 # CONFIG_PHY_MAPPHONE_MDM6600 is not set
 # CONFIG_PHY_OCELOT_SERDES is not set
@@ -8414,6 +8587,7 @@ CONFIG_ARM_PMU_ACPI=y
 # CONFIG_ARM_SPE_PMU is not set
 # CONFIG_ARM_DMC620_PMU is not set
 CONFIG_HISI_PMU=y
+# CONFIG_HISI_PCIE_PMU is not set
 # end of Performance monitor support
 
 CONFIG_RAS=y
@@ -8433,7 +8607,6 @@ CONFIG_ND_BTT=m
 CONFIG_BTT=y
 CONFIG_OF_PMEM=y
 CONFIG_NVDIMM_KEYS=y
-CONFIG_DAX_DRIVER=y
 CONFIG_DAX=y
 CONFIG_NVMEM=y
 CONFIG_NVMEM_SYSFS=y
@@ -8530,13 +8703,13 @@ CONFIG_F2FS_FS_SECURITY=y
 # CONFIG_F2FS_CHECK_FS is not set
 # CONFIG_F2FS_FAULT_INJECTION is not set
 # CONFIG_F2FS_FS_COMPRESSION is not set
+CONFIG_F2FS_IOSTAT=y
 # CONFIG_ZONEFS_FS is not set
 # CONFIG_FS_DAX is not set
 CONFIG_FS_POSIX_ACL=y
 CONFIG_EXPORTFS=y
 CONFIG_EXPORTFS_BLOCK_OPS=y
 CONFIG_FILE_LOCKING=y
-CONFIG_MANDATORY_FILE_LOCKING=y
 CONFIG_FS_ENCRYPTION=y
 CONFIG_FS_ENCRYPTION_ALGS=y
 # CONFIG_FS_VERITY is not set
@@ -8569,15 +8742,13 @@ CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
 # Caches
 #
 CONFIG_NETFS_SUPPORT=m
-# CONFIG_NETFS_STATS is not set
+CONFIG_NETFS_STATS=y
 CONFIG_FSCACHE=m
 CONFIG_FSCACHE_STATS=y
-# CONFIG_FSCACHE_HISTOGRAM is not set
 # CONFIG_FSCACHE_DEBUG is not set
-CONFIG_FSCACHE_OBJECT_LIST=y
 CONFIG_CACHEFILES=m
 # CONFIG_CACHEFILES_DEBUG is not set
-# CONFIG_CACHEFILES_HISTOGRAM is not set
+# CONFIG_CACHEFILES_ERROR_INJECTION is not set
 # end of Caches
 
 #
@@ -8601,6 +8772,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
 CONFIG_EXFAT_FS=m
 CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
 # CONFIG_NTFS_FS is not set
+# CONFIG_NTFS3_FS is not set
 # end of DOS/FAT/EXFAT/NT Filesystems
 
 #
@@ -8691,6 +8863,7 @@ CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
 # CONFIG_PSTORE_CONSOLE is not set
 # CONFIG_PSTORE_PMSG is not set
 CONFIG_PSTORE_RAM=m
+# CONFIG_PSTORE_BLK is not set
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
 # CONFIG_UFS_FS_WRITE is not set
@@ -8747,7 +8920,6 @@ CONFIG_CEPH_FS_POSIX_ACL=y
 CONFIG_CIFS=m
 # CONFIG_CIFS_STATS2 is not set
 CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y
-CONFIG_CIFS_WEAK_PW_HASH=y
 CONFIG_CIFS_UPCALL=y
 CONFIG_CIFS_XATTR=y
 CONFIG_CIFS_POSIX=y
@@ -8757,6 +8929,8 @@ CONFIG_CIFS_DEBUG=y
 CONFIG_CIFS_DFS_UPCALL=y
 # CONFIG_CIFS_SWN_UPCALL is not set
 CONFIG_CIFS_FSCACHE=y
+# CONFIG_SMB_SERVER is not set
+CONFIG_SMBFS_COMMON=m
 CONFIG_CODA_FS=m
 # CONFIG_AFS_FS is not set
 CONFIG_9P_FS=m
@@ -8868,11 +9042,13 @@ CONFIG_INIT_STACK_NONE=y
 # CONFIG_GCC_PLUGIN_STACKLEAK is not set
 # CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
 # CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
+CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
+# CONFIG_ZERO_CALL_USED_REGS is not set
 # end of Memory initialization
 # end of Kernel hardening options
 # end of Security options
 
-CONFIG_XOR_BLOCKS=m
+CONFIG_XOR_BLOCKS=y
 CONFIG_ASYNC_CORE=m
 CONFIG_ASYNC_MEMCPY=m
 CONFIG_ASYNC_XOR=m
@@ -8911,7 +9087,6 @@ CONFIG_CRYPTO_PCRYPT=m
 CONFIG_CRYPTO_CRYPTD=y
 CONFIG_CRYPTO_AUTHENC=m
 # CONFIG_CRYPTO_TEST is not set
-CONFIG_CRYPTO_SIMD=y
 CONFIG_CRYPTO_ENGINE=y
 
 #
@@ -9038,26 +9213,6 @@ CONFIG_CRYPTO_USER_API_AEAD=y
 CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
 # CONFIG_CRYPTO_STATS is not set
 CONFIG_CRYPTO_HASH_INFO=y
-
-#
-# Crypto library routines
-#
-CONFIG_CRYPTO_LIB_AES=y
-CONFIG_CRYPTO_LIB_ARC4=m
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m
-CONFIG_CRYPTO_LIB_BLAKE2S=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
-CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
-CONFIG_CRYPTO_LIB_CHACHA=m
-CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
-CONFIG_CRYPTO_LIB_CURVE25519=m
-CONFIG_CRYPTO_LIB_DES=m
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
-CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
-CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305=m
-CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
-CONFIG_CRYPTO_LIB_SHA256=y
 CONFIG_CRYPTO_HW=y
 CONFIG_CRYPTO_DEV_ALLWINNER=y
 # CONFIG_CRYPTO_DEV_SUN4I_SS is not set
@@ -9136,7 +9291,6 @@ CONFIG_HAVE_ARCH_BITREVERSE=y
 CONFIG_GENERIC_STRNCPY_FROM_USER=y
 CONFIG_GENERIC_STRNLEN_USER=y
 CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
 CONFIG_CORDIC=m
 # CONFIG_PRIME_NUMBERS is not set
 CONFIG_RATIONAL=y
@@ -9145,6 +9299,28 @@ CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
 CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
 CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
 # CONFIG_INDIRECT_PIO is not set
+
+#
+# Crypto library routines
+#
+CONFIG_CRYPTO_LIB_AES=y
+CONFIG_CRYPTO_LIB_ARC4=m
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
+CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
+CONFIG_CRYPTO_LIB_CHACHA=m
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
+CONFIG_CRYPTO_LIB_CURVE25519=m
+CONFIG_CRYPTO_LIB_DES=m
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
+CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
+CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
+CONFIG_CRYPTO_LIB_POLY1305=m
+CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_SM4=y
+# end of Crypto library routines
+
 CONFIG_CRC_CCITT=y
 CONFIG_CRC16=y
 CONFIG_CRC_T10DIF=y
@@ -9183,6 +9359,7 @@ CONFIG_XZ_DEC=y
 CONFIG_XZ_DEC_ARM=y
 CONFIG_XZ_DEC_ARMTHUMB=y
 # CONFIG_XZ_DEC_SPARC is not set
+# CONFIG_XZ_DEC_MICROLZMA is not set
 CONFIG_XZ_DEC_BCJ=y
 # CONFIG_XZ_DEC_TEST is not set
 CONFIG_DECOMPRESS_GZIP=y
@@ -9218,6 +9395,7 @@ CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
 CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
 CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
 CONFIG_SWIOTLB=y
+# CONFIG_DMA_RESTRICTED_POOL is not set
 CONFIG_DMA_NONCOHERENT_MMAP=y
 CONFIG_DMA_COHERENT_POOL=y
 CONFIG_DMA_REMAP=y
@@ -9324,12 +9502,22 @@ CONFIG_KGDB_TESTS=y
 # CONFIG_KGDB_KDB is not set
 CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
 # CONFIG_UBSAN is not set
+CONFIG_HAVE_ARCH_KCSAN=y
+CONFIG_HAVE_KCSAN_COMPILER=y
+# CONFIG_KCSAN is not set
 # end of Generic Kernel Debugging Instruments
 
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_MISC=y
 
 #
+# Networking Debugging
+#
+# CONFIG_NET_DEV_REFCNT_TRACKER is not set
+# CONFIG_NET_NS_REFCNT_TRACKER is not set
+# end of Networking Debugging
+
+#
 # Memory Debugging
 #
 # CONFIG_PAGE_EXTENSION is not set
@@ -9363,6 +9551,7 @@ CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y
 CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y
 CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
 CONFIG_CC_HAS_KASAN_GENERIC=y
+CONFIG_CC_HAS_KASAN_SW_TAGS=y
 CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
 # CONFIG_KASAN is not set
 CONFIG_HAVE_ARCH_KFENCE=y
@@ -9449,7 +9638,6 @@ CONFIG_RCU_CPU_STALL_TIMEOUT=60
 # end of RCU Debugging
 
 # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
 # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
 # CONFIG_LATENCYTOP is not set
 CONFIG_HAVE_FUNCTION_TRACER=y
@@ -9482,7 +9670,6 @@ CONFIG_FUNCTION_ERROR_INJECTION=y
 # CONFIG_FAULT_INJECTION is not set
 CONFIG_ARCH_HAS_KCOV=y
 CONFIG_CC_HAS_SANCOV_TRACE_PC=y
-# CONFIG_KCOV is not set
 # CONFIG_RUNTIME_TESTING_MENU is not set
 CONFIG_ARCH_USE_MEMTEST=y
 # CONFIG_MEMTEST is not set
diff --git a/drv-media-cedrus-10-bit-HEVC-support.patch b/drv-media-cedrus-10-bit-HEVC-support.patch
new file mode 100644
index 000000000000..99a921ef9a6c
--- /dev/null
+++ b/drv-media-cedrus-10-bit-HEVC-support.patch
@@ -0,0 +1,170 @@
+From 649d9696074a8446bda17be77b2277e72be2c2eb Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Sun, 15 Mar 2020 21:35:39 +0100
+Subject: [PATCH 056/101] drv:media:cedrus: 10-bit HEVC support
+
+WIp: 10-bit HEVC support
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+---
+ drivers/staging/media/sunxi/cedrus/cedrus.c   |  4 +--
+ .../staging/media/sunxi/cedrus/cedrus_h265.c  | 12 ++++++++
+ .../staging/media/sunxi/cedrus/cedrus_regs.h  |  4 +++
+ .../staging/media/sunxi/cedrus/cedrus_video.c | 30 +++++++++++++++----
+ .../staging/media/sunxi/cedrus/cedrus_video.h |  2 +-
+ 5 files changed, 44 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c
+index 314afde91..180fa9cee 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus.c
++++ b/drivers/staging/media/sunxi/cedrus/cedrus.c
+@@ -336,7 +336,7 @@ static int cedrus_open(struct file *file)
+ 		goto err_ctrls;
+ 	}
+ 	ctx->dst_fmt.pixelformat = V4L2_PIX_FMT_NV12_32L32;
+-	cedrus_prepare_format(&ctx->dst_fmt);
++	cedrus_prepare_format(&ctx->dst_fmt, 0);
+ 	ctx->src_fmt.pixelformat = V4L2_PIX_FMT_MPEG2_SLICE;
+ 	/*
+ 	 * TILED_NV12 has more strict requirements, so copy the width and
+@@ -344,7 +344,7 @@ static int cedrus_open(struct file *file)
+ 	 */
+ 	ctx->src_fmt.width = ctx->dst_fmt.width;
+ 	ctx->src_fmt.height = ctx->dst_fmt.height;
+-	cedrus_prepare_format(&ctx->src_fmt);
++	cedrus_prepare_format(&ctx->src_fmt, 0);
+ 
+ 	v4l2_fh_add(&ctx->fh);
+ 
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
+index 3d7f87a80..7caec0e57 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
++++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
+@@ -534,6 +534,18 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
+ 
+ 	cedrus_write(dev, VE_DEC_H265_DEC_PCM_CTRL, reg);
+ 
++	if (sps->bit_depth_luma_minus8 == 2) {
++		unsigned int size;
++
++		size = ALIGN(ctx->src_fmt.width, 16) * ALIGN(ctx->src_fmt.height, 16);
++
++		reg = (size * 3) / 2;
++		cedrus_write(dev, VE_DEC_H265_OFFSET_ADDR_FIRST_OUT, reg);
++
++		reg = DIV_ROUND_UP(ctx->src_fmt.width, 4);
++		cedrus_write(dev, VE_DEC_H265_10BIT_CONFIGURE, ALIGN(reg, 32));
++	}
++
+ 	/* PPS. */
+ 
+ 	reg = VE_DEC_H265_DEC_PPS_CTRL0_PPS_CR_QP_OFFSET(pps->pps_cr_qp_offset) |
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h
+index bdb062ad8..7ab3a2b0a 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h
++++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h
+@@ -499,6 +499,10 @@
+ 
+ #define VE_DEC_H265_LOW_ADDR			(VE_ENGINE_DEC_H265 + 0x80)
+ 
++#define VE_DEC_H265_OFFSET_ADDR_FIRST_OUT	(VE_ENGINE_DEC_H265 + 0x84)
++#define VE_DEC_H265_OFFSET_ADDR_SECOND_OUT	(VE_ENGINE_DEC_H265 + 0x88)
++#define VE_DEC_H265_10BIT_CONFIGURE		(VE_ENGINE_DEC_H265 + 0x8c)
++
+ #define VE_DEC_H265_LOW_ADDR_PRIMARY_CHROMA(a) \
+ 	SHIFT_AND_MASK_BITS(a, 31, 24)
+ #define VE_DEC_H265_LOW_ADDR_SECONDARY_CHROMA(a) \
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c
+index 80e33775b..247377138 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c
++++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c
+@@ -100,7 +100,7 @@ static struct cedrus_format *cedrus_find_format(u32 pixelformat, u32 directions,
+ 	return &cedrus_formats[i];
+ }
+ 
+-void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt)
++void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt, int extended)
+ {
+ 	unsigned int width = pix_fmt->width;
+ 	unsigned int height = pix_fmt->height;
+@@ -155,6 +155,17 @@ void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt)
+ 		break;
+ 	}
+ 
++	if (extended) {
++		unsigned int extra_size;
++
++		extra_size = DIV_ROUND_UP(pix_fmt->width, 4);
++		extra_size = ALIGN(extra_size, 32);
++		extra_size *= ALIGN(pix_fmt->height, 16) * 3;
++		extra_size /= 2;
++
++		sizeimage += extra_size;
++	}
++
+ 	pix_fmt->width = width;
+ 	pix_fmt->height = height;
+ 
+@@ -247,17 +258,27 @@ static int cedrus_try_fmt_vid_cap(struct file *file, void *priv,
+ 	struct cedrus_ctx *ctx = cedrus_file2ctx(file);
+ 	struct cedrus_dev *dev = ctx->dev;
+ 	struct v4l2_pix_format *pix_fmt = &f->fmt.pix;
++	const struct v4l2_ctrl_hevc_sps *sps;
+ 	struct cedrus_format *fmt =
+ 		cedrus_find_format(pix_fmt->pixelformat, CEDRUS_DECODE_DST,
+ 				   dev->capabilities);
++	int extended;
+ 
+ 	if (!fmt)
+ 		return -EINVAL;
+ 
++	sps = cedrus_find_control_data(ctx, V4L2_CID_MPEG_VIDEO_HEVC_SPS);
++
++	/* The 10-bitHEVC decoder needs extra size on the output buffer. */
++	extended = ctx->src_fmt.pixelformat == V4L2_PIX_FMT_HEVC_SLICE &&
++	sps->bit_depth_luma_minus8 == 2;
++
+ 	pix_fmt->pixelformat = fmt->pixelformat;
+ 	pix_fmt->width = ctx->src_fmt.width;
+ 	pix_fmt->height = ctx->src_fmt.height;
+-	cedrus_prepare_format(pix_fmt);
++
++	pix_fmt->pixelformat = fmt->pixelformat;
++	cedrus_prepare_format(pix_fmt, extended);
+ 
+ 	return 0;
+ }
+@@ -275,8 +296,7 @@ static int cedrus_try_fmt_vid_out(struct file *file, void *priv,
+ 	if (!fmt)
+ 		return -EINVAL;
+ 
+-	pix_fmt->pixelformat = fmt->pixelformat;
+-	cedrus_prepare_format(pix_fmt);
++	cedrus_prepare_format(pix_fmt, 0);
+ 
+ 	return 0;
+ }
+@@ -357,7 +377,7 @@ static int cedrus_s_fmt_vid_out(struct file *file, void *priv,
+ 	ctx->dst_fmt.quantization = f->fmt.pix.quantization;
+ 	ctx->dst_fmt.width = ctx->src_fmt.width;
+ 	ctx->dst_fmt.height = ctx->src_fmt.height;
+-	cedrus_prepare_format(&ctx->dst_fmt);
++	cedrus_prepare_format(&ctx->dst_fmt, 0);
+ 
+ 	return 0;
+ }
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.h b/drivers/staging/media/sunxi/cedrus/cedrus_video.h
+index 05050c0a0..d42e4ebf6 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus_video.h
++++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.h
+@@ -26,6 +26,6 @@ extern const struct v4l2_ioctl_ops cedrus_ioctl_ops;
+ 
+ int cedrus_queue_init(void *priv, struct vb2_queue *src_vq,
+ 		      struct vb2_queue *dst_vq);
+-void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt);
++void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt, int extended);
+ 
+ #endif
+-- 
+2.31.1
+
diff --git a/drv-media-cedrus-Add-callback-for-buffer-cleanup.patch b/drv-media-cedrus-Add-callback-for-buffer-cleanup.patch
new file mode 100644
index 000000000000..8b2b588f9461
--- /dev/null
+++ b/drv-media-cedrus-Add-callback-for-buffer-cleanup.patch
@@ -0,0 +1,57 @@
+From 93b5b1670e96f2a3a8dd1d5a9ac9d2b38c295917 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Sat, 9 Nov 2019 13:06:15 +0100
+Subject: [PATCH 048/101] drv:media: cedrus: Add callback for buffer cleanup
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+---
+ drivers/staging/media/sunxi/cedrus/cedrus.h       |  1 +
+ drivers/staging/media/sunxi/cedrus/cedrus_video.c | 13 +++++++++++++
+ 2 files changed, 14 insertions(+)
+
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h
+index c790963ef..35faf42f2 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus.h
++++ b/drivers/staging/media/sunxi/cedrus/cedrus.h
+@@ -166,6 +166,7 @@ struct cedrus_dec_ops {
+ 	int (*start)(struct cedrus_ctx *ctx);
+ 	void (*stop)(struct cedrus_ctx *ctx);
+ 	void (*trigger)(struct cedrus_ctx *ctx);
++	void (*buf_cleanup)(struct cedrus_ctx *ctx, struct cedrus_buffer *buf);
+ };
+ 
+ struct cedrus_variant {
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c
+index 6e1486987..80e33775b 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c
++++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c
+@@ -469,6 +469,18 @@ static int cedrus_buf_prepare(struct vb2_buffer *vb)
+ 	return 0;
+ }
+ 
++static void cedrus_buf_cleanup(struct vb2_buffer *vb)
++{
++	struct vb2_queue *vq = vb->vb2_queue;
++	struct cedrus_ctx *ctx = vb2_get_drv_priv(vq);
++	struct cedrus_dev *dev = ctx->dev;
++	struct cedrus_dec_ops *ops = dev->dec_ops[ctx->current_codec];
++
++	if (!V4L2_TYPE_IS_OUTPUT(vq->type) && ops->buf_cleanup)
++		ops->buf_cleanup(ctx,
++				 vb2_to_cedrus_buffer(vq->bufs[vb->index]));
++}
++
+ static int cedrus_start_streaming(struct vb2_queue *vq, unsigned int count)
+ {
+ 	struct cedrus_ctx *ctx = vb2_get_drv_priv(vq);
+@@ -551,6 +563,7 @@ static void cedrus_buf_request_complete(struct vb2_buffer *vb)
+ static struct vb2_ops cedrus_qops = {
+ 	.queue_setup		= cedrus_queue_setup,
+ 	.buf_prepare		= cedrus_buf_prepare,
++	.buf_cleanup		= cedrus_buf_cleanup,
+ 	.buf_queue		= cedrus_buf_queue,
+ 	.buf_out_validate	= cedrus_buf_out_validate,
+ 	.buf_request_complete	= cedrus_buf_request_complete,
+-- 
+2.31.1
+
diff --git a/drv-media-cedrus-h264-Improve-buffer-management.patch b/drv-media-cedrus-h264-Improve-buffer-management.patch
new file mode 100644
index 000000000000..5e8ae2e1db25
--- /dev/null
+++ b/drv-media-cedrus-h264-Improve-buffer-management.patch
@@ -0,0 +1,208 @@
+From eb94bf33cc1b37231063703c691c4b460481df7a Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Sat, 9 Nov 2019 14:12:42 +0100
+Subject: [PATCH 051/101] drv:media: cedrus: h264: Improve buffer management
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+---
+ drivers/staging/media/sunxi/cedrus/cedrus.h   |  3 +
+ .../staging/media/sunxi/cedrus/cedrus_h264.c  | 95 ++++++++-----------
+ 2 files changed, 44 insertions(+), 54 deletions(-)
+
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h
+index 54a860ec7..25079901a 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus.h
++++ b/drivers/staging/media/sunxi/cedrus/cedrus.h
+@@ -105,6 +105,9 @@ struct cedrus_buffer {
+ 		struct {
+ 			unsigned int			position;
+ 			enum cedrus_h264_pic_type	pic_type;
++			void		*mv_col_buf;
++			dma_addr_t	mv_col_buf_dma;
++			ssize_t		mv_col_buf_size;
+ 		} h264;
+ 		struct {
+ 			void		*mv_col_buf;
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c
+index b4173a892..787c1575c 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c
++++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c
+@@ -55,16 +55,14 @@ static void cedrus_h264_write_sram(struct cedrus_dev *dev,
+ }
+ 
+ static dma_addr_t cedrus_h264_mv_col_buf_addr(struct cedrus_ctx *ctx,
+-					      unsigned int position,
++					      struct cedrus_buffer *buf,
+ 					      unsigned int field)
+ {
+-	dma_addr_t addr = ctx->codec.h264.mv_col_buf_dma;
+-
+-	/* Adjust for the position */
+-	addr += position * ctx->codec.h264.mv_col_buf_field_size * 2;
++	dma_addr_t addr = buf->codec.h264.mv_col_buf_dma;
+ 
+ 	/* Adjust for the field */
+-	addr += field * ctx->codec.h264.mv_col_buf_field_size;
++	if (field)
++		addr += buf->codec.h264.mv_col_buf_size / 2;
+ 
+ 	return addr;
+ }
+@@ -76,7 +74,6 @@ static void cedrus_fill_ref_pic(struct cedrus_ctx *ctx,
+ 				struct cedrus_h264_sram_ref_pic *pic)
+ {
+ 	struct vb2_buffer *vbuf = &buf->m2m_buf.vb.vb2_buf;
+-	unsigned int position = buf->codec.h264.position;
+ 
+ 	pic->top_field_order_cnt = cpu_to_le32(top_field_order_cnt);
+ 	pic->bottom_field_order_cnt = cpu_to_le32(bottom_field_order_cnt);
+@@ -85,9 +82,9 @@ static void cedrus_fill_ref_pic(struct cedrus_ctx *ctx,
+ 	pic->luma_ptr = cpu_to_le32(cedrus_buf_addr(vbuf, &ctx->dst_fmt, 0));
+ 	pic->chroma_ptr = cpu_to_le32(cedrus_buf_addr(vbuf, &ctx->dst_fmt, 1));
+ 	pic->mv_col_top_ptr =
+-		cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, position, 0));
++		cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, buf, 0));
+ 	pic->mv_col_bot_ptr =
+-		cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, position, 1));
++		cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, buf, 1));
+ }
+ 
+ static void cedrus_write_frame_list(struct cedrus_ctx *ctx,
+@@ -146,6 +143,28 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx,
+ 	output_buf = vb2_to_cedrus_buffer(&run->dst->vb2_buf);
+ 	output_buf->codec.h264.position = position;
+ 
++	if (!output_buf->codec.h264.mv_col_buf_size) {
++		const struct v4l2_ctrl_h264_sps *sps = run->h264.sps;
++		unsigned int field_size;
++
++		field_size = DIV_ROUND_UP(ctx->src_fmt.width, 16) *
++			DIV_ROUND_UP(ctx->src_fmt.height, 16) * 16;
++		if (!(sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE))
++			field_size = field_size * 2;
++		if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY))
++			field_size = field_size * 2;
++
++		output_buf->codec.h264.mv_col_buf_size = field_size * 2;
++		output_buf->codec.h264.mv_col_buf =
++			dma_alloc_attrs(dev->dev,
++					output_buf->codec.h264.mv_col_buf_size,
++					&output_buf->codec.h264.mv_col_buf_dma,
++					GFP_KERNEL, DMA_ATTR_NO_KERNEL_MAPPING);
++
++		if (!output_buf->codec.h264.mv_col_buf)
++			output_buf->codec.h264.mv_col_buf_size = 0;
++	}
++
+ 	if (decode->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC)
+ 		output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_FIELD;
+ 	else if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)
+@@ -516,8 +535,6 @@ static int cedrus_h264_start(struct cedrus_ctx *ctx)
+ {
+ 	struct cedrus_dev *dev = ctx->dev;
+ 	unsigned int pic_info_size;
+-	unsigned int field_size;
+-	unsigned int mv_col_size;
+ 	int ret;
+ 
+ 	/*
+@@ -565,38 +582,6 @@ static int cedrus_h264_start(struct cedrus_ctx *ctx)
+ 		goto err_pic_buf;
+ 	}
+ 
+-	field_size = DIV_ROUND_UP(ctx->src_fmt.width, 16) *
+-		DIV_ROUND_UP(ctx->src_fmt.height, 16) * 16;
+-
+-	/*
+-	 * FIXME: This is actually conditional to
+-	 * V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE not being set, we
+-	 * might have to rework this if memory efficiency ever is
+-	 * something we need to work on.
+-	 */
+-	field_size = field_size * 2;
+-
+-	/*
+-	 * FIXME: This is actually conditional to
+-	 * V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY not being set, we might
+-	 * have to rework this if memory efficiency ever is something
+-	 * we need to work on.
+-	 */
+-	field_size = field_size * 2;
+-	ctx->codec.h264.mv_col_buf_field_size = field_size;
+-
+-	mv_col_size = field_size * 2 * CEDRUS_H264_FRAME_NUM;
+-	ctx->codec.h264.mv_col_buf_size = mv_col_size;
+-	ctx->codec.h264.mv_col_buf =
+-		dma_alloc_attrs(dev->dev,
+-				ctx->codec.h264.mv_col_buf_size,
+-				&ctx->codec.h264.mv_col_buf_dma,
+-				GFP_KERNEL, DMA_ATTR_NO_KERNEL_MAPPING);
+-	if (!ctx->codec.h264.mv_col_buf) {
+-		ret = -ENOMEM;
+-		goto err_neighbor_buf;
+-	}
+-
+ 	if (ctx->src_fmt.width > 2048) {
+ 		/*
+ 		 * Formulas for deblock and intra prediction buffer sizes
+@@ -612,7 +597,7 @@ static int cedrus_h264_start(struct cedrus_ctx *ctx)
+ 					GFP_KERNEL, DMA_ATTR_NO_KERNEL_MAPPING);
+ 		if (!ctx->codec.h264.deblk_buf) {
+ 			ret = -ENOMEM;
+-			goto err_mv_col_buf;
++			goto err_neighbor_buf;
+ 		}
+ 
+ 		/*
+@@ -640,12 +625,6 @@ static int cedrus_h264_start(struct cedrus_ctx *ctx)
+ 		       ctx->codec.h264.deblk_buf_dma,
+ 		       DMA_ATTR_NO_KERNEL_MAPPING);
+ 
+-err_mv_col_buf:
+-	dma_free_attrs(dev->dev, ctx->codec.h264.mv_col_buf_size,
+-		       ctx->codec.h264.mv_col_buf,
+-		       ctx->codec.h264.mv_col_buf_dma,
+-		       DMA_ATTR_NO_KERNEL_MAPPING);
+-
+ err_neighbor_buf:
+ 	dma_free_attrs(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE,
+ 		       ctx->codec.h264.neighbor_info_buf,
+@@ -664,10 +643,6 @@ static void cedrus_h264_stop(struct cedrus_ctx *ctx)
+ {
+ 	struct cedrus_dev *dev = ctx->dev;
+ 
+-	dma_free_attrs(dev->dev, ctx->codec.h264.mv_col_buf_size,
+-		       ctx->codec.h264.mv_col_buf,
+-		       ctx->codec.h264.mv_col_buf_dma,
+-		       DMA_ATTR_NO_KERNEL_MAPPING);
+ 	dma_free_attrs(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE,
+ 		       ctx->codec.h264.neighbor_info_buf,
+ 		       ctx->codec.h264.neighbor_info_buf_dma,
+@@ -696,6 +671,17 @@ static void cedrus_h264_trigger(struct cedrus_ctx *ctx)
+ 		     VE_H264_TRIGGER_TYPE_AVC_SLICE_DECODE);
+ }
+ 
++static void cedrus_h264_buf_cleanup(struct cedrus_ctx *ctx,
++				    struct cedrus_buffer *buf)
++{
++	if (buf->codec.h264.mv_col_buf_size)
++		dma_free_attrs(ctx->dev->dev,
++			       buf->codec.h264.mv_col_buf_size,
++			       buf->codec.h264.mv_col_buf,
++			       buf->codec.h264.mv_col_buf_dma,
++			       DMA_ATTR_NO_KERNEL_MAPPING);
++}
++
+ struct cedrus_dec_ops cedrus_dec_ops_h264 = {
+ 	.irq_clear	= cedrus_h264_irq_clear,
+ 	.irq_disable	= cedrus_h264_irq_disable,
+@@ -704,4 +690,5 @@ struct cedrus_dec_ops cedrus_dec_ops_h264 = {
+ 	.start		= cedrus_h264_start,
+ 	.stop		= cedrus_h264_stop,
+ 	.trigger	= cedrus_h264_trigger,
++	.buf_cleanup	= cedrus_h264_buf_cleanup,
+ };
+-- 
+2.31.1
+
+
diff --git a/drv-media-cedrus-hevc-Improve-buffer-management.patch b/drv-media-cedrus-hevc-Improve-buffer-management.patch
new file mode 100644
index 000000000000..42ccc693d012
--- /dev/null
+++ b/drv-media-cedrus-hevc-Improve-buffer-management.patch
@@ -0,0 +1,245 @@
+From e5464070b7b15a21dc9bc133734f95a45d0c58e4 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Sat, 9 Nov 2019 13:22:05 +0100
+Subject: [PATCH 049/101] drv:media:cedrus: hevc: Improve buffer management
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+---
+ drivers/staging/media/sunxi/cedrus/cedrus.h   |   9 +-
+ .../staging/media/sunxi/cedrus/cedrus_h265.c  | 119 ++++++++++--------
+ 2 files changed, 70 insertions(+), 58 deletions(-)
+
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h
+index 35faf42f2..6ddcff8f5 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus.h
++++ b/drivers/staging/media/sunxi/cedrus/cedrus.h
+@@ -106,6 +106,11 @@ struct cedrus_buffer {
+ 			unsigned int			position;
+ 			enum cedrus_h264_pic_type	pic_type;
+ 		} h264;
++		struct {
++			void		*mv_col_buf;
++			dma_addr_t	mv_col_buf_dma;
++			ssize_t		mv_col_buf_size;
++		} h265;
+ 	} codec;
+ };
+ 
+@@ -139,10 +144,6 @@ struct cedrus_ctx {
+ 			ssize_t		intra_pred_buf_size;
+ 		} h264;
+ 		struct {
+-			void		*mv_col_buf;
+-			dma_addr_t	mv_col_buf_addr;
+-			ssize_t		mv_col_buf_size;
+-			ssize_t		mv_col_buf_unit_size;
+ 			void		*neighbor_info_buf;
+ 			dma_addr_t	neighbor_info_buf_addr;
+ 			void		*entry_points_buf;
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
+index 4fa5016a2..3d7f87a80 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
++++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
+@@ -91,26 +91,66 @@ static void cedrus_h265_sram_write_data(struct cedrus_dev *dev, void *data,
+ 
+ static inline dma_addr_t
+ cedrus_h265_frame_info_mv_col_buf_addr(struct cedrus_ctx *ctx,
+-				       unsigned int index, unsigned int field)
++				       unsigned int index,
++				       const struct v4l2_ctrl_hevc_sps *sps)
+ {
+-	return ctx->codec.h265.mv_col_buf_addr + index *
+-	       ctx->codec.h265.mv_col_buf_unit_size +
+-	       field * ctx->codec.h265.mv_col_buf_unit_size / 2;
++	struct cedrus_buffer *cedrus_buf = NULL;
++	struct vb2_buffer *buf = NULL;
++	struct vb2_queue *vq;
++
++	vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
++	if (vq)
++		buf = vb2_get_buffer(vq, index);
++
++	if (buf)
++		cedrus_buf = vb2_to_cedrus_buffer(buf);
++
++	if (!cedrus_buf)
++		return 0;
++
++	if (!cedrus_buf->codec.h265.mv_col_buf_size) {
++		unsigned int ctb_size_luma, width_in_ctb_luma;
++		unsigned int log2_max_luma_coding_block_size;
++
++		log2_max_luma_coding_block_size =
++			sps->log2_min_luma_coding_block_size_minus3 + 3 +
++			sps->log2_diff_max_min_luma_coding_block_size;
++		ctb_size_luma = 1 << log2_max_luma_coding_block_size;
++		width_in_ctb_luma = DIV_ROUND_UP(sps->pic_width_in_luma_samples,
++						 ctb_size_luma);
++
++		cedrus_buf->codec.h265.mv_col_buf_size = ALIGN(width_in_ctb_luma *
++			DIV_ROUND_UP(sps->pic_height_in_luma_samples, ctb_size_luma) *
++			CEDRUS_H265_MV_COL_BUF_UNIT_CTB_SIZE, 1024);
++
++		cedrus_buf->codec.h265.mv_col_buf =
++			dma_alloc_attrs(ctx->dev->dev,
++					cedrus_buf->codec.h265.mv_col_buf_size,
++					&cedrus_buf->codec.h265.mv_col_buf_dma,
++					GFP_KERNEL, DMA_ATTR_NO_KERNEL_MAPPING);
++
++		if (!cedrus_buf->codec.h265.mv_col_buf) {
++			cedrus_buf->codec.h265.mv_col_buf_size = 0;
++			cedrus_buf->codec.h265.mv_col_buf_dma = 0;
++		}
++	}
++
++	return cedrus_buf->codec.h265.mv_col_buf_dma;
+ }
+ 
+ static void cedrus_h265_frame_info_write_single(struct cedrus_ctx *ctx,
+ 						unsigned int index,
+ 						bool field_pic,
+ 						u32 pic_order_cnt[],
+-						int buffer_index)
++						int buffer_index,
++						const struct v4l2_ctrl_hevc_sps *sps)
+ {
+ 	struct cedrus_dev *dev = ctx->dev;
+ 	dma_addr_t dst_luma_addr = cedrus_dst_buf_addr(ctx, buffer_index, 0);
+ 	dma_addr_t dst_chroma_addr = cedrus_dst_buf_addr(ctx, buffer_index, 1);
+ 	dma_addr_t mv_col_buf_addr[2] = {
+-		cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index, 0),
+-		cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index,
+-						       field_pic ? 1 : 0)
++		cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index, sps),
++		cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index, sps)
+ 	};
+ 	u32 offset = VE_DEC_H265_SRAM_OFFSET_FRAME_INFO +
+ 		     VE_DEC_H265_SRAM_OFFSET_FRAME_INFO_UNIT * index;
+@@ -134,7 +174,8 @@ static void cedrus_h265_frame_info_write_single(struct cedrus_ctx *ctx,
+ 
+ static void cedrus_h265_frame_info_write_dpb(struct cedrus_ctx *ctx,
+ 					     const struct v4l2_hevc_dpb_entry *dpb,
+-					     u8 num_active_dpb_entries)
++					     u8 num_active_dpb_entries,
++					     const struct v4l2_ctrl_hevc_sps *sps)
+ {
+ 	struct vb2_queue *vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx,
+ 					       V4L2_BUF_TYPE_VIDEO_CAPTURE);
+@@ -149,7 +190,7 @@ static void cedrus_h265_frame_info_write_dpb(struct cedrus_ctx *ctx,
+ 
+ 		cedrus_h265_frame_info_write_single(ctx, i, dpb[i].field_pic,
+ 						    pic_order_cnt,
+-						    buffer_index);
++						    buffer_index, sps);
+ 	}
+ }
+ 
+@@ -388,37 +388,6 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
+ 	width_in_ctb_luma =
+ 		DIV_ROUND_UP(sps->pic_width_in_luma_samples, ctb_size_luma);
+ 
+-	/* MV column buffer size and allocation. */
+-	if (!ctx->codec.h265.mv_col_buf_size) {
+-		unsigned int num_buffers =
+-			run->dst->vb2_buf.vb2_queue->num_buffers;
+-
+-		/*
+-		 * Each CTB requires a MV col buffer with a specific unit size.
+-		 * Since the address is given with missing lsb bits, 1 KiB is
+-		 * added to each buffer to ensure proper alignment.
+-		 */
+-		ctx->codec.h265.mv_col_buf_unit_size =
+-			DIV_ROUND_UP(ctx->src_fmt.width, ctb_size_luma) *
+-			DIV_ROUND_UP(ctx->src_fmt.height, ctb_size_luma) *
+-			CEDRUS_H265_MV_COL_BUF_UNIT_CTB_SIZE + SZ_1K;
+-
+-		ctx->codec.h265.mv_col_buf_size = num_buffers *
+-			ctx->codec.h265.mv_col_buf_unit_size;
+-
+-		/* Buffer is never accessed by CPU, so we can skip kernel mapping. */
+-		ctx->codec.h265.mv_col_buf =
+-			dma_alloc_attrs(dev->dev,
+-					ctx->codec.h265.mv_col_buf_size,
+-					&ctx->codec.h265.mv_col_buf_addr,
+-					GFP_KERNEL, DMA_ATTR_NO_KERNEL_MAPPING);
+-		if (!ctx->codec.h265.mv_col_buf) {
+-			ctx->codec.h265.mv_col_buf_size = 0;
+-			// TODO: Abort the process here.
+-			return;
+-		}
+-	}
+-
+ 	/* Activate H265 engine. */
+ 	cedrus_engine_enable(ctx, CEDRUS_CODEC_H265);
+ 
+@@ -671,7 +682,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
+ 
+ 	/* Write decoded picture buffer in pic list. */
+ 	cedrus_h265_frame_info_write_dpb(ctx, decode_params->dpb,
+-					 decode_params->num_active_dpb_entries);
++					 decode_params->num_active_dpb_entries, sps);
+ 
+ 	/* Output frame. */
+ 
+@@ -682,7 +693,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
+ 	cedrus_h265_frame_info_write_single(ctx, output_pic_list_index,
+ 					    slice_params->pic_struct != 0,
+ 					    pic_order_cnt,
+-					    run->dst->vb2_buf.index);
++					    run->dst->vb2_buf.index, sps);
+ 
+ 	cedrus_write(dev, VE_DEC_H265_OUTPUT_FRAME_IDX, output_pic_list_index);
+ 
+@@ -732,9 +701,6 @@ static int cedrus_h265_start(struct cedrus_ctx *ctx)
+ {
+ 	struct cedrus_dev *dev = ctx->dev;
+ 
+-	/* The buffer size is calculated at setup time. */
+-	ctx->codec.h265.mv_col_buf_size = 0;
+-
+ 	/* Buffer is never accessed by CPU, so we can skip kernel mapping. */
+ 	ctx->codec.h265.neighbor_info_buf =
+ 		dma_alloc_attrs(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE,
+@@ -759,15 +767,6 @@ static void cedrus_h265_stop(struct cedrus_ctx *ctx)
+ {
+ 	struct cedrus_dev *dev = ctx->dev;
+ 
+-	if (ctx->codec.h265.mv_col_buf_size > 0) {
+-		dma_free_attrs(dev->dev, ctx->codec.h265.mv_col_buf_size,
+-			       ctx->codec.h265.mv_col_buf,
+-			       ctx->codec.h265.mv_col_buf_addr,
+-			       DMA_ATTR_NO_KERNEL_MAPPING);
+-
+-		ctx->codec.h265.mv_col_buf_size = 0;
+-	}
+-
+ 	dma_free_attrs(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE,
+ 		       ctx->codec.h265.neighbor_info_buf,
+ 		       ctx->codec.h265.neighbor_info_buf_addr,
+@@ -784,6 +783,17 @@ static void cedrus_h265_trigger(struct cedrus_ctx *ctx)
+ 	cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_DEC_SLICE);
+ }
+ 
++static void cedrus_h265_buf_cleanup(struct cedrus_ctx *ctx,
++				    struct cedrus_buffer *buf)
++{
++	if (buf->codec.h265.mv_col_buf_size)
++		dma_free_attrs(ctx->dev->dev,
++			       buf->codec.h265.mv_col_buf_size,
++			       buf->codec.h265.mv_col_buf,
++			       buf->codec.h265.mv_col_buf_dma,
++			       DMA_ATTR_NO_KERNEL_MAPPING);
++}
++
+ struct cedrus_dec_ops cedrus_dec_ops_h265 = {
+ 	.irq_clear	= cedrus_h265_irq_clear,
+ 	.irq_disable	= cedrus_h265_irq_disable,
+@@ -792,4 +802,5 @@ struct cedrus_dec_ops cedrus_dec_ops_h265 = {
+ 	.start		= cedrus_h265_start,
+ 	.stop		= cedrus_h265_stop,
+ 	.trigger	= cedrus_h265_trigger,
++	.buf_cleanup	= cedrus_h265_buf_cleanup,
+ };
+-- 
+2.31.1
+
diff --git a/drv-media-cedrus-hevc-tiles-hack.patch b/drv-media-cedrus-hevc-tiles-hack.patch
new file mode 100644
index 000000000000..7d1238b08c63
--- /dev/null
+++ b/drv-media-cedrus-hevc-tiles-hack.patch
@@ -0,0 +1,180 @@
+From 08ec2c0d449a9e91f9174b347bd3f560f50ca872 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Sat, 26 Oct 2019 21:23:55 +0200
+Subject: [PATCH 046/101] drv:media: cedrus: hevc: tiles hack
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+---
+ drivers/staging/media/sunxi/cedrus/cedrus.h   |  2 +
+ .../staging/media/sunxi/cedrus/cedrus_h265.c  | 93 +++++++++++++++++--
+ 2 files changed, 89 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h
+index 9c7bfd2b6..c790963ef 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus.h
++++ b/drivers/staging/media/sunxi/cedrus/cedrus.h
+@@ -144,6 +144,8 @@ struct cedrus_ctx {
+ 			ssize_t		mv_col_buf_unit_size;
+ 			void		*neighbor_info_buf;
+ 			dma_addr_t	neighbor_info_buf_addr;
++			void		*entry_points_buf;
++			dma_addr_t	entry_points_buf_addr;
+ 		} h265;
+ 		struct {
+ 			unsigned int	last_frame_p_type;
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
+index bb7eb5610..4fa5016a2 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
++++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
+@@ -301,6 +301,61 @@ static void cedrus_h265_write_scaling_list(struct cedrus_ctx *ctx,
+ 		}
+ }
+ 
++static void write_entry_point_list(struct cedrus_ctx *ctx,
++				   struct cedrus_run *run,
++				   unsigned int ctb_addr_x,
++				   unsigned int ctb_addr_y)
++{
++	const struct v4l2_ctrl_hevc_slice_params *slice_params;
++	const struct v4l2_ctrl_hevc_pps *pps;
++	struct cedrus_dev *dev = ctx->dev;
++	int i, x, tx, y, ty;
++	u32 *entry_points;
++
++	pps = run->h265.pps;
++	slice_params = run->h265.slice_params;
++
++	for (x = 0, tx = 0; tx < pps->num_tile_columns_minus1 + 1; tx++) {
++		if (x + pps->column_width_minus1[tx] + 1 > ctb_addr_x)
++			break;
++
++		x += pps->column_width_minus1[tx] + 1;
++	}
++
++	for (y = 0, ty = 0; ty < pps->num_tile_rows_minus1 + 1; ty++) {
++		if (y + pps->row_height_minus1[ty] + 1 > ctb_addr_y)
++			break;
++
++		y += pps->row_height_minus1[ty] + 1;
++	}
++
++	cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, (y << 16) | (x << 0));
++	cedrus_write(dev, VE_DEC_H265_TILE_END_CTB,
++		     ((y + pps->row_height_minus1[ty]) << 16) |
++		     ((x + pps->column_width_minus1[tx]) << 0));
++
++	entry_points = ctx->codec.h265.entry_points_buf;
++	if (pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED) {
++		for (i = 0; i < slice_params->num_entry_point_offsets; i++)
++			entry_points[i] = slice_params->entry_point_offset_minus1[i] + 1;
++	} else {
++		for (i = 0; i < slice_params->num_entry_point_offsets; i++) {
++			if (tx + 1 >= pps->num_tile_columns_minus1 + 1) {
++				x = 0;
++				tx = 0;
++				y += pps->row_height_minus1[ty++] + 1;
++			} else {
++				x += pps->column_width_minus1[tx++] + 1;
++			}
++
++			entry_points[i * 4 + 0] = slice_params->entry_point_offset_minus1[i] + 1;
++			entry_points[i * 4 + 1] = 0x0;
++			entry_points[i * 4 + 2] = (y << 16) | (x << 0);
++			entry_points[i * 4 + 3] = ((y + pps->row_height_minus1[ty]) << 16) | ((x + pps->column_width_minus1[tx]) << 0);
++		}
++	}
++}
++
+ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
+ 			      struct cedrus_run *run)
+ {
+@@ -312,6 +367,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
+ 	const struct v4l2_hevc_pred_weight_table *pred_weight_table;
+ 	unsigned int width_in_ctb_luma, ctb_size_luma;
+ 	unsigned int log2_max_luma_coding_block_size;
++	unsigned int ctb_addr_x, ctb_addr_y;
+ 	dma_addr_t src_buf_addr;
+ 	dma_addr_t src_buf_end_addr;
+ 	u32 chroma_log2_weight_denom;
+@@ -390,12 +446,19 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
+ 	cedrus_write(dev, VE_DEC_H265_BITS_END_ADDR, reg);
+ 
+ 	/* Coding tree block address */
+-	reg = VE_DEC_H265_DEC_CTB_ADDR_X(slice_params->slice_segment_addr % width_in_ctb_luma);
+-	reg |= VE_DEC_H265_DEC_CTB_ADDR_Y(slice_params->slice_segment_addr / width_in_ctb_luma);
++	ctb_addr_x = slice_params->slice_segment_addr % width_in_ctb_luma;
++	ctb_addr_y = slice_params->slice_segment_addr / width_in_ctb_luma;
++	reg = VE_DEC_H265_DEC_CTB_ADDR_X(ctb_addr_x);
++	reg |= VE_DEC_H265_DEC_CTB_ADDR_Y(ctb_addr_y);
+ 	cedrus_write(dev, VE_DEC_H265_DEC_CTB_ADDR, reg);
+ 
+-	cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, 0);
+-	cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, 0);
++	if ((pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) ||
++	    (pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED)) {
++		write_entry_point_list(ctx, run, ctb_addr_x, ctb_addr_y);
++	} else {
++		cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, 0);
++		cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, 0);
++	}
+ 
+ 	/* Clear the number of correctly-decoded coding tree blocks. */
+ 	if (ctx->fh.m2m_ctx->new_frame)
+@@ -499,7 +562,9 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
+ 				V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED,
+ 				pps->flags);
+ 
+-	/* TODO: VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TILES_ENABLED */
++	reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TILES_ENABLED,
++				V4L2_HEVC_PPS_FLAG_TILES_ENABLED,
++				pps->flags);
+ 
+ 	reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TRANSQUANT_BYPASS_ENABLED,
+ 				V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED,
+@@ -575,12 +640,14 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
+ 
+ 	chroma_log2_weight_denom = pred_weight_table->luma_log2_weight_denom +
+ 				   pred_weight_table->delta_chroma_log2_weight_denom;
+-	reg = VE_DEC_H265_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(0) |
++	reg = VE_DEC_H265_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(slice_params->num_entry_point_offsets) |
+ 	      VE_DEC_H265_DEC_SLICE_HDR_INFO2_CHROMA_LOG2_WEIGHT_DENOM(chroma_log2_weight_denom) |
+ 	      VE_DEC_H265_DEC_SLICE_HDR_INFO2_LUMA_LOG2_WEIGHT_DENOM(pred_weight_table->luma_log2_weight_denom);
+ 
+ 	cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO2, reg);
+ 
++	cedrus_write(dev, VE_DEC_H265_ENTRY_POINT_OFFSET_ADDR, ctx->codec.h265.entry_points_buf_addr >> 8);
++
+ 	/* Decoded picture size. */
+ 
+ 	reg = VE_DEC_H265_DEC_PIC_SIZE_WIDTH(ctx->src_fmt.width) |
+@@ -674,6 +741,17 @@ static int cedrus_h265_start(struct cedrus_ctx *ctx)
+ 	if (!ctx->codec.h265.neighbor_info_buf)
+ 		return -ENOMEM;
+ 
++	ctx->codec.h265.entry_points_buf =
++		dma_alloc_coherent(dev->dev, CEDRUS_H265_ENTRY_POINTS_BUF_SIZE,
++				   &ctx->codec.h265.entry_points_buf_addr,
++				   GFP_KERNEL);
++	if (!ctx->codec.h265.entry_points_buf) {
++		dma_free_coherent(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE,
++			          ctx->codec.h265.neighbor_info_buf,
++			          ctx->codec.h265.neighbor_info_buf_addr);
++		return -ENOMEM;
++	}
++
+ 	return 0;
+ }
+ 
+@@ -694,6 +772,9 @@ static void cedrus_h265_stop(struct cedrus_ctx *ctx)
+ 		       ctx->codec.h265.neighbor_info_buf,
+ 		       ctx->codec.h265.neighbor_info_buf_addr,
+ 		       DMA_ATTR_NO_KERNEL_MAPPING);
++	dma_free_coherent(dev->dev, CEDRUS_H265_ENTRY_POINTS_BUF_SIZE,
++		          ctx->codec.h265.entry_points_buf,
++		          ctx->codec.h265.entry_points_buf_addr);
+ }
+ 
+ static void cedrus_h265_trigger(struct cedrus_ctx *ctx)
+-- 
+2.31.1
+
diff --git a/0001-mfd-Add-support-for-AC200.patch b/drv-mfd-Add-support-for-AC200.patch
index f74e3c209c36..0a79ef9e9176 100644
--- a/0001-mfd-Add-support-for-AC200.patch
+++ b/drv-mfd-Add-support-for-AC200.patch
@@ -1,7 +1,7 @@
-From d98aa318aabd4aba05328f9c832b23bdf2e1677a Mon Sep 17 00:00:00 2001
+From 3e6411db1aa4dfe1d1a6d63c2cbed2c588d35aef Mon Sep 17 00:00:00 2001
 From: Jernej Skrabec <jernej.skrabec@siol.net>
 Date: Fri, 16 Aug 2019 16:38:21 +0200
-Subject: [PATCH 1/4] mfd: Add support for AC200
+Subject: [PATCH 006/101] drv:mfd: Add support for AC200
 
 Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
 ---
@@ -14,7 +14,7 @@ Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
  create mode 100644 include/linux/mfd/ac200.h
 
 diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
-index 420900852166..a45e7c88ac9b 100644
+index d2f345245..5b756e81b 100644
 --- a/drivers/mfd/Kconfig
 +++ b/drivers/mfd/Kconfig
 @@ -178,6 +178,15 @@ config MFD_AC100
@@ -22,7 +22,7 @@ index 420900852166..a45e7c88ac9b 100644
  	  components like codecs or RTC under the corresponding menus.
  
 +config MFD_AC200
-+	tristate "X-Powers AC200"
++	bool "X-Powers AC200"
 +	select MFD_CORE
 +	depends on I2C
 +	help
@@ -34,10 +34,10 @@ index 420900852166..a45e7c88ac9b 100644
  	tristate
  	select MFD_CORE
 diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
-index aed99f08739f..4431a4cf19ca 100644
+index 2ba6646e8..7edc825f9 100644
 --- a/drivers/mfd/Makefile
 +++ b/drivers/mfd/Makefile
-@@ -141,6 +141,7 @@ obj-$(CONFIG_MFD_DA9052_SPI)	+= da9052-spi.o
+@@ -142,6 +142,7 @@ obj-$(CONFIG_MFD_DA9052_SPI)	+= da9052-spi.o
  obj-$(CONFIG_MFD_DA9052_I2C)	+= da9052-i2c.o
  
  obj-$(CONFIG_MFD_AC100)		+= ac100.o
@@ -47,7 +47,7 @@ index aed99f08739f..4431a4cf19ca 100644
  obj-$(CONFIG_MFD_AXP20X_RSB)	+= axp20x-rsb.o
 diff --git a/drivers/mfd/ac200.c b/drivers/mfd/ac200.c
 new file mode 100644
-index 000000000000..570573790d91
+index 000000000..570573790
 --- /dev/null
 +++ b/drivers/mfd/ac200.c
 @@ -0,0 +1,170 @@
@@ -223,7 +223,7 @@ index 000000000000..570573790d91
 +MODULE_LICENSE("GPL v2");
 diff --git a/include/linux/mfd/ac200.h b/include/linux/mfd/ac200.h
 new file mode 100644
-index 000000000000..0c677094a5b3
+index 000000000..0c677094a
 --- /dev/null
 +++ b/include/linux/mfd/ac200.h
 @@ -0,0 +1,208 @@
@@ -436,5 +436,5 @@ index 000000000000..0c677094a5b3
 +
 +#endif /* __LINUX_MFD_AC200_H */
 -- 
-2.20.1
+2.31.1
 
diff --git a/0002-net-phy-Add-support-for-AC200-EPHY.patch b/drv-net-phy-Add-support-for-AC200-EPHY.patch
index ff87c895fb3d..f763bd4e2097 100644
--- a/0002-net-phy-Add-support-for-AC200-EPHY.patch
+++ b/drv-net-phy-Add-support-for-AC200-EPHY.patch
@@ -1,7 +1,7 @@
-From 1b528543ea41a9837d39e9ab621631c77122f1aa Mon Sep 17 00:00:00 2001
+From e0b1f9c0e3ca7fb234215eef9f643a8fb98a4d06 Mon Sep 17 00:00:00 2001
 From: Jernej Skrabec <jernej.skrabec@siol.net>
 Date: Fri, 16 Aug 2019 16:38:57 +0200
-Subject: [PATCH 2/4] net: phy: Add support for AC200 EPHY
+Subject: [PATCH 009/101] drv:net:phy: Add support for AC200 EPHY
 
 Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
 ---
@@ -12,12 +12,12 @@ Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
  create mode 100644 drivers/net/phy/ac200.c
 
 diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
-index 2e016271e126..248d9384091c 100644
+index 902495afc..056b7965d 100644
 --- a/drivers/net/phy/Kconfig
 +++ b/drivers/net/phy/Kconfig
-@@ -266,6 +266,13 @@ config ADIN_PHY
- 	  - ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
- 	    Ethernet PHY
+@@ -63,6 +63,13 @@ config SFP
+ 
+ comment "MII PHY device drivers"
  
 +config AC200_PHY
 +	tristate "AC200 EPHY"
@@ -28,12 +28,12 @@ index 2e016271e126..248d9384091c 100644
 +
  config AMD_PHY
  	tristate "AMD PHYs"
- 	---help---
+ 	help
 diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
-index fe5badf13b65..2143587f010e 100644
+index b2728d00f..dbaa8f29c 100644
 --- a/drivers/net/phy/Makefile
 +++ b/drivers/net/phy/Makefile
-@@ -49,6 +49,7 @@ obj-$(CONFIG_SFP)		+= sfp.o
+@@ -30,6 +30,7 @@ obj-$(CONFIG_SFP)		+= sfp.o
  sfp-obj-$(CONFIG_SFP)		+= sfp-bus.o
  obj-y				+= $(sfp-obj-y) $(sfp-obj-m)
  
@@ -43,7 +43,7 @@ index fe5badf13b65..2143587f010e 100644
  aquantia-objs			+= aquantia_main.o
 diff --git a/drivers/net/phy/ac200.c b/drivers/net/phy/ac200.c
 new file mode 100644
-index 000000000000..cb713188f7ec
+index 000000000..cb713188f
 --- /dev/null
 +++ b/drivers/net/phy/ac200.c
 @@ -0,0 +1,220 @@
@@ -268,5 +268,5 @@ index 000000000000..cb713188f7ec
 +MODULE_DESCRIPTION("AC200 Ethernet PHY driver");
 +MODULE_LICENSE("GPL");
 -- 
-2.20.1
+2.31.1
 
diff --git a/drv-pinctrl-sunxi-pinctrl-sun50i-h6.c-GPIO-disable_strict_mode.patch b/drv-pinctrl-sunxi-pinctrl-sun50i-h6.c-GPIO-disable_strict_mode.patch
new file mode 100644
index 000000000000..482b724462b6
--- /dev/null
+++ b/drv-pinctrl-sunxi-pinctrl-sun50i-h6.c-GPIO-disable_strict_mode.patch
@@ -0,0 +1,25 @@
+From f847d2c94b8345f73c5f9e7fa29cea96d2339234 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 1 Feb 2022 19:11:11 +0300
+Subject: [PATCH 02/50] drv:pinctrl:sunxi:pinctrl-sun50i-h6.c GPIO
+ disable_strict_mode
+
+---
+ drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
+index 3cc112158..1182cc864 100644
+--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
++++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
+@@ -588,6 +588,7 @@ static const unsigned int h6_irq_bank_map[] = { 1, 5, 6, 7 };
+ static const struct sunxi_pinctrl_desc h6_pinctrl_data = {
+ 	.pins = h6_pins,
+ 	.npins = ARRAY_SIZE(h6_pins),
++	.disable_strict_mode = true,
+ 	.irq_banks = 4,
+ 	.irq_bank_map = h6_irq_bank_map,
+ 	.irq_read_needs_mux = true,
+-- 
+2.34.1
+
diff --git a/fastgit_wget.sh b/fastgit_wget.sh
new file mode 100644
index 000000000000..b5e98acfd66b
--- /dev/null
+++ b/fastgit_wget.sh
@@ -0,0 +1,3 @@
+links=$(sed -e "s|github.com|raw.fastgit.org|g" -e "s|/blob||g" $1)
+echo $links
+wget -c -q $links
diff --git a/0004-net-stmmac-sun8i-Add-support-for-enabling-a-regulato.patch b/net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch
index a38543d319b9..a794b531a27e 100644
--- a/0004-net-stmmac-sun8i-Add-support-for-enabling-a-regulato.patch
+++ b/net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch
@@ -1,8 +1,8 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Ondrej Jirman <megous@megous.com>
+From 97d6eb56c5d765ef33016e08b92310c609c9c353 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
 Date: Tue, 20 Aug 2019 14:31:38 +0200
-Subject: [PATCH] net: stmmac: sun8i: Add support for enabling a regulator for
- PHY I/O pins
+Subject: [PATCH 072/456] net: stmmac: sun8i: Add support for enabling a
+ regulator for PHY I/O pins
 
 Orange Pi 3 has two regulators that power the Realtek RTL8211E. According
 to the phy datasheet, both regulators need to be enabled at the same time.
@@ -10,11 +10,13 @@ to the phy datasheet, both regulators need to be enabled at the same time.
 Add support for the second optional regulator, "phy-io", to the glue
 driver.
 
-Signed-off-by: Ondrej Jirman <megous@megous.com>
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
 ---
- .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 23 ++++++++++++++++++-
- 1 file changed, 22 insertions(+), 1 deletion(-)
+ .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 22 ++++++++++++++++++-
+ 1 file changed, 21 insertions(+), 1 deletion(-)
 
+diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+index b44f14c278ca..afa2a61d7ec8 100644
 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
 @@ -61,6 +61,8 @@ struct emac_variant {
@@ -34,7 +36,7 @@ Signed-off-by: Ondrej Jirman <megous@megous.com>
  	struct reset_control *rst_ephy;
  	const struct emac_variant *variant;
  	struct regmap_field *regmap_field;
-@@ -551,10 +554,16 @@ static int sun8i_dwmac_init(struct platf
+@@ -573,10 +576,16 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
  	struct sunxi_priv_data *gmac = priv;
  	int ret;
  
@@ -52,7 +54,7 @@ Signed-off-by: Ondrej Jirman <megous@megous.com>
  	}
  
  	ret = clk_prepare_enable(gmac->tx_clk);
-@@ -575,6 +584,8 @@ err_disable_clk:
+@@ -597,6 +606,8 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
  	clk_disable_unprepare(gmac->tx_clk);
  err_disable_regulator:
  	regulator_disable(gmac->regulator_phy);
@@ -61,7 +63,7 @@ Signed-off-by: Ondrej Jirman <megous@megous.com>
  
  	return ret;
  }
-@@ -1021,6 +1032,7 @@ static void sun8i_dwmac_exit(struct plat
+@@ -1045,6 +1056,7 @@ static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
  	clk_disable_unprepare(gmac->tx_clk);
  
  	regulator_disable(gmac->regulator_phy);
@@ -69,7 +71,7 @@ Signed-off-by: Ondrej Jirman <megous@megous.com>
  }
  
  static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable)
-@@ -1154,6 +1166,15 @@ static int sun8i_dwmac_probe(struct plat
+@@ -1179,6 +1191,14 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
  		return ret;
  	}
  
@@ -77,11 +79,13 @@ Signed-off-by: Ondrej Jirman <megous@megous.com>
 +	gmac->regulator_phy_io = devm_regulator_get(dev, "phy-io");
 +	if (IS_ERR(gmac->regulator_phy_io)) {
 +		ret = PTR_ERR(gmac->regulator_phy_io);
-+		if (ret != -EPROBE_DEFER)
-+			dev_err(dev, "Failed to get PHY I/O regulator (%d)\n", ret);
++		dev_err_probe(dev, ret, "Failed to get PHY I/O regulator\n");
 +		return ret;
 +	}
 +
  	/* The "GMAC clock control" register might be located in the
  	 * CCU address range (on the R40), or the system control address
  	 * range (on most other sun8i and later SoCs).
+-- 
+2.34.1
+
diff --git a/0003-net-stmmac-sun8i-Rename-PHY-regulator-variable-to-re.patch b/net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch
index 81132eb2b0ff..942157148d12 100644
--- a/0003-net-stmmac-sun8i-Rename-PHY-regulator-variable-to-re.patch
+++ b/net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch
@@ -1,17 +1,19 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Ondrej Jirman <megous@megous.com>
+From 93aeb9e1d803bae947d8a47ce90a1a57663ee0da Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
 Date: Tue, 20 Aug 2019 14:29:29 +0200
-Subject: [PATCH] net: stmmac: sun8i: Rename PHY regulator variable to
+Subject: [PATCH 070/456] net: stmmac: sun8i: Rename PHY regulator variable to
  regulator_phy
 
 We'll be adding further optional regulators, and this makes it clearer
 what the regulator is for.
 
-Signed-off-by: Ondrej Jirman <megous@megous.com>
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
 ---
- .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 39 +++++++++----------
- 1 file changed, 19 insertions(+), 20 deletions(-)
+ .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 40 +++++++++----------
+ 1 file changed, 20 insertions(+), 20 deletions(-)
 
+diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+index c0c8ce1f8b00..b44f14c278ca 100644
 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
 @@ -57,20 +57,22 @@ struct emac_variant {
@@ -47,7 +49,7 @@ Signed-off-by: Ondrej Jirman <megous@megous.com>
  	struct reset_control *rst_ephy;
  	const struct emac_variant *variant;
  	struct regmap_field *regmap_field;
-@@ -549,9 +551,9 @@ static int sun8i_dwmac_init(struct platf
+@@ -571,9 +573,9 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
  	struct sunxi_priv_data *gmac = priv;
  	int ret;
  
@@ -59,7 +61,7 @@ Signed-off-by: Ondrej Jirman <megous@megous.com>
  		return ret;
  	}
  
-@@ -572,8 +574,7 @@ static int sun8i_dwmac_init(struct platf
+@@ -594,8 +596,7 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
  err_disable_clk:
  	clk_disable_unprepare(gmac->tx_clk);
  err_disable_regulator:
@@ -69,7 +71,7 @@ Signed-off-by: Ondrej Jirman <megous@megous.com>
  
  	return ret;
  }
-@@ -1019,7 +1020,7 @@ static void sun8i_dwmac_exit(struct plat
+@@ -1043,7 +1044,7 @@ static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
  
  	clk_disable_unprepare(gmac->tx_clk);
  
@@ -78,7 +80,7 @@ Signed-off-by: Ondrej Jirman <megous@megous.com>
  }
  
  static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable)
-@@ -1147,11 +1148,9 @@ static int sun8i_dwmac_probe(struct plat
+@@ -1171,11 +1172,10 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
  	}
  
  	/* Optional regulator for PHY */
@@ -89,7 +91,11 @@ Signed-off-by: Ondrej Jirman <megous@megous.com>
 -			dev_err(dev, "Failed to get PHY regulator (%d)\n", ret);
 +	gmac->regulator_phy = devm_regulator_get(dev, "phy");
 +	if (IS_ERR(gmac->regulator_phy)) {
++		ret = PTR_ERR(gmac->regulator_phy);
 +		dev_err_probe(dev, ret, "Failed to get PHY regulator\n");
  		return ret;
  	}
  
+-- 
+2.34.1
+
diff --git a/0002-net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regu.patch b/net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch
index 50e7cc4d460e..a371a65ffa42 100644
--- a/0002-net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regu.patch
+++ b/net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch
@@ -1,7 +1,8 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Ondrej Jirman <megous@megous.com>
+From b29d33d0e22bc5305c62de369642f842a205f80a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
 Date: Wed, 27 Mar 2019 13:21:06 +0100
-Subject: [PATCH] net: stmmac: sun8i: Use devm_regulator_get for PHY regulator
+Subject: [PATCH 068/456] net: stmmac: sun8i: Use devm_regulator_get for PHY
+ regulator
 
 Use devm_regulator_get instead of devm_regulator_get_optional and rely
 on dummy supply. This avoids NULL checks before regulator_enable/disable
@@ -15,14 +16,16 @@ was reported previously on errors and lack of regulator property in DT.
 Finally, we'll be adding further optional regulators, and the overall
 code will be simpler.
 
-Signed-off-by: Ondrej Jirman <megous@megous.com>
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
 ---
  .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 23 ++++++++-----------
  1 file changed, 10 insertions(+), 13 deletions(-)
 
+diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+index 09644ab0d87a..c0c8ce1f8b00 100644
 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
 +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
-@@ -549,12 +549,10 @@ static int sun8i_dwmac_init(struct platf
+@@ -571,12 +571,10 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
  	struct sunxi_priv_data *gmac = priv;
  	int ret;
  
@@ -39,7 +42,7 @@ Signed-off-by: Ondrej Jirman <megous@megous.com>
  	}
  
  	ret = clk_prepare_enable(gmac->tx_clk);
-@@ -1021,8 +1019,7 @@ static void sun8i_dwmac_exit(struct plat
+@@ -1045,8 +1043,7 @@ static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
  
  	clk_disable_unprepare(gmac->tx_clk);
  
@@ -49,7 +52,7 @@ Signed-off-by: Ondrej Jirman <megous@megous.com>
  }
  
  static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable)
-@@ -1150,12 +1147,12 @@ static int sun8i_dwmac_probe(struct plat
+@@ -1174,12 +1171,12 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
  	}
  
  	/* Optional regulator for PHY */
@@ -67,3 +70,6 @@ Signed-off-by: Ondrej Jirman <megous@megous.com>
  	}
  
  	/* The "GMAC clock control" register might be located in the
+-- 
+2.34.1
+
diff --git a/patches-links.txt b/patches-links.txt
new file mode 100644
index 000000000000..514e74779e2a
--- /dev/null
+++ b/patches-links.txt
@@ -0,0 +1,3 @@
+https://github.com/armbian/build/blob/master/patch/kernel/archive/sunxi-5.17/patches.armbian/HACK-media-uapi-hevc-tiles-and-num_slices.patch
+https://github.com/armbian/build/blob/master/patch/kernel/archive/sunxi-5.17/patches.armbian/Revert-net-Remove-net-ipx.h-and-uapi-linux-ipx.h-hea.patch
+https://github.com/armbian/build/blob/master/patch/kernel/archive/sunxi-5.17/patches.armbian/WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch
diff --git a/sun50i-h6-tqc-a01.dts b/sun50i-h6-tqc-a01.dts
index e3e01fad4797..543ff87cd704 100644
--- a/sun50i-h6-tqc-a01.dts
+++ b/sun50i-h6-tqc-a01.dts
@@ -152,6 +152,10 @@
 	};
 };
 
+&i2s1 {
+    status = "okay";
+};
+
 &i2c3 {
     status = "okay";
 };
@@ -342,6 +346,10 @@
 	clocks = <&ext_osc32k>;
 };
 
+&sound_hdmi {
+    status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_ph_pins>;
author	yjun	2022-05-17 12:16:32 +0800
committer	yjun	2022-05-17 12:16:32 +0800
commit	d66c7d0fc0b35270f9fe591a311563cc0d851555 (patch)
tree	78708ccbe7b46d0494838100815004e5f5fff152
parent	df61abd38d06cbb1f4eca16f1e070d986a8b6dbd (diff)
download	aur-d66c7d0fc0b35270f9fe591a311563cc0d851555.tar.gz