Update to 4.17.9-1

1 files changed, 22 insertions, 62 deletions

diff --git a/add-acs-overrides.patch b/add-acs-overrides.patch
index f08febddaf1b..b92a5f326d67 100644
--- a/add-acs-overrides.patch
+++ b/add-acs-overrides.patch
@@ -1,67 +1,26 @@
-From 220e23ae8d0d346e1b16d843649dd137ba76861c Mon Sep 17 00:00:00 2001
+From 087743912610c92eeff1ffbfbd2964faac969d0f Mon Sep 17 00:00:00 2001
 From: Mark Weiman <mark.weiman@markzz.com>
 Date: Sun, 24 Jun 2018 12:31:25 -0400
-Subject: [PATCH] [PATCH] pci: Enable overrides for missing ACS capabilities
- (4.17)
+Subject: [PATCH] pci: Enable overrides for missing ACS capabilities (4.17)
 
 This an updated version of Alex Williamson's patch from:
 https://lkml.org/lkml/2013/5/30/513
 
 Original commit message follows:
 ---
-PCIe ACS (Access Control Services) is the PCIe 2.0+ feature that
-allows us to control whether transactions are allowed to be redirected
-in various subnodes of a PCIe topology.  For instance, if two
-endpoints are below a root port or downsteam switch port, the
-downstream port may optionally redirect transactions between the
-devices, bypassing upstream devices.  The same can happen internally
-on multifunction devices.  The transaction may never be visible to the
-upstream devices.
-
-One upstream device that we particularly care about is the IOMMU.  If
-a redirection occurs in the topology below the IOMMU, then the IOMMU
-cannot provide isolation between devices.  This is why the PCIe spec
-encourages topologies to include ACS support.  Without it, we have to
-assume peer-to-peer DMA within a hierarchy can bypass IOMMU isolation.
-
-Unfortunately, far too many topologies do not support ACS to make this
-a steadfast requirement.  Even the latest chipsets from Intel are only
-sporadically supporting ACS.  We have trouble getting interconnect
-vendors to include the PCIe spec required PCIe capability, let alone
-suggested features.
-
-Therefore, we need to add some flexibility.  The pcie_acs_override=
-boot option lets users opt-in specific devices or sets of devices to
-assume ACS support.  The "downstream" option assumes full ACS support
-on root ports and downstream switch ports.  The "multifunction"
-option assumes the subset of ACS features available on multifunction
-endpoints and upstream switch ports are supported.  The "id:nnnn:nnnn"
-option enables ACS support on devices matching the provided vendor
-and device IDs, allowing more strategic ACS overrides.  These options
-may be combined in any order.  A maximum of 16 id specific overrides
-are available.  It's suggested to use the most limited set of options
-necessary to avoid completely disabling ACS across the topology.
-Note to hardware vendors, we have facilities to permanently quirk
-specific devices which enforce isolation but not provide an ACS
-capability.  Please contact me to have your devices added and save
-your customers the hassle of this boot option.
-
-Signed-off-by: Mark Weiman <mark.weiman@markzz.com>
----
- .../admin-guide/kernel-parameters.txt         |   9 ++
- drivers/pci/quirks.c                          | 101 ++++++++++++++++++
+ .../admin-guide/kernel-parameters.txt         |   8 ++
+ drivers/pci/quirks.c                          | 102 ++++++++++++++++++
  2 files changed, 110 insertions(+)
 
 diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
-index f2040d46f095..33ccd3daa8bc 100644
+index 533ff5c68970..353481231683 100644
 --- a/Documentation/admin-guide/kernel-parameters.txt
 +++ b/Documentation/admin-guide/kernel-parameters.txt
-@@ -3019,6 +3019,15 @@
+@@ -3028,6 +3028,14 @@
  		nomsi		[MSI] If the PCI_MSI kernel config parameter is
  				enabled, this kernel boot option can be used to
  				disable the use of MSI interrupts system-wide.
-+		pci_acs_override =
-+					[PCIE] Override missing PCIe ACS support for:
++		pci_acs_override [PCIE] Override missing PCIe ACS support for:
 +				downstream
 +					All downstream ports - full ACS capabilities
 +				multifunction
@@ -73,11 +32,11 @@ index f2040d46f095..33ccd3daa8bc 100644
  				Safety option to keep boot IRQs enabled. This
  				should never be necessary.
 diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
-index 2990ad1e7c99..962372b61e26 100644
+index f439de848658..5c3ec5e04349 100644
 --- a/drivers/pci/quirks.c
 +++ b/drivers/pci/quirks.c
-@@ -3533,6 +3533,106 @@ static int __init pci_apply_final_quirks(void)
- 
+@@ -186,6 +186,106 @@ static int __init pci_apply_final_quirks(void)
+ }
  fs_initcall_sync(pci_apply_final_quirks);
  
 +static bool acs_on_downstream;
@@ -181,16 +140,17 @@ index 2990ad1e7c99..962372b61e26 100644
 +}
 +
  /*
-  * Following are device-specific reset methods which can be used to
-  * reset a single function if other methods (e.g. FLR, PM D0->D3) are
-@@ -4372,6 +4472,7 @@ static const struct pci_dev_acs_enabled {
- 	{ PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
- 	/* APM X-Gene */
- 	{ PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
-+    { PCI_ANY_ID, PCI_ANY_ID, pcie_acs_overrides },
- 	/* Ampere Computing */
- 	{ PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
- 	{ PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
+  * Decoding should be disabled for a PCI device during BAR sizing to avoid
+  * conflict. But doing so may cause problems on host bridge and perhaps other
+@@ -4395,6 +4495,8 @@ static const struct pci_dev_acs_enabled {
+ 	{ PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
+ 	{ PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
+ 	{ PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
++	/* allow acs for any */
++	{ PCI_ANY_ID, PCI_ANY_ID, pcie_acs_overrides },
+ 	{ 0 }
+ };
+ 
 -- 
-2.17.1
+2.18.0