5.4.8

1 files changed, 24 insertions, 78 deletions

diff --git a/add-acs-overrides.patch b/add-acs-overrides.patch
index aa9b381f6d30..5989e6d3f262 100644
--- a/add-acs-overrides.patch
+++ b/add-acs-overrides.patch
@@ -1,81 +1,31 @@
-From f56f33917f418568141184eb2503ec65309a8255 Mon Sep 17 00:00:00 2001
-From: Mark Weiman <mark.weiman@markzz.com>
-Date: Thu, 13 Dec 2018 13:15:16 -0500
-Subject: [PATCH] pci: Enable overrides for missing ACS capabilities (4.18)
-
-This an updated version of Alex Williamson's patch from:
-https://lkml.org/lkml/2013/5/30/513
-
-Original commit message follows:
----
-PCIe ACS (Access Control Services) is the PCIe 2.0+ feature that
-allows us to control whether transactions are allowed to be redirected
-in various subnodes of a PCIe topology.  For instance, if two
-endpoints are below a root port or downsteam switch port, the
-downstream port may optionally redirect transactions between the
-devices, bypassing upstream devices.  The same can happen internally
-on multifunction devices.  The transaction may never be visible to the
-upstream devices.
-
-One upstream device that we particularly care about is the IOMMU.  If
-a redirection occurs in the topology below the IOMMU, then the IOMMU
-cannot provide isolation between devices.  This is why the PCIe spec
-encourages topologies to include ACS support.  Without it, we have to
-assume peer-to-peer DMA within a hierarchy can bypass IOMMU isolation.
-
-Unfortunately, far too many topologies do not support ACS to make this
-a steadfast requirement.  Even the latest chipsets from Intel are only
-sporadically supporting ACS.  We have trouble getting interconnect
-vendors to include the PCIe spec required PCIe capability, let alone
-suggested features.
-
-Therefore, we need to add some flexibility.  The pcie_acs_override=
-boot option lets users opt-in specific devices or sets of devices to
-assume ACS support.  The "downstream" option assumes full ACS support
-on root ports and downstream switch ports.  The "multifunction"
-option assumes the subset of ACS features available on multifunction
-endpoints and upstream switch ports are supported.  The "id:nnnn:nnnn"
-option enables ACS support on devices matching the provided vendor
-and device IDs, allowing more strategic ACS overrides.  These options
-may be combined in any order.  A maximum of 16 id specific overrides
-are available.  It's suggested to use the most limited set of options
-necessary to avoid completely disabling ACS across the topology.
-Note to hardware vendors, we have facilities to permanently quirk
-specific devices which enforce isolation but not provide an ACS
-capability.  Please contact me to have your devices added and save
-your customers the hassle of this boot option.
----
- .../admin-guide/kernel-parameters.txt         |   8 ++
- drivers/pci/quirks.c                          | 102 ++++++++++++++++++
- 2 files changed, 110 insertions(+)
-
 diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
-index 0c404cda531a..0d45f0014f4a 100644
+index a84a83f8881e..7d3517aaaebe 100644
 --- a/Documentation/admin-guide/kernel-parameters.txt
 +++ b/Documentation/admin-guide/kernel-parameters.txt
-@@ -3165,6 +3165,14 @@
+@@ -3375,6 +3375,15 @@
  		nomsi		[MSI] If the PCI_MSI kernel config parameter is
  				enabled, this kernel boot option can be used to
  				disable the use of MSI interrupts system-wide.
-+		pci_acs_override [PCIE] Override missing PCIe ACS support for:
++		pcie_acs_override =
++					[PCIE] Override missing PCIe ACS support for:
 +				downstream
 +					All downstream ports - full ACS capabilities
-+				multifunction
-+					Add multifunction devices - multifunction ACS subset
++				multfunction
++					All multifunction devices - multifunction ACS subset
 +				id:nnnn:nnnn
-+					Specific device - full ACS capabilities
++					Specfic device - full ACS capabilities
 +					Specified as vid:did (vendor/device ID) in hex
  		noioapicquirk	[APIC] Disable all boot interrupt quirks.
  				Safety option to keep boot IRQs enabled. This
  				should never be necessary.
 diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
-index c0673a717239..695d99b390f7 100644
+index 320255e5e8f8..d4aaf74c54df 100644
 --- a/drivers/pci/quirks.c
 +++ b/drivers/pci/quirks.c
-@@ -194,6 +194,106 @@ static int __init pci_apply_final_quirks(void)
+@@ -3483,6 +3483,106 @@ static void quirk_no_bus_reset(struct pci_dev *dev)
+ 	dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
  }
- fs_initcall_sync(pci_apply_final_quirks);
- 
+
 +static bool acs_on_downstream;
 +static bool acs_on_multifunction;
 +
@@ -116,10 +66,11 @@ index c0673a717239..695d99b390f7 100644
 +				goto next;
 +			}
 +			acs_on_ids[max_acs_id].vendor = val;
-+		p += strcspn(p, ":");
-+		if (*p != ':') {
-+			pr_warn("PCIe ACS invalid ID\n");
-+			goto next;
++
++			p += strcspn(p, ":");
++			if (*p != ':') {
++				pr_warn("PCIe ACS invalid ID\n");
++				goto next;
 +			}
 +
 +			p++;
@@ -159,7 +110,7 @@ index c0673a717239..695d99b390f7 100644
 +			acs_on_ids[i].device == dev->device)
 +				return 1;
 +
-+switch (pci_pcie_type(dev)) {
++	switch (pci_pcie_type(dev)) {
 +	case PCI_EXP_TYPE_DOWNSTREAM:
 +	case PCI_EXP_TYPE_ROOT_PORT:
 +		if (acs_on_downstream)
@@ -175,19 +126,14 @@ index c0673a717239..695d99b390f7 100644
 +
 +	return -ENOTTY;
 +}
-+
  /*
-  * Decoding should be disabled for a PCI device during BAR sizing to avoid
-  * conflict. But doing so may cause problems on host bridge and perhaps other
-@@ -4513,6 +4613,8 @@ static const struct pci_dev_acs_enabled {
- 	{ PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
- 	{ PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
- 	{ PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
-+	/* allow acs for any */
-+	{ PCI_ANY_ID, PCI_ANY_ID, pcie_acs_overrides },
+  * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
+  * The device will throw a Link Down error on AER-capable systems and
+@@ -4663,6 +4763,7 @@ static const struct pci_dev_acs_enabled {
+ 	{ PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
+ 	/* Amazon Annapurna Labs */
+ 	{ PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
++   { PCI_ANY_ID, PCI_ANY_ID, pcie_acs_overrides },
  	{ 0 }
  };
- 
--- 
-2.20.0