diff options
| author | Shayne Hartford | 2019-04-10 10:49:38 -0400 |
|---|---|---|
| committer | Shayne Hartford | 2019-04-10 10:49:38 -0400 |
| commit | 53faef76c4becc8e1030d1616db191a70e3b9e9f (patch) | |
| tree | f0d0071c26748242d52eb4061beac695af67f5fb /add-acs-overrides.patch | |
| download | aur-53faef76c4becc8e1030d1616db191a70e3b9e9f.tar.gz | |
Added kernel
Diffstat (limited to 'add-acs-overrides.patch')
| -rw-r--r-- | add-acs-overrides.patch | 443 |
1 files changed, 443 insertions, 0 deletions
diff --git a/add-acs-overrides.patch b/add-acs-overrides.patch new file mode 100644 index 000000000000..42ee6f8ef548 --- /dev/null +++ b/add-acs-overrides.patch @@ -0,0 +1,443 @@ +<!DOCTYPE html> +<html lang='en'> +<head> +<title>add-acs-overrides.patch - aur.git - AUR Package Repositories</title> +<meta name='generator' content='cgit v1.2.1-2-g66f5'/> +<meta name='robots' content='index, nofollow'/> +<link rel='stylesheet' type='text/css' href='/css/cgit.css'/> +<link rel='shortcut icon' href='/images/favicon.ico'/> +<link rel='alternate' title='Atom feed' href='https://aur.archlinux.org/cgit/aur.git/atom/add-acs-overrides.patch?h=linux-vfio' type='application/atom+xml'/> +<link rel='vcs-git' href='https://aur.archlinux.org/linux-vfio.git/' title='aur.git Git repository'/> +</head> +<body> + <div id="archnavbar" class="anb-aur"> + <div id="archnavbarlogo"><h1><a href="/" title="Return to the main page">Arch Linux User Repository</a></h1></div> + <div id="archnavbarmenu"> + <ul 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+<a id='n193' href='#n193'>193</a> +</pre></td> +<td class='lines'><pre><code>From f56f33917f418568141184eb2503ec65309a8255 Mon Sep 17 00:00:00 2001 +From: Mark Weiman <mark.weiman@markzz.com> +Date: Thu, 13 Dec 2018 13:15:16 -0500 +Subject: [PATCH] pci: Enable overrides for missing ACS capabilities (4.18) + +This an updated version of Alex Williamson's patch from: +https://lkml.org/lkml/2013/5/30/513 + +Original commit message follows: +<span class="hl kwa">---</span> +PCIe ACS (Access Control Services) is the PCIe 2.0+ feature that +allows us to control whether transactions are allowed to be redirected +in various subnodes of a PCIe topology. For instance, if two +endpoints are below a root port or downsteam switch port, the +downstream port may optionally redirect transactions between the +devices, bypassing upstream devices. The same can happen internally +on multifunction devices. The transaction may never be visible to the +upstream devices. + +One upstream device that we particularly care about is the IOMMU. If +a redirection occurs in the topology below the IOMMU, then the IOMMU +cannot provide isolation between devices. This is why the PCIe spec +encourages topologies to include ACS support. Without it, we have to +assume peer-to-peer DMA within a hierarchy can bypass IOMMU isolation. + +Unfortunately, far too many topologies do not support ACS to make this +a steadfast requirement. Even the latest chipsets from Intel are only +sporadically supporting ACS. We have trouble getting interconnect +vendors to include the PCIe spec required PCIe capability, let alone +suggested features. + +Therefore, we need to add some flexibility. The pcie_acs_override= +boot option lets users opt-in specific devices or sets of devices to +assume ACS support. The "downstream" option assumes full ACS support +on root ports and downstream switch ports. The "multifunction" +option assumes the subset of ACS features available on multifunction +endpoints and upstream switch ports are supported. The "id:nnnn:nnnn" +option enables ACS support on devices matching the provided vendor +and device IDs, allowing more strategic ACS overrides. These options +may be combined in any order. A maximum of 16 id specific overrides +are available. It's suggested to use the most limited set of options +necessary to avoid completely disabling ACS across the topology. +Note to hardware vendors, we have facilities to permanently quirk +specific devices which enforce isolation but not provide an ACS +capability. Please contact me to have your devices added and save +your customers the hassle of this boot option. +<span class="hl kwa">---</span> + .../admin-guide/kernel-parameters.txt | 8 ++ + drivers/pci/quirks.c | 102 ++++++++++++++++++ + 2 files changed, 110 insertions(+) + +diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt +index 0c404cda531a..0d45f0014f4a 100644 +<span class="hl kwa">--- a/Documentation/admin-guide/kernel-parameters.txt</span> +<span class="hl kwb">+++ b/Documentation/admin-guide/kernel-parameters.txt</span> +<span class="hl kwd">@@ -3165,6 +3165,14 @@</span> + nomsi [MSI] If the PCI_MSI kernel config parameter is + enabled, this kernel boot option can be used to + disable the use of MSI interrupts system-wide. +<span class="hl kwb">+ pci_acs_override [PCIE] Override missing PCIe ACS support for:</span> +<span class="hl kwb">+ downstream</span> +<span class="hl kwb">+ All downstream ports - full ACS capabilities</span> +<span class="hl kwb">+ multifunction</span> +<span class="hl kwb">+ Add multifunction devices - multifunction ACS subset</span> +<span class="hl kwb">+ id:nnnn:nnnn</span> +<span class="hl kwb">+ Specific device - full ACS capabilities</span> +<span class="hl kwb">+ Specified as vid:did (vendor/device ID) in hex</span> + noioapicquirk [APIC] Disable all boot interrupt quirks. + Safety option to keep boot IRQs enabled. This + should never be necessary. +diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c +index c0673a717239..695d99b390f7 100644 +<span class="hl kwa">--- a/drivers/pci/quirks.c</span> +<span class="hl kwb">+++ b/drivers/pci/quirks.c</span> +@@ -194,6 +194,106 @@ static int __init pci_apply_final_quirks(void) + } + fs_initcall_sync(pci_apply_final_quirks); + +<span class="hl kwb">+static bool acs_on_downstream;</span> +<span class="hl kwb">+static bool acs_on_multifunction;</span> +<span class="hl kwb">+</span> +<span class="hl kwb">+#define NUM_ACS_IDS 16</span> +<span class="hl kwb">+struct acs_on_id {</span> +<span class="hl kwb">+ unsigned short vendor;</span> +<span class="hl kwb">+ unsigned short device;</span> +<span class="hl kwb">+};</span> +<span class="hl kwb">+static struct acs_on_id acs_on_ids[NUM_ACS_IDS];</span> +<span class="hl kwb">+static u8 max_acs_id;</span> +<span class="hl kwb">+</span> +<span class="hl kwb">+static __init int pcie_acs_override_setup(char *p)</span> +<span class="hl kwb">+{</span> +<span class="hl kwb">+ if (!p)</span> +<span class="hl kwb">+ return -EINVAL;</span> +<span class="hl kwb">+</span> +<span class="hl kwb">+ while (*p) {</span> +<span class="hl kwb">+ if (!strncmp(p, "downstream", 10))</span> +<span class="hl kwb">+ acs_on_downstream = true;</span> +<span class="hl kwb">+ if (!strncmp(p, "multifunction", 13))</span> +<span class="hl kwb">+ acs_on_multifunction = true;</span> +<span class="hl kwb">+ if (!strncmp(p, "id:", 3)) {</span> +<span class="hl kwb">+ char opt[5];</span> +<span class="hl kwb">+ int ret;</span> +<span class="hl kwb">+ long val;</span> +<span class="hl kwb">+</span> +<span class="hl kwb">+ if (max_acs_id >= NUM_ACS_IDS - 1) {</span> +<span class="hl kwb">+ pr_warn("Out of PCIe ACS override slots (%d)\n",</span> +<span class="hl kwb">+ NUM_ACS_IDS);</span> +<span class="hl kwb">+ goto next;</span> +<span class="hl kwb">+ }</span> +<span class="hl kwb">+</span> +<span class="hl kwb">+ p += 3;</span> +<span class="hl kwb">+ snprintf(opt, 5, "%s", p);</span> +<span class="hl kwb">+ ret = kstrtol(opt, 16, &val);</span> +<span class="hl kwb">+ if (ret) {</span> +<span class="hl kwb">+ pr_warn("PCIe ACS ID parse error %d\n", ret);</span> +<span class="hl kwb">+ goto next;</span> +<span class="hl kwb">+ }</span> +<span class="hl kwb">+ acs_on_ids[max_acs_id].vendor = val;</span> +<span class="hl kwb">+ p += strcspn(p, ":");</span> +<span class="hl kwb">+ if (*p != ':') {</span> +<span class="hl kwb">+ pr_warn("PCIe ACS invalid ID\n");</span> +<span class="hl kwb">+ goto next;</span> +<span class="hl kwb">+ }</span> +<span class="hl kwb">+</span> +<span class="hl kwb">+ p++;</span> +<span class="hl kwb">+ snprintf(opt, 5, "%s", p);</span> +<span class="hl kwb">+ ret = kstrtol(opt, 16, &val);</span> +<span class="hl kwb">+ if (ret) {</span> +<span class="hl kwb">+ pr_warn("PCIe ACS ID parse error %d\n", ret);</span> +<span class="hl kwb">+ goto next;</span> +<span class="hl kwb">+ }</span> +<span class="hl kwb">+ acs_on_ids[max_acs_id].device = val;</span> +<span class="hl kwb">+ max_acs_id++;</span> +<span class="hl kwb">+ }</span> +<span class="hl kwb">+next:</span> +<span class="hl kwb">+ p += strcspn(p, ",");</span> +<span class="hl kwb">+ if (*p == ',')</span> +<span class="hl kwb">+ p++;</span> +<span class="hl kwb">+ }</span> +<span class="hl kwb">+</span> +<span class="hl kwb">+ if (acs_on_downstream || acs_on_multifunction || max_acs_id)</span> +<span class="hl kwb">+ pr_warn("Warning: PCIe ACS overrides enabled; This may allow non-IOMMU protected peer-to-peer DMA\n");</span> +<span class="hl kwb">+</span> +<span class="hl kwb">+ return 0;</span> +<span class="hl kwb">+}</span> +<span class="hl kwb">+early_param("pcie_acs_override", pcie_acs_override_setup);</span> +<span class="hl kwb">+</span> +<span class="hl kwb">+static int pcie_acs_overrides(struct pci_dev *dev, u16 acs_flags)</span> +<span class="hl kwb">+{</span> +<span class="hl kwb">+ int i;</span> +<span class="hl kwb">+</span> +<span class="hl kwb">+ /* Never override ACS for legacy devices or devices with ACS caps */</span> +<span class="hl kwb">+ if (!pci_is_pcie(dev) ||</span> +<span class="hl kwb">+ pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS))</span> +<span class="hl kwb">+ return -ENOTTY;</span> +<span class="hl kwb">+</span> +<span class="hl kwb">+ for (i = 0; i < max_acs_id; i++)</span> +<span class="hl kwb">+ if (acs_on_ids[i].vendor == dev->vendor &&</span> +<span class="hl kwb">+ acs_on_ids[i].device == dev->device)</span> +<span class="hl kwb">+ return 1;</span> +<span class="hl kwb">+</span> +<span class="hl kwb">+switch (pci_pcie_type(dev)) {</span> +<span class="hl kwb">+ case PCI_EXP_TYPE_DOWNSTREAM:</span> +<span class="hl kwb">+ case PCI_EXP_TYPE_ROOT_PORT:</span> +<span class="hl kwb">+ if (acs_on_downstream)</span> +<span class="hl kwb">+ return 1;</span> +<span class="hl kwb">+ break;</span> +<span class="hl kwb">+ case PCI_EXP_TYPE_ENDPOINT:</span> +<span class="hl kwb">+ case PCI_EXP_TYPE_UPSTREAM:</span> +<span class="hl kwb">+ case PCI_EXP_TYPE_LEG_END:</span> +<span class="hl kwb">+ case PCI_EXP_TYPE_RC_END:</span> +<span class="hl kwb">+ if (acs_on_multifunction && dev->multifunction)</span> +<span class="hl kwb">+ return 1;</span> +<span class="hl kwb">+ }</span> +<span class="hl kwb">+</span> +<span class="hl kwb">+ return -ENOTTY;</span> +<span class="hl kwb">+}</span> +<span class="hl kwb">+</span> + /* + * Decoding should be disabled for a PCI device during BAR sizing to avoid + * conflict. But doing so may cause problems on host bridge and perhaps other +@@ -4513,6 +4613,8 @@ static const struct pci_dev_acs_enabled { + { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs }, + { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs }, + { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs }, +<span class="hl kwb">+ /* allow acs for any */</span> +<span class="hl kwb">+ { PCI_ANY_ID, PCI_ANY_ID, pcie_acs_overrides },</span> + { 0 } + }; + +<span class="hl kwa">-- </span> +2.20.0 + +</code></pre></td></tr></table> +</div> <!-- class=content --> +<div id="footer"> + <p> + Copyright © 2004-2018 aurweb Development Team – + <strong>AUR packages are user produced content. Any use of the provided files is at your own risk.</strong> + </p> +</div> +</div> <!-- id=cgit --> +</body> +</html> |