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| author | yjun | 2022-04-25 11:46:44 +0800 |
|---|---|---|
| committer | yjun | 2022-04-25 11:46:44 +0800 |
| commit | c125b79690b319c3348cb88c768ad0bb718643e8 (patch) | |
| tree | e91c2a97b9fa94eab72a615379b6f9372de1fbb6 /general-meson-gx-mmc-set-core-clock-phase-to-270-degres.patch | |
| parent | 6c5931fb034098e8aa111835b9817f75a4a69bec (diff) | |
| download | aur-c125b79690b319c3348cb88c768ad0bb718643e8.tar.gz | |
updpkg: linux-phicomm-n1 5.17.4 && some meson-vdec, hdmix, mmc optimation patches
Diffstat (limited to 'general-meson-gx-mmc-set-core-clock-phase-to-270-degres.patch')
| -rw-r--r-- | general-meson-gx-mmc-set-core-clock-phase-to-270-degres.patch | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/general-meson-gx-mmc-set-core-clock-phase-to-270-degres.patch b/general-meson-gx-mmc-set-core-clock-phase-to-270-degres.patch new file mode 100644 index 000000000000..704e97c2d495 --- /dev/null +++ b/general-meson-gx-mmc-set-core-clock-phase-to-270-degres.patch @@ -0,0 +1,59 @@ +From 5c5664545a97520bbce591add5a7dbbea143b999 Mon Sep 17 00:00:00 2001 +From: Neil Armstrong <narmstrong@baylibre.com> +Date: Thu, 14 Jan 2021 17:43:02 +0100 +Subject: [PATCH 54/90] WIP: mmc: meson-gx-mmc: set core clock phase to 270 + degrees for AXG compatible controllers + +Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> +--- + drivers/mmc/host/meson-gx-mmc.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c +index 1a11a4bf4d4f..df60312a1765 100644 +--- a/drivers/mmc/host/meson-gx-mmc.c ++++ b/drivers/mmc/host/meson-gx-mmc.c +@@ -38,6 +38,7 @@ + #define CLK_RX_PHASE_MASK GENMASK(13, 12) + #define CLK_PHASE_0 0 + #define CLK_PHASE_180 2 ++#define CLK_PHASE_270 3 + #define CLK_V2_TX_DELAY_MASK GENMASK(19, 16) + #define CLK_V2_RX_DELAY_MASK GENMASK(23, 20) + #define CLK_V2_ALWAYS_ON BIT(24) +@@ -136,6 +137,7 @@ struct meson_mmc_data { + unsigned int rx_delay_mask; + unsigned int always_on; + unsigned int adjust; ++ unsigned int clk_core_phase; + }; + + struct sd_emmc_desc { +@@ -428,7 +430,7 @@ static int meson_mmc_clk_init(struct meson_host *host) + /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ + clk_reg = CLK_ALWAYS_ON(host); + clk_reg |= CLK_DIV_MASK; +- clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180); ++ clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, host->data->clk_core_phase); + clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0); + clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0); + writel(clk_reg, host->regs + SD_EMMC_CLOCK); +@@ -1337,6 +1339,7 @@ static const struct meson_mmc_data meson_gx_data = { + .rx_delay_mask = CLK_V2_RX_DELAY_MASK, + .always_on = CLK_V2_ALWAYS_ON, + .adjust = SD_EMMC_ADJUST, ++ .clk_core_phase = CLK_PHASE_180, + }; + + static const struct meson_mmc_data meson_axg_data = { +@@ -1344,6 +1347,7 @@ static const struct meson_mmc_data meson_axg_data = { + .rx_delay_mask = CLK_V3_RX_DELAY_MASK, + .always_on = CLK_V3_ALWAYS_ON, + .adjust = SD_EMMC_V3_ADJUST, ++ .clk_core_phase = CLK_PHASE_270, + }; + + static const struct of_device_id meson_mmc_of_match[] = { +-- +2.35.1 + |