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Diffstat (limited to '.SRCINFO')
| -rw-r--r-- | .SRCINFO | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/.SRCINFO b/.SRCINFO new file mode 100644 index 000000000000..8236d230599f --- /dev/null +++ b/.SRCINFO @@ -0,0 +1,20 @@ +pkgbase = python-fusesoc + pkgdesc = Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python + pkgver = 1.9 + pkgrel = 0 + url = http://github.com/olofk/fusesoc/ + arch = any + license = GPLv3 + makedepends = python-setuptools + depends = python + depends = python-edalize + optdepends = iverilog: for simulating verilog designs + optdepends = ghdl: for simulating VHDL designs + provides = python-fusesoc + conflicts = python-fusesoc-git + options = !emptydirs + source = https://github.com/olofk/fusesoc/releases/download/1.9/fusesoc-1.9.tar.gz + md5sums = eec2d6fd3c8c68ce00b2eae7edb8e1a7 + +pkgname = python-fusesoc + |