diff options
Diffstat (limited to '0004-cpufreq-intel_pstate-ITMT-support-for-overclocked-sy.patch')
| -rw-r--r-- | 0004-cpufreq-intel_pstate-ITMT-support-for-overclocked-sy.patch | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/0004-cpufreq-intel_pstate-ITMT-support-for-overclocked-sy.patch b/0004-cpufreq-intel_pstate-ITMT-support-for-overclocked-sy.patch new file mode 100644 index 000000000000..9ae648cf5c73 --- /dev/null +++ b/0004-cpufreq-intel_pstate-ITMT-support-for-overclocked-sy.patch @@ -0,0 +1,55 @@ +From 62f1f7606485d450b23f86bc18dab101e7a2443d Mon Sep 17 00:00:00 2001 +From: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> +Date: Thu, 18 Nov 2021 21:18:01 -0800 +Subject: [PATCH 4/8] cpufreq: intel_pstate: ITMT support for overclocked + system + +On systems with overclocking enabled, CPPC Highest Performance can be +hard coded to 0xff. In this case even if we have cores with different +highest performance, ITMT can't be enabled as the current implementation +depends on CPPC Highest Performance. + +On such systems we can use MSR_HWP_CAPABILITIES maximum performance field +when CPPC.Highest Performance is 0xff. + +Due to legacy reasons, we can't solely depend on MSR_HWP_CAPABILITIES as +in some older systems CPPC Highest Performance is the only way to identify +different performing cores. + +Reported-by: Michael Larabel <Michael@MichaelLarabel.com> +Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> +--- + drivers/cpufreq/intel_pstate.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c +index e15c3bc17a55..8a2c6b58b652 100644 +--- a/drivers/cpufreq/intel_pstate.c ++++ b/drivers/cpufreq/intel_pstate.c +@@ -335,6 +335,8 @@ static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) + + static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); + ++#define CPPC_MAX_PERF U8_MAX ++ + static void intel_pstate_set_itmt_prio(int cpu) + { + struct cppc_perf_caps cppc_perf; +@@ -345,6 +347,14 @@ static void intel_pstate_set_itmt_prio(int cpu) + if (ret) + return; + ++ /* ++ * On some systems with overclocking enabled, CPPC.highest_perf is hardcoded to 0xff. ++ * In this case we can't use CPPC.highest_perf to enable ITMT. ++ * In this case we can look at MSR_HWP_CAPABILITIES bits [8:0] to decide. ++ */ ++ if (cppc_perf.highest_perf == CPPC_MAX_PERF) ++ cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached)); ++ + /* + * The priorities can be set regardless of whether or not + * sched_set_itmt_support(true) has been called and it is valid to +-- +2.34.1 + |