diff options
Diffstat (limited to '0008-drm-amd-display-Read-Golden-Settings-Table-from-VBIO.patch')
| -rw-r--r-- | 0008-drm-amd-display-Read-Golden-Settings-Table-from-VBIO.patch | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/0008-drm-amd-display-Read-Golden-Settings-Table-from-VBIO.patch b/0008-drm-amd-display-Read-Golden-Settings-Table-from-VBIO.patch new file mode 100644 index 000000000000..debcf3f29344 --- /dev/null +++ b/0008-drm-amd-display-Read-Golden-Settings-Table-from-VBIO.patch @@ -0,0 +1,41 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Sherry Wang <YAO.WANG1@amd.com> +Date: Tue, 10 May 2022 18:42:18 +0800 +Subject: [PATCH] drm/amd/display: Read Golden Settings Table from VBIOS + +[ Upstream commit 4b81dd2cc6f4f4e8cea0ed6ee8d5193a8ae14a72 ] + +[Why] +Dmub read AUX_DPHY_RX_CONTROL0 from Golden Setting Table, +but driver will set it to default value 0x103d1110, which +causes issue in some case + +[How] +Remove the driver code, use the value set by dmub in +dp_aux_init + +Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> +Acked-by: Jasdeep Dhillon <jdhillon@amd.com> +Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> +Signed-off-by: Sherry Wang <YAO.WANG1@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Sasha Levin <sashal@kernel.org> +--- + drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c +index d94fd1010debcfa582f11294d0039bbfef23ff17..8b12b4111c8870a54bda0561c8d5b076720e83d9 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c +@@ -230,9 +230,7 @@ static void enc31_hw_init(struct link_encoder *enc) + AUX_RX_PHASE_DETECT_LEN, [21,20] = 0x3 default is 3 + AUX_RX_DETECTION_THRESHOLD [30:28] = 1 + */ +- AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110); +- +- AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a); ++ // dmub will read AUX_DPHY_RX_CONTROL0/AUX_DPHY_TX_CONTROL from vbios table in dp_aux_init + + //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32; + // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk |