diff options
Diffstat (limited to '0012_loongson_force_cache_flush.patch')
| -rw-r--r-- | 0012_loongson_force_cache_flush.patch | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/0012_loongson_force_cache_flush.patch b/0012_loongson_force_cache_flush.patch new file mode 100644 index 000000000000..6211e6cc6e2c --- /dev/null +++ b/0012_loongson_force_cache_flush.patch @@ -0,0 +1,22 @@ +Description: Forced whole instruction cache flushing on Loongson. + Workaround for instruction cache flushing malfunction on Loongson systems + that occasionally cause failures under stress test conditions. +Author: Dusan Milosavljevic <dusan.milosavljevic@rt-rk.com> +Origin:upstream,https://github.com/paul99/v8m-rb/commit/ded6c2c2.patch +Last-Update: 2012-06-13 +--- a/src/mips/cpu-mips.cc ++++ b/src/mips/cpu-mips.cc +@@ -72,6 +72,13 @@ + #else // ANDROID + int res; + // See http://www.linux-mips.org/wiki/Cacheflush_Syscall. ++ if (kArchVariant==kLoongson) { ++ // Force flushing of whole instruction cache on Loongson. This is a ++ // workaround for problem when under stress tests cache lines are not ++ // flushed through syscall for some reasons. ++ size_t iCacheSize = 64 * KB; ++ size = iCacheSize + 1; ++ } + res = syscall(__NR_cacheflush, start, size, ICACHE); + if (res) { + V8_Fatal(__FILE__, __LINE__, "Failed to flush the instruction cache"); |