diff options
Diffstat (limited to '0030-mmc-sdhci-of-dwcmshc-rename-rk3568-to-rk35xx.patch')
| -rw-r--r-- | 0030-mmc-sdhci-of-dwcmshc-rename-rk3568-to-rk35xx.patch | 202 |
1 files changed, 202 insertions, 0 deletions
diff --git a/0030-mmc-sdhci-of-dwcmshc-rename-rk3568-to-rk35xx.patch b/0030-mmc-sdhci-of-dwcmshc-rename-rk3568-to-rk35xx.patch new file mode 100644 index 000000000000..6466e967f226 --- /dev/null +++ b/0030-mmc-sdhci-of-dwcmshc-rename-rk3568-to-rk35xx.patch @@ -0,0 +1,202 @@ +From 30841ba786ee2e55e05fa98a7c255b83313694f4 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel <sebastian.reichel@collabora.com> +Date: Wed, 4 May 2022 23:32:40 +0200 +Subject: [PATCH 30/73] mmc: sdhci-of-dwcmshc: rename rk3568 to rk35xx + +[ Upstream commit 86e1a8e1f9b555af342c53ae06284eeeab9a4263 ] + +Prepare driver for rk3588 support by renaming the internal data +structures. + +Acked-by: Adrian Hunter <adrian.hunter@intel.com> +Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> +Link: https://lore.kernel.org/r/20220504213251.264819-11-sebastian.reichel@collabora.com +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +Signed-off-by: Sasha Levin <sashal@kernel.org> +--- + drivers/mmc/host/sdhci-of-dwcmshc.c | 46 ++++++++++++++--------------- + 1 file changed, 23 insertions(+), 23 deletions(-) + +diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c +index 3a1b5ba36405..f5fd88c7adef 100644 +--- a/drivers/mmc/host/sdhci-of-dwcmshc.c ++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c +@@ -56,14 +56,14 @@ + #define DLL_LOCK_WO_TMOUT(x) \ + ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \ + (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0)) +-#define RK3568_MAX_CLKS 3 ++#define RK35xx_MAX_CLKS 3 + + #define BOUNDARY_OK(addr, len) \ + ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1))) + +-struct rk3568_priv { ++struct rk35xx_priv { + /* Rockchip specified optional clocks */ +- struct clk_bulk_data rockchip_clks[RK3568_MAX_CLKS]; ++ struct clk_bulk_data rockchip_clks[RK35xx_MAX_CLKS]; + struct reset_control *reset; + u8 txclk_tapnum; + }; +@@ -178,7 +178,7 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock + { + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); +- struct rk3568_priv *priv = dwc_priv->priv; ++ struct rk35xx_priv *priv = dwc_priv->priv; + u8 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT; + u32 extra, reg; + int err; +@@ -281,7 +281,7 @@ static const struct sdhci_ops sdhci_dwcmshc_ops = { + .adma_write_desc = dwcmshc_adma_write_desc, + }; + +-static const struct sdhci_ops sdhci_dwcmshc_rk3568_ops = { ++static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = { + .set_clock = dwcmshc_rk3568_set_clock, + .set_bus_width = sdhci_set_bus_width, + .set_uhs_signaling = dwcmshc_set_uhs_signaling, +@@ -296,18 +296,18 @@ static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = { + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, + }; + +-static const struct sdhci_pltfm_data sdhci_dwcmshc_rk3568_pdata = { +- .ops = &sdhci_dwcmshc_rk3568_ops, ++static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = { ++ .ops = &sdhci_dwcmshc_rk35xx_ops, + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | + SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | + SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, + }; + +-static int dwcmshc_rk3568_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) ++static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) + { + int err; +- struct rk3568_priv *priv = dwc_priv->priv; ++ struct rk35xx_priv *priv = dwc_priv->priv; + + priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc)); + if (IS_ERR(priv->reset)) { +@@ -319,14 +319,14 @@ static int dwcmshc_rk3568_init(struct sdhci_host *host, struct dwcmshc_priv *dwc + priv->rockchip_clks[0].id = "axi"; + priv->rockchip_clks[1].id = "block"; + priv->rockchip_clks[2].id = "timer"; +- err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), RK3568_MAX_CLKS, ++ err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), RK35xx_MAX_CLKS, + priv->rockchip_clks); + if (err) { + dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err); + return err; + } + +- err = clk_bulk_prepare_enable(RK3568_MAX_CLKS, priv->rockchip_clks); ++ err = clk_bulk_prepare_enable(RK35xx_MAX_CLKS, priv->rockchip_clks); + if (err) { + dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err); + return err; +@@ -348,7 +348,7 @@ static int dwcmshc_rk3568_init(struct sdhci_host *host, struct dwcmshc_priv *dwc + static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { + { + .compatible = "rockchip,rk3568-dwcmshc", +- .data = &sdhci_dwcmshc_rk3568_pdata, ++ .data = &sdhci_dwcmshc_rk35xx_pdata, + }, + { + .compatible = "snps,dwcmshc-sdhci", +@@ -371,7 +371,7 @@ static int dwcmshc_probe(struct platform_device *pdev) + struct sdhci_pltfm_host *pltfm_host; + struct sdhci_host *host; + struct dwcmshc_priv *priv; +- struct rk3568_priv *rk_priv = NULL; ++ struct rk35xx_priv *rk_priv = NULL; + const struct sdhci_pltfm_data *pltfm_data; + int err; + u32 extra; +@@ -426,8 +426,8 @@ static int dwcmshc_probe(struct platform_device *pdev) + host->mmc_host_ops.request = dwcmshc_request; + host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe; + +- if (pltfm_data == &sdhci_dwcmshc_rk3568_pdata) { +- rk_priv = devm_kzalloc(&pdev->dev, sizeof(struct rk3568_priv), GFP_KERNEL); ++ if (pltfm_data == &sdhci_dwcmshc_rk35xx_pdata) { ++ rk_priv = devm_kzalloc(&pdev->dev, sizeof(struct rk35xx_priv), GFP_KERNEL); + if (!rk_priv) { + err = -ENOMEM; + goto err_clk; +@@ -435,7 +435,7 @@ static int dwcmshc_probe(struct platform_device *pdev) + + priv->priv = rk_priv; + +- err = dwcmshc_rk3568_init(host, priv); ++ err = dwcmshc_rk35xx_init(host, priv); + if (err) + goto err_clk; + } +@@ -452,7 +452,7 @@ static int dwcmshc_probe(struct platform_device *pdev) + clk_disable_unprepare(pltfm_host->clk); + clk_disable_unprepare(priv->bus_clk); + if (rk_priv) +- clk_bulk_disable_unprepare(RK3568_MAX_CLKS, ++ clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, + rk_priv->rockchip_clks); + free_pltfm: + sdhci_pltfm_free(pdev); +@@ -464,14 +464,14 @@ static int dwcmshc_remove(struct platform_device *pdev) + struct sdhci_host *host = platform_get_drvdata(pdev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); +- struct rk3568_priv *rk_priv = priv->priv; ++ struct rk35xx_priv *rk_priv = priv->priv; + + sdhci_remove_host(host, 0); + + clk_disable_unprepare(pltfm_host->clk); + clk_disable_unprepare(priv->bus_clk); + if (rk_priv) +- clk_bulk_disable_unprepare(RK3568_MAX_CLKS, ++ clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, + rk_priv->rockchip_clks); + sdhci_pltfm_free(pdev); + +@@ -484,7 +484,7 @@ static int dwcmshc_suspend(struct device *dev) + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); +- struct rk3568_priv *rk_priv = priv->priv; ++ struct rk35xx_priv *rk_priv = priv->priv; + int ret; + + ret = sdhci_suspend_host(host); +@@ -496,7 +496,7 @@ static int dwcmshc_suspend(struct device *dev) + clk_disable_unprepare(priv->bus_clk); + + if (rk_priv) +- clk_bulk_disable_unprepare(RK3568_MAX_CLKS, ++ clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, + rk_priv->rockchip_clks); + + return ret; +@@ -507,7 +507,7 @@ static int dwcmshc_resume(struct device *dev) + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); +- struct rk3568_priv *rk_priv = priv->priv; ++ struct rk35xx_priv *rk_priv = priv->priv; + int ret; + + ret = clk_prepare_enable(pltfm_host->clk); +@@ -521,7 +521,7 @@ static int dwcmshc_resume(struct device *dev) + } + + if (rk_priv) { +- ret = clk_bulk_prepare_enable(RK3568_MAX_CLKS, ++ ret = clk_bulk_prepare_enable(RK35xx_MAX_CLKS, + rk_priv->rockchip_clks); + if (ret) + return ret; +-- +2.37.3 + |