summarylogtreecommitdiffstats
path: root/0039-drm-amd-display-Fix-HDMI-VSIF-V3-incorrect-issue.patch
diff options
context:
space:
mode:
Diffstat (limited to '0039-drm-amd-display-Fix-HDMI-VSIF-V3-incorrect-issue.patch')
-rw-r--r--0039-drm-amd-display-Fix-HDMI-VSIF-V3-incorrect-issue.patch75
1 files changed, 75 insertions, 0 deletions
diff --git a/0039-drm-amd-display-Fix-HDMI-VSIF-V3-incorrect-issue.patch b/0039-drm-amd-display-Fix-HDMI-VSIF-V3-incorrect-issue.patch
new file mode 100644
index 000000000000..70d2f1797d54
--- /dev/null
+++ b/0039-drm-amd-display-Fix-HDMI-VSIF-V3-incorrect-issue.patch
@@ -0,0 +1,75 @@
+From 71f2cb739a3cbcda4612889ce660fd8c380e3e1d Mon Sep 17 00:00:00 2001
+From: Leo Ma <hanghong.ma@amd.com>
+Date: Fri, 22 Jul 2022 13:42:58 -0400
+Subject: [PATCH 39/73] drm/amd/display: Fix HDMI VSIF V3 incorrect issue
+
+[ Upstream commit 0591183699fceeafb4c4141072d47775de83ecfb ]
+
+[Why]
+Reported from customer the checksum in AMD VSIF V3 is incorrect and
+causing blank screen issue.
+
+[How]
+Fix the packet length issue on AMD HDMI VSIF V3.
+
+Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
+Acked-by: Tom Chung <chiahsuan.chung@amd.com>
+Signed-off-by: Leo Ma <hanghong.ma@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../drm/amd/display/modules/freesync/freesync.c | 15 +++------------
+ 1 file changed, 3 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+index 03fa63d56fa6..948151e73573 100644
+--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
++++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+@@ -615,10 +615,6 @@ static void build_vrr_infopacket_data_v1(const struct mod_vrr_params *vrr,
+ * Note: We should never go above the field rate of the mode timing set.
+ */
+ infopacket->sb[8] = (unsigned char)((vrr->max_refresh_in_uhz + 500000) / 1000000);
+-
+- /* FreeSync HDR */
+- infopacket->sb[9] = 0;
+- infopacket->sb[10] = 0;
+ }
+
+ static void build_vrr_infopacket_data_v3(const struct mod_vrr_params *vrr,
+@@ -686,10 +682,6 @@ static void build_vrr_infopacket_data_v3(const struct mod_vrr_params *vrr,
+
+ /* PB16 : Reserved bits 7:1, FixedRate bit 0 */
+ infopacket->sb[16] = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? 1 : 0;
+-
+- //FreeSync HDR
+- infopacket->sb[9] = 0;
+- infopacket->sb[10] = 0;
+ }
+
+ static void build_vrr_infopacket_fs2_data(enum color_transfer_func app_tf,
+@@ -774,8 +766,7 @@ static void build_vrr_infopacket_header_v2(enum signal_type signal,
+ /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x09] */
+ infopacket->hb2 = 0x09;
+
+- *payload_size = 0x0A;
+-
++ *payload_size = 0x09;
+ } else if (dc_is_dp_signal(signal)) {
+
+ /* HEADER */
+@@ -824,9 +815,9 @@ static void build_vrr_infopacket_header_v3(enum signal_type signal,
+ infopacket->hb1 = version;
+
+ /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length] */
+- *payload_size = 0x10;
+- infopacket->hb2 = *payload_size - 1; //-1 for checksum
++ infopacket->hb2 = 0x10;
+
++ *payload_size = 0x10;
+ } else if (dc_is_dp_signal(signal)) {
+
+ /* HEADER */
+--
+2.37.3
+