diff options
Diffstat (limited to '0076-ice-Fix-PTP-TX-timestamp-offset-calculation.patch')
| -rw-r--r-- | 0076-ice-Fix-PTP-TX-timestamp-offset-calculation.patch | 84 |
1 files changed, 84 insertions, 0 deletions
diff --git a/0076-ice-Fix-PTP-TX-timestamp-offset-calculation.patch b/0076-ice-Fix-PTP-TX-timestamp-offset-calculation.patch new file mode 100644 index 000000000000..70ed76ac92c1 --- /dev/null +++ b/0076-ice-Fix-PTP-TX-timestamp-offset-calculation.patch @@ -0,0 +1,84 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Michal Michalik <michal.michalik@intel.com> +Date: Tue, 10 May 2022 13:03:43 +0200 +Subject: [PATCH] ice: Fix PTP TX timestamp offset calculation + +[ Upstream commit 71a579f0d3777a704355e6f1572dfba92a9b58b2 ] + +The offset was being incorrectly calculated for E822 - that led to +collisions in choosing TX timestamp register location when more than +one port was trying to use timestamping mechanism. + +In E822 one quad is being logically split between ports, so quad 0 is +having trackers for ports 0-3, quad 1 ports 4-7 etc. Each port should +have separate memory location for tracking timestamps. Due to error for +example ports 1 and 2 had been assigned to quad 0 with same offset (0), +while port 1 should have offset 0 and 1 offset 16. + +Fix it by correctly calculating quad offset. + +Fixes: 3a7496234d17 ("ice: implement basic E822 PTP support") +Signed-off-by: Michal Michalik <michal.michalik@intel.com> +Tested-by: Gurucharan <gurucharanx.g@intel.com> (A Contingent worker at Intel) +Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com> +Signed-off-by: Sasha Levin <sashal@kernel.org> +--- + drivers/net/ethernet/intel/ice/ice_ptp.c | 2 +- + drivers/net/ethernet/intel/ice/ice_ptp.h | 31 ++++++++++++++++++++++++ + 2 files changed, 32 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c +index 662947c882e8b1c84439eec7310a55c4893395ea..ef9344ef0d8e46654aae8b46b3e1cf6fb58a9222 100644 +--- a/drivers/net/ethernet/intel/ice/ice_ptp.c ++++ b/drivers/net/ethernet/intel/ice/ice_ptp.c +@@ -2271,7 +2271,7 @@ static int + ice_ptp_init_tx_e822(struct ice_pf *pf, struct ice_ptp_tx *tx, u8 port) + { + tx->quad = port / ICE_PORTS_PER_QUAD; +- tx->quad_offset = tx->quad * INDEX_PER_PORT; ++ tx->quad_offset = (port % ICE_PORTS_PER_QUAD) * INDEX_PER_PORT; + tx->len = INDEX_PER_PORT; + + return ice_ptp_alloc_tx_tracker(tx); +diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.h b/drivers/net/ethernet/intel/ice/ice_ptp.h +index afd048d699598170cc5850e21cb80e5206710ae5..10e396abf13094cc633b5baf8a05124b94a18534 100644 +--- a/drivers/net/ethernet/intel/ice/ice_ptp.h ++++ b/drivers/net/ethernet/intel/ice/ice_ptp.h +@@ -49,6 +49,37 @@ struct ice_perout_channel { + * To allow multiple ports to access the shared register block independently, + * the blocks are split up so that indexes are assigned to each port based on + * hardware logical port number. ++ * ++ * The timestamp blocks are handled differently for E810- and E822-based ++ * devices. In E810 devices, each port has its own block of timestamps, while in ++ * E822 there is a need to logically break the block of registers into smaller ++ * chunks based on the port number to avoid collisions. ++ * ++ * Example for port 5 in E810: ++ * +--------+--------+--------+--------+--------+--------+--------+--------+ ++ * |register|register|register|register|register|register|register|register| ++ * | block | block | block | block | block | block | block | block | ++ * | for | for | for | for | for | for | for | for | ++ * | port 0 | port 1 | port 2 | port 3 | port 4 | port 5 | port 6 | port 7 | ++ * +--------+--------+--------+--------+--------+--------+--------+--------+ ++ * ^^ ++ * || ++ * |--- quad offset is always 0 ++ * ---- quad number ++ * ++ * Example for port 5 in E822: ++ * +-----------------------------+-----------------------------+ ++ * | register block for quad 0 | register block for quad 1 | ++ * |+------+------+------+------+|+------+------+------+------+| ++ * ||port 0|port 1|port 2|port 3|||port 0|port 1|port 2|port 3|| ++ * |+------+------+------+------+|+------+------+------+------+| ++ * +-----------------------------+-------^---------------------+ ++ * ^ | ++ * | --- quad offset* ++ * ---- quad number ++ * ++ * * PHY port 5 is port 1 in quad 1 ++ * + */ + + /** |