diff options
Diffstat (limited to '0105-drm-amdgpu-display-mst-limit_payload_to_be_updated_one_by_one.patch')
| -rw-r--r-- | 0105-drm-amdgpu-display-mst-limit_payload_to_be_updated_one_by_one.patch | 102 |
1 files changed, 102 insertions, 0 deletions
diff --git a/0105-drm-amdgpu-display-mst-limit_payload_to_be_updated_one_by_one.patch b/0105-drm-amdgpu-display-mst-limit_payload_to_be_updated_one_by_one.patch new file mode 100644 index 000000000000..c81937d34a6b --- /dev/null +++ b/0105-drm-amdgpu-display-mst-limit_payload_to_be_updated_one_by_one.patch @@ -0,0 +1,102 @@ +From 50811dff5e09b96380a305d5e44de1f17d9cd7c0 Mon Sep 17 00:00:00 2001 +From: Wayne Lin <Wayne.Lin@amd.com> +Date: Fri, 9 Dec 2022 19:05:33 +0800 +Subject: [PATCH] drm/amdgpu/display/mst: limit payload to be updated one by + one + +[Why] +amdgpu expects to update payload table for one stream one time +by calling dm_helpers_dp_mst_write_payload_allocation_table(). +Currently, it get modified to try to update HW payload table +at once by referring mst_state. + +[How] +This is just a quick workaround. Should find way to remove the +temporary struct dc_dp_mst_stream_allocation_table later if set +struct link_mst_stream_allocatio directly is possible. + +Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2171 +Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> +Signed-off-by: Harry Wentland <harry.wentland@amd.com> +Fixes: 4d07b0bc4034 ("drm/display/dp_mst: Move all payload info into the atomic state") +Cc: stable@vger.kernel.org # 6.1 +Acked-by: Harry Wentland <harry.wentland@amd.com> +--- + .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 51 ++++++++++++++----- + 1 file changed, 39 insertions(+), 12 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +index f72c013d3a5b05..16623f73ddbe69 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +@@ -120,23 +120,50 @@ enum dc_edid_status dm_helpers_parse_edid_caps( + } + + static void +-fill_dc_mst_payload_table_from_drm(struct drm_dp_mst_topology_state *mst_state, +- struct amdgpu_dm_connector *aconnector, ++fill_dc_mst_payload_table_from_drm(struct dc_link *link, ++ bool enable, ++ struct drm_dp_mst_atomic_payload *target_payload, + struct dc_dp_mst_stream_allocation_table *table) + { + struct dc_dp_mst_stream_allocation_table new_table = { 0 }; + struct dc_dp_mst_stream_allocation *sa; +- struct drm_dp_mst_atomic_payload *payload; ++ struct link_mst_stream_allocation_table copy_of_link_table = ++ link->mst_stream_alloc_table; ++ ++ int i; ++ int current_hw_table_stream_cnt = copy_of_link_table.stream_count; ++ struct link_mst_stream_allocation *dc_alloc; ++ ++ /* TODO: refactor to set link->mst_stream_alloc_table directly if possible.*/ ++ if (enable) { ++ dc_alloc = ++ ©_of_link_table.stream_allocations[current_hw_table_stream_cnt]; ++ dc_alloc->vcp_id = target_payload->vcpi; ++ dc_alloc->slot_count = target_payload->time_slots; ++ } else { ++ for (i = 0; i < copy_of_link_table.stream_count; i++) { ++ dc_alloc = ++ ©_of_link_table.stream_allocations[i]; ++ ++ if (dc_alloc->vcp_id == target_payload->vcpi) { ++ dc_alloc->vcp_id = 0; ++ dc_alloc->slot_count = 0; ++ break; ++ } ++ } ++ ASSERT(i != copy_of_link_table.stream_count); ++ } + + /* Fill payload info*/ +- list_for_each_entry(payload, &mst_state->payloads, next) { +- if (payload->delete) +- continue; +- +- sa = &new_table.stream_allocations[new_table.stream_count]; +- sa->slot_count = payload->time_slots; +- sa->vcp_id = payload->vcpi; +- new_table.stream_count++; ++ for (i = 0; i < MAX_CONTROLLER_NUM; i++) { ++ dc_alloc = ++ ©_of_link_table.stream_allocations[i]; ++ if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) { ++ sa = &new_table.stream_allocations[new_table.stream_count]; ++ sa->slot_count = dc_alloc->slot_count; ++ sa->vcp_id = dc_alloc->vcp_id; ++ new_table.stream_count++; ++ } + } + + /* Overwrite the old table */ +@@ -185,7 +212,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( + * AUX message. The sequence is slot 1-63 allocated sequence for each + * stream. AMD ASIC stream slot allocation should follow the same + * sequence. copy DRM MST allocation to dc */ +- fill_dc_mst_payload_table_from_drm(mst_state, aconnector, proposed_table); ++ fill_dc_mst_payload_table_from_drm(stream->link, enable, payload, proposed_table); + + return true; + } |