diff options
| -rw-r--r-- | .SRCINFO | 20 | ||||
| -rw-r--r-- | 0011-dts-h6-tqc-a01-cpu-opp-2ghz.patch | 2 | ||||
| -rw-r--r-- | 0012-arm64-h6-gpu-devfreq-enable.patch | 148 | ||||
| -rw-r--r-- | 0040-wip-H6-deinterlace.patch | 1364 | ||||
| -rw-r--r-- | 0041-arm64-dts-h6-deinterlace.patch | 32 | ||||
| -rw-r--r-- | PKGBUILD | 17 | ||||
| -rw-r--r-- | config | 1026 |
7 files changed, 1592 insertions, 1017 deletions
@@ -1,5 +1,5 @@ pkgbase = linux-tqc-a01 - pkgver = 5.13.9 + pkgver = 5.13.10 pkgrel = 1 url = http://www.kernel.org/ arch = aarch64 @@ -28,11 +28,14 @@ pkgbase = linux-tqc-a01 source = 0006-drm-sun4i-Add-GEM-allocator.patch source = 0010-general-h6-add-dma-i2c-ir-spi-uart.patch source = 0011-dts-h6-tqc-a01-cpu-opp-2ghz.patch + source = 0012-arm64-h6-gpu-devfreq-enable.patch + source = 0040-wip-H6-deinterlace.patch + source = 0041-arm64-dts-h6-deinterlace.patch source = config source = linux.preset source = 60-linux.hook source = 90-linux.hook - source = https://cdn.kernel.org/pub/linux/kernel/v5.x/patch-5.13.9.xz + source = https://cdn.kernel.org/pub/linux/kernel/v5.x/patch-5.13.10.xz md5sums = 76c60fb304510a7bbd9c838790bc5fe4 md5sums = 46d921dba031a9f397955a787c71911e md5sums = 17aa0c69176c68cd98b4522740a1b747 @@ -46,12 +49,15 @@ pkgbase = linux-tqc-a01 md5sums = 335382823f6dc2aae2f6038b7aee339e md5sums = cb38b30491472097c3b9b475de39127f md5sums = bc65c0b9e4d6fb2fe3a81b8358886885 - md5sums = 6637a33cfc563c8f1ccff00cfd5b39c5 - md5sums = a5564b07e7a88dc6211d647c7949904d + md5sums = 74baf0cb243b3abd5e38f0131c95408f + md5sums = 05c4d9cbe622d5ff15e6b84b1c5c1a70 + md5sums = d1543c205b4faf9be4552d4308228217 + md5sums = e4ef0ae46cdfb23abb11d729452f68b2 + md5sums = 75b51f71570f7ee1a7a18cfa05b67edd md5sums = 66e0ae63183426b28c0ec0c7e10b5e16 md5sums = ce6c81ad1ad1f8b333fd6077d47abdaf md5sums = 3dc88030a8f2f5a5f97266d99b149f77 - md5sums = 39a5d2b3ff92c000dc93f9fa2efb2c45 + md5sums = 4d745d474d07277daee24107239c8902 pkgname = linux-tqc-a01 pkgdesc = The Linux Kernel and modules - AArch64 kernel for TQC A01 @@ -61,7 +67,7 @@ pkgname = linux-tqc-a01 depends = kmod depends = mkinitcpio>=0.7 optdepends = crda: to set the correct wireless channels of your country - provides = linux=5.13.9 + provides = linux=5.13.10 provides = WIREGUARD-MODULE conflicts = linux replaces = linux-armv8 @@ -69,5 +75,5 @@ pkgname = linux-tqc-a01 pkgname = linux-tqc-a01-headers pkgdesc = Header files and scripts for building modules for linux kernel - AArch64 kernel for TQC A01 - provides = linux-headers=5.13.9 + provides = linux-headers=5.13.10 conflicts = linux-headers diff --git a/0011-dts-h6-tqc-a01-cpu-opp-2ghz.patch b/0011-dts-h6-tqc-a01-cpu-opp-2ghz.patch index 3d43242d70e0..b44aed025e70 100644 --- a/0011-dts-h6-tqc-a01-cpu-opp-2ghz.patch +++ b/0011-dts-h6-tqc-a01-cpu-opp-2ghz.patch @@ -159,7 +159,7 @@ index e3e01fa..a2f6364 100644 regulator-always-on; regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1160000>; -+ regulator-max-microvolt = <0x129da0>; ++ regulator-max-microvolt = <1220000>; regulator-ramp-delay = <2500>; regulator-name = "vdd-cpu"; }; diff --git a/0012-arm64-h6-gpu-devfreq-enable.patch b/0012-arm64-h6-gpu-devfreq-enable.patch new file mode 100644 index 000000000000..589a8df898e4 --- /dev/null +++ b/0012-arm64-h6-gpu-devfreq-enable.patch @@ -0,0 +1,148 @@ +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index d422353..c71f886 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -204,6 +204,8 @@ gpu: gpu@1800000 { + clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; + clock-names = "core", "bus"; + resets = <&ccu RST_BUS_GPU>; ++ operating-points-v2 = <&gpu_opp_table>; ++ #cooling-cells = <2>; + status = "disabled"; + }; + +@@ -1176,6 +1178,105 @@ gpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 1>; ++ trips { ++ gpu_alert: gpu-alert { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ gpu-crit { ++ temperature = <100000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&gpu_alert>; ++ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++ }; ++ }; ++ ++ gpu_opp_table: gpu-opp-table { ++ compatible = "operating-points-v2"; ++ ++ opp@216000000 { ++ opp-hz = /bits/ 64 <216000000>; ++ opp-microvolt = <810000 810000 1200000>; ++ }; ++ ++ opp@264000000 { ++ opp-hz = /bits/ 64 <264000000>; ++ opp-microvolt = <810000 810000 1200000>; ++ }; ++ ++ opp@312000000 { ++ opp-hz = /bits/ 64 <312000000>; ++ opp-microvolt = <810000 810000 1200000>; ++ }; ++ ++ opp@336000000 { ++ opp-hz = /bits/ 64 <336000000>; ++ opp-microvolt = <810000 810000 1200000>; ++ }; ++ ++ opp@360000000 { ++ opp-hz = /bits/ 64 <360000000>; ++ opp-microvolt = <820000 820000 1200000>; ++ }; ++ ++ opp@384000000 { ++ opp-hz = /bits/ 64 <384000000>; ++ opp-microvolt = <830000 830000 1200000>; ++ }; ++ ++ opp@408000000 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <840000 840000 1200000>; ++ }; ++ ++ opp@420000000 { ++ opp-hz = /bits/ 64 <420000000>; ++ opp-microvolt = <850000 850000 1200000>; ++ }; ++ ++ opp@432000000 { ++ opp-hz = /bits/ 64 <432000000>; ++ opp-microvolt = <860000 860000 1200000>; ++ }; ++ ++ opp@456000000 { ++ opp-hz = /bits/ 64 <456000000>; ++ opp-microvolt = <870000 870000 1200000>; ++ }; ++ ++ opp@504000000 { ++ opp-hz = /bits/ 64 <504000000>; ++ opp-microvolt = <890000 890000 1200000>; ++ }; ++ ++ opp@540000000 { ++ opp-hz = /bits/ 64 <540000000>; ++ opp-microvolt = <910000 910000 1200000>; ++ }; ++ ++ opp@576000000 { ++ opp-hz = /bits/ 64 <576000000>; ++ opp-microvolt = <930000 930000 1200000>; ++ }; ++ ++ opp@624000000 { ++ opp-hz = /bits/ 64 <624000000>; ++ opp-microvolt = <950000 950000 1200000>; ++ }; ++ ++ opp@756000000 { ++ opp-hz = /bits/ 64 <756000000>; ++ opp-microvolt = <1040000 1040000 1200000>; + }; + }; + }; +diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +index 199ab77..db61727 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c ++++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +@@ -299,7 +299,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670, + 0, 3, /* M */ + 24, 1, /* mux */ + BIT(31), /* gate */ +- CLK_SET_RATE_PARENT); ++ 0); + + static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2", + 0x67c, BIT(0), 0); +@@ -1240,6 +1240,15 @@ static int sun50i_h6_ccu_probe(struct platform_device *pdev) + val |= BIT(24); + writel(val, reg + SUN50I_H6_HDMI_CEC_CLK_REG); + ++ /* ++ * Enforce n = 62 m = 1 p = 0 for GPU PLL = 756MHz ++ */ ++ ++ val = readl(reg + SUN50I_H6_PLL_GPU_REG); ++ val &= ~(GENMASK(8, 8) | BIT(1) | BIT(0)); ++ val |= (62 << 8) | BIT(1); ++ writel(val, reg + SUN50I_H6_PLL_GPU_REG); ++ + return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_h6_ccu_desc); + } + diff --git a/0040-wip-H6-deinterlace.patch b/0040-wip-H6-deinterlace.patch new file mode 100644 index 000000000000..b5bb79679e74 --- /dev/null +++ b/0040-wip-H6-deinterlace.patch @@ -0,0 +1,1364 @@ +From 91c70ea17b58c9205c35cd43a3dd8266bbe035b1 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec <jernej.skrabec@siol.net> +Date: Mon, 25 May 2020 19:06:07 +0200 +Subject: [PATCH 40/44] wip: H6 deinterlace + +Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> +--- + drivers/media/platform/Kconfig | 13 + + drivers/media/platform/sunxi/Makefile | 1 + + .../media/platform/sunxi/sun50i-di/Makefile | 2 + + .../platform/sunxi/sun50i-di/sun50i-di.c | 1134 +++++++++++++++++ + .../platform/sunxi/sun50i-di/sun50i-di.h | 172 +++ + 5 files changed, 1322 insertions(+) + create mode 100644 drivers/media/platform/sunxi/sun50i-di/Makefile + create mode 100644 drivers/media/platform/sunxi/sun50i-di/sun50i-di.c + create mode 100644 drivers/media/platform/sunxi/sun50i-di/sun50i-di.h + +--- a/drivers/media/platform/Kconfig ++++ b/drivers/media/platform/Kconfig +@@ -510,6 +510,19 @@ config VIDEO_QCOM_VENUS + on various Qualcomm SoCs. + To compile this driver as a module choose m here. + ++config VIDEO_SUN50I_DEINTERLACE ++ tristate "Allwinner Deinterlace v2 driver" ++ depends on VIDEO_DEV && VIDEO_V4L2 ++ depends on ARCH_SUNXI || COMPILE_TEST ++ depends on COMMON_CLK && OF ++ depends on PM ++ select VIDEOBUF2_DMA_CONTIG ++ select V4L2_MEM2MEM_DEV ++ help ++ Support for the Allwinner deinterlace v2 unit found on ++ some SoCs, like H6. ++ To compile this driver as a module choose m here. ++ + config VIDEO_SUN8I_DEINTERLACE + tristate "Allwinner Deinterlace driver" + depends on VIDEO_DEV && VIDEO_V4L2 +--- a/drivers/media/platform/sunxi/Makefile ++++ b/drivers/media/platform/sunxi/Makefile +@@ -3,4 +3,5 @@ + obj-y += sun4i-csi/ + obj-y += sun6i-csi/ + obj-y += sun8i-di/ ++obj-y += sun50i-di/ + obj-y += sun8i-rotate/ +--- /dev/null ++++ b/drivers/media/platform/sunxi/sun50i-di/Makefile +@@ -0,0 +1,2 @@ ++# SPDX-License-Identifier: GPL-2.0 ++obj-$(CONFIG_VIDEO_SUN50I_DEINTERLACE) += sun50i-di.o +--- /dev/null ++++ b/drivers/media/platform/sunxi/sun50i-di/sun50i-di.c +@@ -0,0 +1,1134 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Allwinner sun50i deinterlacer driver ++ * ++ * Copyright (C) 2020 Jernej Skrabec <jernej.skrabec@siol.net> ++ * ++ * Based on vim2m driver. ++ */ ++ ++#include <linux/clk.h> ++#include <linux/interrupt.h> ++#include <linux/io.h> ++#include <linux/iopoll.h> ++#include <linux/module.h> ++#include <linux/of.h> ++#include <linux/of_device.h> ++#include <linux/pm_runtime.h> ++#include <linux/reset.h> ++ ++#include <media/v4l2-device.h> ++#include <media/v4l2-ioctl.h> ++#include <media/v4l2-mem2mem.h> ++ ++#include "sun50i-di.h" ++ ++#define FLAG_SIZE (DEINTERLACE_MAX_WIDTH * DEINTERLACE_MAX_HEIGHT / 4) ++ ++static u32 deinterlace_formats[] = { ++ V4L2_PIX_FMT_NV12, ++ V4L2_PIX_FMT_NV21, ++ V4L2_PIX_FMT_YUV420, ++ V4L2_PIX_FMT_NV16, ++ V4L2_PIX_FMT_NV61, ++ V4L2_PIX_FMT_YUV422P ++}; ++ ++static inline u32 deinterlace_read(struct deinterlace_dev *dev, u32 reg) ++{ ++ return readl(dev->base + reg); ++} ++ ++static inline void deinterlace_write(struct deinterlace_dev *dev, ++ u32 reg, u32 value) ++{ ++ writel(value, dev->base + reg); ++} ++ ++static inline void deinterlace_set_bits(struct deinterlace_dev *dev, ++ u32 reg, u32 bits) ++{ ++ u32 val = readl(dev->base + reg); ++ ++ val |= bits; ++ ++ writel(val, dev->base + reg); ++} ++ ++static inline void deinterlace_clr_set_bits(struct deinterlace_dev *dev, ++ u32 reg, u32 clr, u32 set) ++{ ++ u32 val = readl(dev->base + reg); ++ ++ val &= ~clr; ++ val |= set; ++ ++ writel(val, dev->base + reg); ++} ++ ++static void deinterlace_device_run(void *priv) ++{ ++ u32 width, height, reg, msk, pitch[3], offset[2], fmt; ++ dma_addr_t buf, prev, curr, next, addr[4][3]; ++ struct deinterlace_ctx *ctx = priv; ++ struct deinterlace_dev *dev = ctx->dev; ++ struct vb2_v4l2_buffer *src, *dst; ++ unsigned int val; ++ bool motion; ++ ++ src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); ++ dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); ++ ++ v4l2_m2m_buf_copy_metadata(src, dst, true); ++ ++ fmt = ctx->src_fmt.pixelformat; ++ ++ deinterlace_write(dev, DEINTERLACE_IN_FLAG_ADDR, ctx->flag1_buf_dma); ++ deinterlace_write(dev, DEINTERLACE_OUT_FLAG_ADDR, ctx->flag2_buf_dma); ++ deinterlace_write(dev, DEINTERLACE_FLAG_ADDRH, 0); ++ deinterlace_write(dev, DEINTERLACE_FLAG_PITCH, 0x200); ++ ++ width = ctx->src_fmt.width; ++ height = ctx->src_fmt.height; ++ ++ reg = DEINTERLACE_SIZE_WIDTH(width); ++ reg |= DEINTERLACE_SIZE_HEIGHT(height); ++ deinterlace_write(dev, DEINTERLACE_SIZE, reg); ++ ++ switch (fmt) { ++ case V4L2_PIX_FMT_NV12: ++ case V4L2_PIX_FMT_NV21: ++ reg = DEINTERLACE_FORMAT_YUV420SP; ++ break; ++ case V4L2_PIX_FMT_YUV420: ++ reg = DEINTERLACE_FORMAT_YUV420P; ++ break; ++ case V4L2_PIX_FMT_NV16: ++ case V4L2_PIX_FMT_NV61: ++ reg = DEINTERLACE_FORMAT_YUV422SP; ++ break; ++ case V4L2_PIX_FMT_YUV422P: ++ reg = DEINTERLACE_FORMAT_YUV422P; ++ break; ++ } ++ deinterlace_write(dev, DEINTERLACE_FORMAT, reg); ++ ++ pitch[0] = ctx->src_fmt.bytesperline; ++ switch (fmt) { ++ case V4L2_PIX_FMT_YUV420: ++ case V4L2_PIX_FMT_YUV422P: ++ pitch[1] = pitch[0] / 2; ++ pitch[2] = pitch[1]; ++ break; ++ case V4L2_PIX_FMT_NV12: ++ case V4L2_PIX_FMT_NV21: ++ case V4L2_PIX_FMT_NV16: ++ case V4L2_PIX_FMT_NV61: ++ pitch[1] = pitch[0]; ++ pitch[2] = 0; ++ break; ++ } ++ ++ deinterlace_write(dev, DEINTERLACE_IN_PITCH0, pitch[0] * 2); ++ deinterlace_write(dev, DEINTERLACE_IN_PITCH1, pitch[1] * 2); ++ deinterlace_write(dev, DEINTERLACE_IN_PITCH2, pitch[2] * 2); ++ deinterlace_write(dev, DEINTERLACE_OUT_PITCH0, pitch[0]); ++ deinterlace_write(dev, DEINTERLACE_OUT_PITCH1, pitch[1]); ++ deinterlace_write(dev, DEINTERLACE_OUT_PITCH2, pitch[2]); ++ ++ offset[0] = pitch[0] * height; ++ switch (fmt) { ++ case V4L2_PIX_FMT_YUV420: ++ offset[1] = offset[0] + offset[0] / 4; ++ break; ++ case V4L2_PIX_FMT_YUV422P: ++ offset[1] = offset[0] + offset[0] / 2; ++ break; ++ default: ++ offset[1] = 0; ++ break; ++ } ++ ++ buf = vb2_dma_contig_plane_dma_addr(&src->vb2_buf, 0); ++ next = buf; ++ if (ctx->prev[0]) ++ buf = vb2_dma_contig_plane_dma_addr(&ctx->prev[0]->vb2_buf, 0); ++ curr = buf; ++ if (ctx->prev[1]) ++ buf = vb2_dma_contig_plane_dma_addr(&ctx->prev[1]->vb2_buf, 0); ++ prev = buf; ++ ++ if (ctx->first_field == 0) { ++ if (ctx->field == 0) { ++ addr[0][0] = prev; ++ addr[0][1] = prev + offset[0]; ++ addr[0][2] = prev + offset[1]; ++ addr[1][0] = prev + pitch[0]; ++ addr[1][1] = prev + offset[0] + pitch[1]; ++ addr[1][2] = prev + offset[1] + pitch[2]; ++ addr[2][0] = curr; ++ addr[2][1] = curr + offset[0]; ++ addr[2][2] = curr + offset[1]; ++ addr[3][0] = curr + pitch[0]; ++ addr[3][1] = curr + offset[0] + pitch[1]; ++ addr[3][2] = curr + offset[1] + pitch[2]; ++ } else { ++ addr[0][0] = prev + pitch[0]; ++ addr[0][1] = prev + offset[0] + pitch[1]; ++ addr[0][2] = prev + offset[1] + pitch[2]; ++ addr[1][0] = curr; ++ addr[1][1] = curr + offset[0]; ++ addr[1][2] = curr + offset[1]; ++ addr[2][0] = curr + pitch[0]; ++ addr[2][1] = curr + offset[0] + pitch[1]; ++ addr[2][2] = curr + offset[1] + pitch[2]; ++ addr[3][0] = next; ++ addr[3][1] = next + offset[0]; ++ addr[3][2] = next + offset[1]; ++ } ++ } else { ++ if (ctx->field == 0) { ++ addr[0][0] = prev; ++ addr[0][1] = prev + offset[0]; ++ addr[0][2] = prev + offset[1]; ++ addr[1][0] = curr + pitch[0]; ++ addr[1][1] = curr + offset[0] + pitch[1]; ++ addr[1][2] = curr + offset[1] + pitch[2]; ++ addr[2][0] = curr; ++ addr[2][1] = curr + offset[0]; ++ addr[2][2] = curr + offset[1]; ++ addr[3][0] = next + pitch[0]; ++ addr[3][1] = next + offset[0] + pitch[1]; ++ addr[3][2] = next + offset[1] + pitch[2]; ++ } else { ++ addr[0][0] = prev + pitch[0]; ++ addr[0][1] = prev + offset[0] + pitch[1]; ++ addr[0][2] = prev + offset[1] + pitch[2]; ++ addr[1][0] = prev; ++ addr[1][1] = prev + offset[0]; ++ addr[1][2] = prev + offset[1]; ++ addr[2][0] = curr + pitch[0]; ++ addr[2][1] = curr + offset[0] + pitch[1]; ++ addr[2][2] = curr + offset[1] + pitch[2]; ++ addr[3][0] = curr; ++ addr[3][1] = curr + offset[0]; ++ addr[3][2] = curr + offset[1]; ++ } ++ } ++ ++ deinterlace_write(dev, DEINTERLACE_IN0_ADDR0, addr[0][0]); ++ deinterlace_write(dev, DEINTERLACE_IN0_ADDR1, addr[0][1]); ++ deinterlace_write(dev, DEINTERLACE_IN0_ADDR2, addr[0][2]); ++ ++ deinterlace_write(dev, DEINTERLACE_IN1_ADDR0, addr[1][0]); ++ deinterlace_write(dev, DEINTERLACE_IN1_ADDR1, addr[1][1]); ++ deinterlace_write(dev, DEINTERLACE_IN1_ADDR2, addr[1][2]); ++ ++ deinterlace_write(dev, DEINTERLACE_IN2_ADDR0, addr[2][0]); ++ deinterlace_write(dev, DEINTERLACE_IN2_ADDR1, addr[2][1]); ++ deinterlace_write(dev, DEINTERLACE_IN2_ADDR2, addr[2][2]); ++ ++ deinterlace_write(dev, DEINTERLACE_IN3_ADDR0, addr[3][0]); ++ deinterlace_write(dev, DEINTERLACE_IN3_ADDR1, addr[3][1]); ++ deinterlace_write(dev, DEINTERLACE_IN3_ADDR2, addr[3][2]); ++ ++ buf = vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0); ++ deinterlace_write(dev, DEINTERLACE_OUT_ADDR0, buf); ++ deinterlace_write(dev, DEINTERLACE_OUT_ADDR1, buf + offset[0]); ++ deinterlace_write(dev, DEINTERLACE_OUT_ADDR2, buf + offset[1]); ++ ++ if (ctx->first_field == 0) ++ val = 4; ++ else ++ val = 5; ++ ++ reg = DEINTERLACE_INTP_PARAM0_LUMA_CUR_FAC_MODE(val); ++ reg |= DEINTERLACE_INTP_PARAM0_CHROMA_CUR_FAC_MODE(val); ++ msk = DEINTERLACE_INTP_PARAM0_LUMA_CUR_FAC_MODE_MSK; ++ msk |= DEINTERLACE_INTP_PARAM0_CHROMA_CUR_FAC_MODE_MSK; ++ deinterlace_clr_set_bits(dev, DEINTERLACE_INTP_PARAM0, msk, reg); ++ ++ reg = DEINTERLACE_POLAR_FIELD(ctx->field); ++ deinterlace_write(dev, DEINTERLACE_POLAR, reg); ++ ++ motion = ctx->prev[0] && ctx->prev[1]; ++ reg = DEINTERLACE_MODE_DEINT_LUMA; ++ if (motion) ++ reg |= DEINTERLACE_MODE_MOTION_EN; ++ reg |= DEINTERLACE_MODE_INTP_EN; ++ reg |= DEINTERLACE_MODE_AUTO_UPD_MODE(ctx->first_field); ++ reg |= DEINTERLACE_MODE_DEINT_CHROMA; ++ if (!motion) ++ reg |= DEINTERLACE_MODE_FIELD_MODE; ++ deinterlace_write(dev, DEINTERLACE_MODE, reg); ++ ++ deinterlace_set_bits(dev, DEINTERLACE_INT_CTRL, ++ DEINTERLACE_INT_EN); ++ ++ deinterlace_set_bits(dev, DEINTERLACE_CTRL, ++ DEINTERLACE_CTRL_START); ++} ++ ++static int deinterlace_job_ready(void *priv) ++{ ++ struct deinterlace_ctx *ctx = priv; ++ ++ return v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) >= 1 && ++ v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) >= 2; ++} ++ ++static void deinterlace_job_abort(void *priv) ++{ ++ struct deinterlace_ctx *ctx = priv; ++ ++ /* Will cancel the transaction in the next interrupt handler */ ++ ctx->aborting = 1; ++} ++ ++static irqreturn_t deinterlace_irq(int irq, void *data) ++{ ++ struct deinterlace_dev *dev = data; ++ struct vb2_v4l2_buffer *src, *dst; ++ struct deinterlace_ctx *ctx; ++ unsigned int val; ++ ++ ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev); ++ if (!ctx) { ++ v4l2_err(&dev->v4l2_dev, ++ "Instance released before the end of transaction\n"); ++ return IRQ_NONE; ++ } ++ ++ val = deinterlace_read(dev, DEINTERLACE_STATUS); ++ if (!(val & DEINTERLACE_STATUS_FINISHED)) ++ return IRQ_NONE; ++ ++ deinterlace_write(dev, DEINTERLACE_INT_CTRL, 0); ++ deinterlace_set_bits(dev, DEINTERLACE_STATUS, ++ DEINTERLACE_STATUS_FINISHED); ++ deinterlace_clr_set_bits(dev, DEINTERLACE_CTRL, ++ DEINTERLACE_CTRL_START, 0); ++ ++ dst = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); ++ v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE); ++ ++ if (ctx->field != ctx->first_field || ctx->aborting) { ++ ctx->field = ctx->first_field; ++ ++ src = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); ++ if (ctx->prev[1]) ++ v4l2_m2m_buf_done(ctx->prev[1], VB2_BUF_STATE_DONE); ++ ctx->prev[1] = ctx->prev[0]; ++ ctx->prev[0] = src; ++ ++ v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx); ++ } else { ++ ctx->field = !ctx->first_field; ++ deinterlace_device_run(ctx); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static void deinterlace_init(struct deinterlace_dev *dev) ++{ ++ u32 reg; ++ ++ deinterlace_write(dev, DEINTERLACE_OUT_PATH, 0); ++ ++ reg = DEINTERLACE_MD_PARAM0_MIN_LUMA_TH(4); ++ reg |= DEINTERLACE_MD_PARAM0_MAX_LUMA_TH(12); ++ reg |= DEINTERLACE_MD_PARAM0_AVG_LUMA_SHIFT(6); ++ reg |= DEINTERLACE_MD_PARAM0_TH_SHIFT(1); ++ deinterlace_write(dev, DEINTERLACE_MD_PARAM0, reg); ++ ++ reg = DEINTERLACE_MD_PARAM1_MOV_FAC_NONEDGE(2); ++ deinterlace_write(dev, DEINTERLACE_MD_PARAM1, reg); ++ ++ reg = DEINTERLACE_MD_PARAM2_CHROMA_SPATIAL_TH(128); ++ reg |= DEINTERLACE_MD_PARAM2_CHROMA_DIFF_TH(5); ++ reg |= DEINTERLACE_MD_PARAM2_PIX_STATIC_TH(3); ++ deinterlace_write(dev, DEINTERLACE_MD_PARAM2, reg); ++ ++ reg = DEINTERLACE_INTP_PARAM0_ANGLE_LIMIT(20); ++ reg |= DEINTERLACE_INTP_PARAM0_ANGLE_CONST_TH(5); ++ reg |= DEINTERLACE_INTP_PARAM0_LUMA_CUR_FAC_MODE(1); ++ reg |= DEINTERLACE_INTP_PARAM0_CHROMA_CUR_FAC_MODE(1); ++ deinterlace_write(dev, DEINTERLACE_INTP_PARAM0, reg); ++ ++ reg = DEINTERLACE_MD_CH_PARAM_BLEND_MODE(1); ++ reg |= DEINTERLACE_MD_CH_PARAM_FONT_PRO_EN; ++ reg |= DEINTERLACE_MD_CH_PARAM_FONT_PRO_TH(48); ++ reg |= DEINTERLACE_MD_CH_PARAM_FONT_PRO_FAC(4); ++ deinterlace_write(dev, DEINTERLACE_MD_CH_PARAM, reg); ++ ++ reg = DEINTERLACE_INTP_PARAM1_A(4); ++ reg |= DEINTERLACE_INTP_PARAM1_EN; ++ reg |= DEINTERLACE_INTP_PARAM1_C(10); ++ reg |= DEINTERLACE_INTP_PARAM1_CMAX(64); ++ reg |= DEINTERLACE_INTP_PARAM1_MAXRAT(2); ++ deinterlace_write(dev, DEINTERLACE_INTP_PARAM1, reg); ++ ++ /* only 32-bit addresses are supported, so high bits are always 0 */ ++ deinterlace_write(dev, DEINTERLACE_IN0_ADDRH, 0); ++ deinterlace_write(dev, DEINTERLACE_IN1_ADDRH, 0); ++ deinterlace_write(dev, DEINTERLACE_IN2_ADDRH, 0); ++ deinterlace_write(dev, DEINTERLACE_IN3_ADDRH, 0); ++ deinterlace_write(dev, DEINTERLACE_OUT_ADDRH, 0); ++} ++ ++static inline struct deinterlace_ctx *deinterlace_file2ctx(struct file *file) ++{ ++ return container_of(file->private_data, struct deinterlace_ctx, fh); ++} ++ ++static bool deinterlace_check_format(u32 pixelformat) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(deinterlace_formats); i++) ++ if (deinterlace_formats[i] == pixelformat) ++ return true; ++ ++ return false; ++} ++ ++static void deinterlace_prepare_format(struct v4l2_pix_format *pix_fmt) ++{ ++ unsigned int bytesperline = pix_fmt->bytesperline; ++ unsigned int height = pix_fmt->height; ++ unsigned int width = pix_fmt->width; ++ unsigned int sizeimage; ++ ++ width = clamp(width, DEINTERLACE_MIN_WIDTH, ++ DEINTERLACE_MAX_WIDTH); ++ height = clamp(height, DEINTERLACE_MIN_HEIGHT, ++ DEINTERLACE_MAX_HEIGHT); ++ ++ /* try to respect userspace wishes about pitch */ ++ bytesperline = ALIGN(bytesperline, 2); ++ if (bytesperline < ALIGN(width, 2)) ++ bytesperline = ALIGN(width, 2); ++ ++ /* luma */ ++ sizeimage = bytesperline * height; ++ /* chroma */ ++ switch (pix_fmt->pixelformat) { ++ case V4L2_PIX_FMT_NV12: ++ case V4L2_PIX_FMT_NV21: ++ case V4L2_PIX_FMT_YUV420: ++ sizeimage += bytesperline * height / 2; ++ break; ++ case V4L2_PIX_FMT_NV16: ++ case V4L2_PIX_FMT_NV61: ++ case V4L2_PIX_FMT_YUV422P: ++ sizeimage += bytesperline * height; ++ break; ++ } ++ ++ if (pix_fmt->sizeimage < sizeimage) ++ pix_fmt->sizeimage = sizeimage; ++ ++ pix_fmt->width = width; ++ pix_fmt->height = height; ++ pix_fmt->bytesperline = bytesperline; ++} ++ ++static int deinterlace_querycap(struct file *file, void *priv, ++ struct v4l2_capability *cap) ++{ ++ strscpy(cap->driver, DEINTERLACE_NAME, sizeof(cap->driver)); ++ strscpy(cap->card, DEINTERLACE_NAME, sizeof(cap->card)); ++ snprintf(cap->bus_info, sizeof(cap->bus_info), ++ "platform:%s", DEINTERLACE_NAME); ++ ++ return 0; ++} ++ ++static int deinterlace_enum_fmt(struct file *file, void *priv, ++ struct v4l2_fmtdesc *f) ++{ ++ if (f->index < ARRAY_SIZE(deinterlace_formats)) { ++ f->pixelformat = deinterlace_formats[f->index]; ++ ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static int deinterlace_enum_framesizes(struct file *file, void *priv, ++ struct v4l2_frmsizeenum *fsize) ++{ ++ if (fsize->index != 0) ++ return -EINVAL; ++ ++ if (!deinterlace_check_format(fsize->pixel_format)) ++ return -EINVAL; ++ ++ fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; ++ fsize->stepwise.min_width = DEINTERLACE_MIN_WIDTH; ++ fsize->stepwise.min_height = DEINTERLACE_MIN_HEIGHT; ++ fsize->stepwise.max_width = DEINTERLACE_MAX_WIDTH; ++ fsize->stepwise.max_height = DEINTERLACE_MAX_HEIGHT; ++ fsize->stepwise.step_width = 2; ++ ++ switch (fsize->pixel_format) { ++ case V4L2_PIX_FMT_NV12: ++ case V4L2_PIX_FMT_NV21: ++ case V4L2_PIX_FMT_YUV420: ++ fsize->stepwise.step_height = 2; ++ break; ++ case V4L2_PIX_FMT_NV16: ++ case V4L2_PIX_FMT_NV61: ++ case V4L2_PIX_FMT_YUV422P: ++ fsize->stepwise.step_height = 1; ++ break; ++ } ++ ++ return 0; ++} ++ ++static int deinterlace_set_cap_format(struct deinterlace_ctx *ctx, ++ struct v4l2_pix_format *f) ++{ ++ if (!deinterlace_check_format(ctx->src_fmt.pixelformat)) ++ return -EINVAL; ++ ++ f->pixelformat = ctx->src_fmt.pixelformat; ++ f->field = V4L2_FIELD_NONE; ++ f->width = ctx->src_fmt.width; ++ f->height = ctx->src_fmt.height; ++ ++ deinterlace_prepare_format(f); ++ ++ return 0; ++} ++ ++static int deinterlace_g_fmt_vid_cap(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct deinterlace_ctx *ctx = deinterlace_file2ctx(file); ++ ++ f->fmt.pix = ctx->dst_fmt; ++ ++ return 0; ++} ++ ++static int deinterlace_g_fmt_vid_out(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct deinterlace_ctx *ctx = deinterlace_file2ctx(file); ++ ++ f->fmt.pix = ctx->src_fmt; ++ ++ return 0; ++} ++ ++static int deinterlace_try_fmt_vid_cap(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct deinterlace_ctx *ctx = deinterlace_file2ctx(file); ++ ++ return deinterlace_set_cap_format(ctx, &f->fmt.pix); ++} ++ ++static int deinterlace_try_fmt_vid_out(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ if (!deinterlace_check_format(f->fmt.pix.pixelformat)) ++ f->fmt.pix.pixelformat = deinterlace_formats[0]; ++ ++ if (f->fmt.pix.field != V4L2_FIELD_INTERLACED_TB && ++ f->fmt.pix.field != V4L2_FIELD_INTERLACED_BT && ++ f->fmt.pix.field != V4L2_FIELD_INTERLACED) ++ f->fmt.pix.field = V4L2_FIELD_INTERLACED; ++ ++ deinterlace_prepare_format(&f->fmt.pix); ++ ++ return 0; ++} ++ ++static int deinterlace_s_fmt_vid_cap(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct deinterlace_ctx *ctx = deinterlace_file2ctx(file); ++ struct vb2_queue *vq; ++ int ret; ++ ++ ret = deinterlace_try_fmt_vid_cap(file, priv, f); ++ if (ret) ++ return ret; ++ ++ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); ++ if (vb2_is_busy(vq)) ++ return -EBUSY; ++ ++ ctx->dst_fmt = f->fmt.pix; ++ ++ return 0; ++} ++ ++static int deinterlace_s_fmt_vid_out(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct deinterlace_ctx *ctx = deinterlace_file2ctx(file); ++ struct vb2_queue *vq; ++ int ret; ++ ++ ret = deinterlace_try_fmt_vid_out(file, priv, f); ++ if (ret) ++ return ret; ++ ++ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); ++ if (vb2_is_busy(vq)) ++ return -EBUSY; ++ ++ /* ++ * Capture queue has to be also checked, because format and size ++ * depends on output format and size. ++ */ ++ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE); ++ if (vb2_is_busy(vq)) ++ return -EBUSY; ++ ++ ctx->src_fmt = f->fmt.pix; ++ ++ /* Propagate colorspace information to capture. */ ++ ctx->dst_fmt.colorspace = f->fmt.pix.colorspace; ++ ctx->dst_fmt.xfer_func = f->fmt.pix.xfer_func; ++ ctx->dst_fmt.ycbcr_enc = f->fmt.pix.ycbcr_enc; ++ ctx->dst_fmt.quantization = f->fmt.pix.quantization; ++ ++ return deinterlace_set_cap_format(ctx, &ctx->dst_fmt); ++} ++ ++static const struct v4l2_ioctl_ops deinterlace_ioctl_ops = { ++ .vidioc_querycap = deinterlace_querycap, ++ ++ .vidioc_enum_framesizes = deinterlace_enum_framesizes, ++ ++ .vidioc_enum_fmt_vid_cap = deinterlace_enum_fmt, ++ .vidioc_g_fmt_vid_cap = deinterlace_g_fmt_vid_cap, ++ .vidioc_try_fmt_vid_cap = deinterlace_try_fmt_vid_cap, ++ .vidioc_s_fmt_vid_cap = deinterlace_s_fmt_vid_cap, ++ ++ .vidioc_enum_fmt_vid_out = deinterlace_enum_fmt, ++ .vidioc_g_fmt_vid_out = deinterlace_g_fmt_vid_out, ++ .vidioc_try_fmt_vid_out = deinterlace_try_fmt_vid_out, ++ .vidioc_s_fmt_vid_out = deinterlace_s_fmt_vid_out, ++ ++ .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, ++ .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, ++ .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, ++ .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, ++ .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, ++ .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, ++ .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, ++ ++ .vidioc_streamon = v4l2_m2m_ioctl_streamon, ++ .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, ++}; ++ ++static int deinterlace_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers, ++ unsigned int *nplanes, unsigned int sizes[], ++ struct device *alloc_devs[]) ++{ ++ struct deinterlace_ctx *ctx = vb2_get_drv_priv(vq); ++ struct v4l2_pix_format *pix_fmt; ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) ++ pix_fmt = &ctx->src_fmt; ++ else ++ pix_fmt = &ctx->dst_fmt; ++ ++ if (*nplanes) { ++ if (sizes[0] < pix_fmt->sizeimage) ++ return -EINVAL; ++ } else { ++ sizes[0] = pix_fmt->sizeimage; ++ *nplanes = 1; ++ } ++ ++ return 0; ++} ++ ++static int deinterlace_buf_prepare(struct vb2_buffer *vb) ++{ ++ struct vb2_queue *vq = vb->vb2_queue; ++ struct deinterlace_ctx *ctx = vb2_get_drv_priv(vq); ++ struct v4l2_pix_format *pix_fmt; ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) ++ pix_fmt = &ctx->src_fmt; ++ else ++ pix_fmt = &ctx->dst_fmt; ++ ++ if (vb2_plane_size(vb, 0) < pix_fmt->sizeimage) ++ return -EINVAL; ++ ++ vb2_set_plane_payload(vb, 0, pix_fmt->sizeimage); ++ ++ return 0; ++} ++ ++static void deinterlace_buf_queue(struct vb2_buffer *vb) ++{ ++ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); ++ struct deinterlace_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); ++ ++ v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf); ++} ++ ++static void deinterlace_queue_cleanup(struct vb2_queue *vq, u32 state) ++{ ++ struct deinterlace_ctx *ctx = vb2_get_drv_priv(vq); ++ struct vb2_v4l2_buffer *vbuf; ++ ++ do { ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) ++ vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); ++ else ++ vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); ++ ++ if (vbuf) ++ v4l2_m2m_buf_done(vbuf, state); ++ } while (vbuf); ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) { ++ if (ctx->prev[0]) ++ v4l2_m2m_buf_done(ctx->prev[0], state); ++ if (ctx->prev[1]) ++ v4l2_m2m_buf_done(ctx->prev[1], state); ++ } ++} ++ ++static int deinterlace_start_streaming(struct vb2_queue *vq, unsigned int count) ++{ ++ struct deinterlace_ctx *ctx = vb2_get_drv_priv(vq); ++ struct device *dev = ctx->dev->dev; ++ int ret; ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) { ++ ret = pm_runtime_get_sync(dev); ++ if (ret < 0) { ++ dev_err(dev, "Failed to enable module\n"); ++ ++ goto err_runtime_get; ++ } ++ ++ ctx->first_field = ++ ctx->src_fmt.field == V4L2_FIELD_INTERLACED_BT; ++ ctx->field = ctx->first_field; ++ ++ ctx->prev[0] = NULL; ++ ctx->prev[1] = NULL; ++ ctx->aborting = 0; ++ ++ ctx->flag1_buf = dma_alloc_coherent(dev, FLAG_SIZE, ++ &ctx->flag1_buf_dma, ++ GFP_KERNEL); ++ if (!ctx->flag1_buf) { ++ ret = -ENOMEM; ++ ++ goto err_no_mem1; ++ } ++ ++ ctx->flag2_buf = dma_alloc_coherent(dev, FLAG_SIZE, ++ &ctx->flag2_buf_dma, ++ GFP_KERNEL); ++ if (!ctx->flag2_buf) { ++ ret = -ENOMEM; ++ ++ goto err_no_mem2; ++ } ++ } ++ ++ return 0; ++ ++err_no_mem2: ++ dma_free_coherent(dev, FLAG_SIZE, ctx->flag1_buf, ++ ctx->flag1_buf_dma); ++err_no_mem1: ++ pm_runtime_put(dev); ++err_runtime_get: ++ deinterlace_queue_cleanup(vq, VB2_BUF_STATE_QUEUED); ++ ++ return ret; ++} ++ ++static void deinterlace_stop_streaming(struct vb2_queue *vq) ++{ ++ struct deinterlace_ctx *ctx = vb2_get_drv_priv(vq); ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) { ++ struct device *dev = ctx->dev->dev; ++ ++ dma_free_coherent(dev, FLAG_SIZE, ctx->flag1_buf, ++ ctx->flag1_buf_dma); ++ dma_free_coherent(dev, FLAG_SIZE, ctx->flag2_buf, ++ ctx->flag2_buf_dma); ++ ++ pm_runtime_put(dev); ++ } ++ ++ deinterlace_queue_cleanup(vq, VB2_BUF_STATE_ERROR); ++} ++ ++static const struct vb2_ops deinterlace_qops = { ++ .queue_setup = deinterlace_queue_setup, ++ .buf_prepare = deinterlace_buf_prepare, ++ .buf_queue = deinterlace_buf_queue, ++ .start_streaming = deinterlace_start_streaming, ++ .stop_streaming = deinterlace_stop_streaming, ++ .wait_prepare = vb2_ops_wait_prepare, ++ .wait_finish = vb2_ops_wait_finish, ++}; ++ ++static int deinterlace_queue_init(void *priv, struct vb2_queue *src_vq, ++ struct vb2_queue *dst_vq) ++{ ++ struct deinterlace_ctx *ctx = priv; ++ int ret; ++ ++ src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT; ++ src_vq->io_modes = VB2_MMAP | VB2_DMABUF; ++ src_vq->drv_priv = ctx; ++ src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); ++ src_vq->min_buffers_needed = 1; ++ src_vq->ops = &deinterlace_qops; ++ src_vq->mem_ops = &vb2_dma_contig_memops; ++ src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ++ src_vq->lock = &ctx->dev->dev_mutex; ++ src_vq->dev = ctx->dev->dev; ++ ++ ret = vb2_queue_init(src_vq); ++ if (ret) ++ return ret; ++ ++ dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; ++ dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; ++ dst_vq->drv_priv = ctx; ++ dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); ++ dst_vq->min_buffers_needed = 2; ++ dst_vq->ops = &deinterlace_qops; ++ dst_vq->mem_ops = &vb2_dma_contig_memops; ++ dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ++ dst_vq->lock = &ctx->dev->dev_mutex; ++ dst_vq->dev = ctx->dev->dev; ++ ++ ret = vb2_queue_init(dst_vq); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static int deinterlace_open(struct file *file) ++{ ++ struct deinterlace_dev *dev = video_drvdata(file); ++ struct deinterlace_ctx *ctx = NULL; ++ int ret; ++ ++ if (mutex_lock_interruptible(&dev->dev_mutex)) ++ return -ERESTARTSYS; ++ ++ ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); ++ if (!ctx) { ++ mutex_unlock(&dev->dev_mutex); ++ return -ENOMEM; ++ } ++ ++ /* default output format */ ++ ctx->src_fmt.pixelformat = deinterlace_formats[0]; ++ ctx->src_fmt.field = V4L2_FIELD_INTERLACED; ++ ctx->src_fmt.width = 640; ++ ctx->src_fmt.height = 480; ++ deinterlace_prepare_format(&ctx->src_fmt); ++ ++ /* default capture format */ ++ ctx->dst_fmt.pixelformat = deinterlace_formats[0]; ++ ctx->dst_fmt.field = V4L2_FIELD_NONE; ++ ctx->dst_fmt.width = 640; ++ ctx->dst_fmt.height = 480; ++ deinterlace_prepare_format(&ctx->dst_fmt); ++ ++ v4l2_fh_init(&ctx->fh, video_devdata(file)); ++ file->private_data = &ctx->fh; ++ ctx->dev = dev; ++ ++ ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, ++ &deinterlace_queue_init); ++ if (IS_ERR(ctx->fh.m2m_ctx)) { ++ ret = PTR_ERR(ctx->fh.m2m_ctx); ++ goto err_free; ++ } ++ ++ v4l2_fh_add(&ctx->fh); ++ ++ mutex_unlock(&dev->dev_mutex); ++ ++ return 0; ++ ++err_free: ++ kfree(ctx); ++ mutex_unlock(&dev->dev_mutex); ++ ++ return ret; ++} ++ ++static int deinterlace_release(struct file *file) ++{ ++ struct deinterlace_dev *dev = video_drvdata(file); ++ struct deinterlace_ctx *ctx = container_of(file->private_data, ++ struct deinterlace_ctx, fh); ++ ++ mutex_lock(&dev->dev_mutex); ++ ++ v4l2_fh_del(&ctx->fh); ++ v4l2_fh_exit(&ctx->fh); ++ v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); ++ ++ kfree(ctx); ++ ++ mutex_unlock(&dev->dev_mutex); ++ ++ return 0; ++} ++ ++static const struct v4l2_file_operations deinterlace_fops = { ++ .owner = THIS_MODULE, ++ .open = deinterlace_open, ++ .release = deinterlace_release, ++ .poll = v4l2_m2m_fop_poll, ++ .unlocked_ioctl = video_ioctl2, ++ .mmap = v4l2_m2m_fop_mmap, ++}; ++ ++static const struct video_device deinterlace_video_device = { ++ .name = DEINTERLACE_NAME, ++ .vfl_dir = VFL_DIR_M2M, ++ .fops = &deinterlace_fops, ++ .ioctl_ops = &deinterlace_ioctl_ops, ++ .minor = -1, ++ .release = video_device_release_empty, ++ .device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING, ++}; ++ ++static const struct v4l2_m2m_ops deinterlace_m2m_ops = { ++ .device_run = deinterlace_device_run, ++ .job_ready = deinterlace_job_ready, ++ .job_abort = deinterlace_job_abort, ++}; ++ ++static int deinterlace_probe(struct platform_device *pdev) ++{ ++ struct deinterlace_dev *dev; ++ struct video_device *vfd; ++ struct resource *res; ++ int irq, ret; ++ ++ dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); ++ if (!dev) ++ return -ENOMEM; ++ ++ dev->vfd = deinterlace_video_device; ++ dev->dev = &pdev->dev; ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq <= 0) ++ return irq; ++ ++ ret = devm_request_irq(dev->dev, irq, deinterlace_irq, ++ 0, dev_name(dev->dev), dev); ++ if (ret) { ++ dev_err(dev->dev, "Failed to request IRQ\n"); ++ ++ return ret; ++ } ++ ++ ret = of_dma_configure(dev->dev, dev->dev->of_node, true); ++ if (ret) ++ return ret; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ dev->base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(dev->base)) ++ return PTR_ERR(dev->base); ++ ++ dev->bus_clk = devm_clk_get(dev->dev, "bus"); ++ if (IS_ERR(dev->bus_clk)) { ++ dev_err(dev->dev, "Failed to get bus clock\n"); ++ ++ return PTR_ERR(dev->bus_clk); ++ } ++ ++ dev->mod_clk = devm_clk_get(dev->dev, "mod"); ++ if (IS_ERR(dev->mod_clk)) { ++ dev_err(dev->dev, "Failed to get mod clock\n"); ++ ++ return PTR_ERR(dev->mod_clk); ++ } ++ ++ dev->ram_clk = devm_clk_get(dev->dev, "ram"); ++ if (IS_ERR(dev->ram_clk)) { ++ dev_err(dev->dev, "Failed to get ram clock\n"); ++ ++ return PTR_ERR(dev->ram_clk); ++ } ++ ++ dev->rstc = devm_reset_control_get(dev->dev, NULL); ++ if (IS_ERR(dev->rstc)) { ++ dev_err(dev->dev, "Failed to get reset control\n"); ++ ++ return PTR_ERR(dev->rstc); ++ } ++ ++ mutex_init(&dev->dev_mutex); ++ ++ ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); ++ if (ret) { ++ dev_err(dev->dev, "Failed to register V4L2 device\n"); ++ ++ return ret; ++ } ++ ++ vfd = &dev->vfd; ++ vfd->lock = &dev->dev_mutex; ++ vfd->v4l2_dev = &dev->v4l2_dev; ++ ++ snprintf(vfd->name, sizeof(vfd->name), "%s", ++ deinterlace_video_device.name); ++ video_set_drvdata(vfd, dev); ++ ++ ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0); ++ if (ret) { ++ v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); ++ ++ goto err_v4l2; ++ } ++ ++ v4l2_info(&dev->v4l2_dev, ++ "Device registered as /dev/video%d\n", vfd->num); ++ ++ dev->m2m_dev = v4l2_m2m_init(&deinterlace_m2m_ops); ++ if (IS_ERR(dev->m2m_dev)) { ++ v4l2_err(&dev->v4l2_dev, ++ "Failed to initialize V4L2 M2M device\n"); ++ ret = PTR_ERR(dev->m2m_dev); ++ ++ goto err_video; ++ } ++ ++ platform_set_drvdata(pdev, dev); ++ ++ pm_runtime_enable(dev->dev); ++ ++ return 0; ++ ++err_video: ++ video_unregister_device(&dev->vfd); ++err_v4l2: ++ v4l2_device_unregister(&dev->v4l2_dev); ++ ++ return ret; ++} ++ ++static int deinterlace_remove(struct platform_device *pdev) ++{ ++ struct deinterlace_dev *dev = platform_get_drvdata(pdev); ++ ++ v4l2_m2m_release(dev->m2m_dev); ++ video_unregister_device(&dev->vfd); ++ v4l2_device_unregister(&dev->v4l2_dev); ++ ++ pm_runtime_force_suspend(&pdev->dev); ++ ++ return 0; ++} ++ ++static int deinterlace_runtime_resume(struct device *device) ++{ ++ struct deinterlace_dev *dev = dev_get_drvdata(device); ++ int ret; ++ ++ ret = clk_prepare_enable(dev->bus_clk); ++ if (ret) { ++ dev_err(dev->dev, "Failed to enable bus clock\n"); ++ ++ return ret; ++ } ++ ++ ret = clk_prepare_enable(dev->mod_clk); ++ if (ret) { ++ dev_err(dev->dev, "Failed to enable mod clock\n"); ++ ++ goto err_bus_clk; ++ } ++ ++ ret = clk_prepare_enable(dev->ram_clk); ++ if (ret) { ++ dev_err(dev->dev, "Failed to enable ram clock\n"); ++ ++ goto err_mod_clk; ++ } ++ ++ ret = reset_control_deassert(dev->rstc); ++ if (ret) { ++ dev_err(dev->dev, "Failed to apply reset\n"); ++ ++ goto err_ram_clk; ++ } ++ ++ deinterlace_init(dev); ++ ++ return 0; ++ ++err_ram_clk: ++ clk_disable_unprepare(dev->ram_clk); ++err_mod_clk: ++ clk_disable_unprepare(dev->mod_clk); ++err_bus_clk: ++ clk_disable_unprepare(dev->bus_clk); ++ ++ return ret; ++} ++ ++static int deinterlace_runtime_suspend(struct device *device) ++{ ++ struct deinterlace_dev *dev = dev_get_drvdata(device); ++ ++ reset_control_assert(dev->rstc); ++ ++ clk_disable_unprepare(dev->ram_clk); ++ clk_disable_unprepare(dev->mod_clk); ++ clk_disable_unprepare(dev->bus_clk); ++ ++ return 0; ++} ++ ++static const struct of_device_id deinterlace_dt_match[] = { ++ { .compatible = "allwinner,sun50i-h6-deinterlace" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, deinterlace_dt_match); ++ ++static const struct dev_pm_ops deinterlace_pm_ops = { ++ .runtime_resume = deinterlace_runtime_resume, ++ .runtime_suspend = deinterlace_runtime_suspend, ++}; ++ ++static struct platform_driver deinterlace_driver = { ++ .probe = deinterlace_probe, ++ .remove = deinterlace_remove, ++ .driver = { ++ .name = DEINTERLACE_NAME, ++ .of_match_table = deinterlace_dt_match, ++ .pm = &deinterlace_pm_ops, ++ }, ++}; ++module_platform_driver(deinterlace_driver); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>"); ++MODULE_DESCRIPTION("Allwinner Deinterlace driver"); +--- /dev/null ++++ b/drivers/media/platform/sunxi/sun50i-di/sun50i-di.h +@@ -0,0 +1,172 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Allwinner Deinterlace driver ++ * ++ * Copyright (C) 2020 Jernej Skrabec <jernej.skrabec@siol.net> ++ */ ++ ++#ifndef _SUN8I_DEINTERLACE_H_ ++#define _SUN8I_DEINTERLACE_H_ ++ ++#include <media/v4l2-device.h> ++#include <media/v4l2-mem2mem.h> ++#include <media/videobuf2-v4l2.h> ++#include <media/videobuf2-dma-contig.h> ++ ++#include <linux/platform_device.h> ++ ++#define DEINTERLACE_NAME "sun50i-di" ++ ++#define DEINTERLACE_CTRL 0x00 ++#define DEINTERLACE_CTRL_START BIT(0) ++#define DEINTERLACE_CTRL_IOMMU_EN BIT(16) ++#define DEINTERLACE_CTRL_RESET BIT(31) ++ ++#define DEINTERLACE_INT_CTRL 0x04 ++#define DEINTERLACE_INT_EN BIT(0) ++ ++#define DEINTERLACE_STATUS 0x08 ++#define DEINTERLACE_STATUS_FINISHED BIT(0) ++#define DEINTERLACE_STATUS_BUSY BIT(8) ++ ++#define DEINTERLACE_SIZE 0x10 ++#define DEINTERLACE_SIZE_WIDTH(w) \ ++ (((w) - 1) & 0x7ff) ++#define DEINTERLACE_SIZE_HEIGHT(h) \ ++ ((((h) - 1) & 0x7ff) << 16) ++ ++#define DEINTERLACE_FORMAT 0x14 ++#define DEINTERLACE_FORMAT_YUV420P 0 ++#define DEINTERLACE_FORMAT_YUV420SP 1 ++#define DEINTERLACE_FORMAT_YUV422P 2 ++#define DEINTERLACE_FORMAT_YUV422SP 3 ++ ++#define DEINTERLACE_POLAR 0x18 ++#define DEINTERLACE_POLAR_FIELD(x) ((x) & 1) ++ ++/* all pitch registers accept 16-bit values */ ++#define DEINTERLACE_IN_PITCH0 0x20 ++#define DEINTERLACE_IN_PITCH1 0x24 ++#define DEINTERLACE_IN_PITCH2 0x28 ++#define DEINTERLACE_OUT_PITCH0 0x30 ++#define DEINTERLACE_OUT_PITCH1 0x34 ++#define DEINTERLACE_OUT_PITCH2 0x38 ++#define DEINTERLACE_FLAG_PITCH 0x40 ++#define DEINTERLACE_IN0_ADDR0 0x50 ++#define DEINTERLACE_IN0_ADDR1 0x54 ++#define DEINTERLACE_IN0_ADDR2 0x58 ++#define DEINTERLACE_IN0_ADDRH 0x5c ++#define DEINTERLACE_IN1_ADDR0 0x60 ++#define DEINTERLACE_IN1_ADDR1 0x64 ++#define DEINTERLACE_IN1_ADDR2 0x68 ++#define DEINTERLACE_IN1_ADDRH 0x6c ++#define DEINTERLACE_IN2_ADDR0 0x70 ++#define DEINTERLACE_IN2_ADDR1 0x74 ++#define DEINTERLACE_IN2_ADDR2 0x78 ++#define DEINTERLACE_IN2_ADDRH 0x7c ++#define DEINTERLACE_IN3_ADDR0 0x80 ++#define DEINTERLACE_IN3_ADDR1 0x84 ++#define DEINTERLACE_IN3_ADDR2 0x88 ++#define DEINTERLACE_IN3_ADDRH 0x8c ++#define DEINTERLACE_OUT_ADDR0 0x90 ++#define DEINTERLACE_OUT_ADDR1 0x94 ++#define DEINTERLACE_OUT_ADDR2 0x98 ++#define DEINTERLACE_OUT_ADDRH 0x9c ++#define DEINTERLACE_IN_FLAG_ADDR 0xa0 ++#define DEINTERLACE_OUT_FLAG_ADDR 0xa4 ++#define DEINTERLACE_FLAG_ADDRH 0xa8 ++ ++#define DEINTERLACE_ADDRH0(x) ((x) & 0xff) ++#define DEINTERLACE_ADDRH1(x) (((x) & 0xff) << 8) ++#define DEINTERLACE_ADDRH2(x) (((x) & 0xff) << 16) ++ ++#define DEINTERLACE_MODE 0xb0 ++#define DEINTERLACE_MODE_DEINT_LUMA BIT(0) ++#define DEINTERLACE_MODE_MOTION_EN BIT(4) ++#define DEINTERLACE_MODE_INTP_EN BIT(5) ++#define DEINTERLACE_MODE_AUTO_UPD_MODE(x) (((x) & 3) << 12) ++#define DEINTERLACE_MODE_DEINT_CHROMA BIT(16) ++#define DEINTERLACE_MODE_FIELD_MODE BIT(31) ++ ++#define DEINTERLACE_MD_PARAM0 0xb4 ++#define DEINTERLACE_MD_PARAM0_MIN_LUMA_TH(x) ((x) & 0xff) ++#define DEINTERLACE_MD_PARAM0_MAX_LUMA_TH(x) (((x) & 0xff) << 8) ++#define DEINTERLACE_MD_PARAM0_AVG_LUMA_SHIFT(x) (((x) & 0xf) << 16) ++#define DEINTERLACE_MD_PARAM0_TH_SHIFT(x) (((x) & 0xf) << 24) ++ ++#define DEINTERLACE_MD_PARAM1 0xb8 ++#define DEINTERLACE_MD_PARAM1_MOV_FAC_NONEDGE(x) (((x) & 0x3) << 28) ++ ++#define DEINTERLACE_MD_PARAM2 0xbc ++#define DEINTERLACE_MD_PARAM2_CHROMA_SPATIAL_TH(x) (((x) & 0xff) << 8) ++#define DEINTERLACE_MD_PARAM2_CHROMA_DIFF_TH(x) (((x) & 0xff) << 16) ++#define DEINTERLACE_MD_PARAM2_PIX_STATIC_TH(x) (((x) & 0x3) << 28) ++ ++#define DEINTERLACE_INTP_PARAM0 0xc0 ++#define DEINTERLACE_INTP_PARAM0_ANGLE_LIMIT(x) ((x) & 0x1f) ++#define DEINTERLACE_INTP_PARAM0_ANGLE_CONST_TH(x) (((x) & 7) << 8) ++#define DEINTERLACE_INTP_PARAM0_LUMA_CUR_FAC_MODE(x) (((x) & 7) << 16) ++#define DEINTERLACE_INTP_PARAM0_LUMA_CUR_FAC_MODE_MSK (7 << 16) ++#define DEINTERLACE_INTP_PARAM0_CHROMA_CUR_FAC_MODE(x) (((x) & 7) << 20) ++#define DEINTERLACE_INTP_PARAM0_CHROMA_CUR_FAC_MODE_MSK (7 << 20) ++ ++#define DEINTERLACE_MD_CH_PARAM 0xc4 ++#define DEINTERLACE_MD_CH_PARAM_BLEND_MODE(x) ((x) & 0xf) ++#define DEINTERLACE_MD_CH_PARAM_FONT_PRO_EN BIT(8) ++#define DEINTERLACE_MD_CH_PARAM_FONT_PRO_TH(x) (((x) & 0xff) << 16) ++#define DEINTERLACE_MD_CH_PARAM_FONT_PRO_FAC(x) (((x) & 0x1f) << 24) ++ ++#define DEINTERLACE_INTP_PARAM1 0xc8 ++#define DEINTERLACE_INTP_PARAM1_A(x) ((x) & 7) ++#define DEINTERLACE_INTP_PARAM1_EN BIT(3) ++#define DEINTERLACE_INTP_PARAM1_C(x) (((x) & 0xf) << 4) ++#define DEINTERLACE_INTP_PARAM1_CMAX(x) (((x) & 0xff) << 8) ++#define DEINTERLACE_INTP_PARAM1_MAXRAT(x) (((x) & 3) << 16) ++ ++#define DEINTERLACE_OUT_PATH 0x200 ++ ++#define DEINTERLACE_MIN_WIDTH 2U ++#define DEINTERLACE_MIN_HEIGHT 2U ++#define DEINTERLACE_MAX_WIDTH 2048U ++#define DEINTERLACE_MAX_HEIGHT 1100U ++ ++struct deinterlace_ctx { ++ struct v4l2_fh fh; ++ struct deinterlace_dev *dev; ++ ++ struct v4l2_pix_format src_fmt; ++ struct v4l2_pix_format dst_fmt; ++ ++ void *flag1_buf; ++ dma_addr_t flag1_buf_dma; ++ ++ void *flag2_buf; ++ dma_addr_t flag2_buf_dma; ++ ++ struct vb2_v4l2_buffer *prev[2]; ++ ++ unsigned int first_field; ++ unsigned int field; ++ ++ int aborting; ++}; ++ ++struct deinterlace_dev { ++ struct v4l2_device v4l2_dev; ++ struct video_device vfd; ++ struct device *dev; ++ struct v4l2_m2m_dev *m2m_dev; ++ ++ /* Device file mutex */ ++ struct mutex dev_mutex; ++ ++ void __iomem *base; ++ ++ struct clk *bus_clk; ++ struct clk *mod_clk; ++ struct clk *ram_clk; ++ ++ struct reset_control *rstc; ++}; ++ ++#endif diff --git a/0041-arm64-dts-h6-deinterlace.patch b/0041-arm64-dts-h6-deinterlace.patch new file mode 100644 index 000000000000..265437c41923 --- /dev/null +++ b/0041-arm64-dts-h6-deinterlace.patch @@ -0,0 +1,32 @@ +From c009b3b707bbde30fa6ff49ca3075160524ea7b9 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec <jernej.skrabec@siol.net> +Date: Tue, 26 May 2020 20:08:27 +0200 +Subject: [PATCH 41/44] arm64: dts: h6 deinterlace + +Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> +--- + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -153,6 +153,17 @@ + }; + }; + ++ deinterlace: deinterlace@1420000 { ++ compatible = "allwinner,sun50i-h6-deinterlace"; ++ reg = <0x01420000 0x2000>; ++ clocks = <&ccu CLK_BUS_DEINTERLACE>, ++ <&ccu CLK_DEINTERLACE>, ++ <&ccu CLK_MBUS_DEINTERLACE>; ++ clock-names = "bus", "mod", "ram"; ++ resets = <&ccu RST_BUS_DEINTERLACE>; ++ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ + video-codec@1c0e000 { + compatible = "allwinner,sun50i-h6-video-engine"; + reg = <0x01c0e000 0x2000>; + + @@ -9,7 +9,7 @@ pkgbase=linux-tqc-a01 _srcname=linux-5.13 _kernelname=${pkgbase#linux} _desc="AArch64 kernel for TQC A01" -pkgver=5.13.9 +pkgver=5.13.10 pkgrel=1 arch=('aarch64') url="http://www.kernel.org/" @@ -30,6 +30,9 @@ source=("http://cdn.kernel.org/pub/linux/kernel/v5.x/${_srcname}.tar.xz" '0006-drm-sun4i-Add-GEM-allocator.patch' '0010-general-h6-add-dma-i2c-ir-spi-uart.patch' '0011-dts-h6-tqc-a01-cpu-opp-2ghz.patch' + '0012-arm64-h6-gpu-devfreq-enable.patch' + '0040-wip-H6-deinterlace.patch' + '0041-arm64-dts-h6-deinterlace.patch' 'config' 'linux.preset' '60-linux.hook' @@ -51,12 +54,15 @@ md5sums=('76c60fb304510a7bbd9c838790bc5fe4' '335382823f6dc2aae2f6038b7aee339e' 'cb38b30491472097c3b9b475de39127f' 'bc65c0b9e4d6fb2fe3a81b8358886885' - '6637a33cfc563c8f1ccff00cfd5b39c5' - 'a5564b07e7a88dc6211d647c7949904d' + '74baf0cb243b3abd5e38f0131c95408f' + '05c4d9cbe622d5ff15e6b84b1c5c1a70' + 'd1543c205b4faf9be4552d4308228217' + 'e4ef0ae46cdfb23abb11d729452f68b2' + '75b51f71570f7ee1a7a18cfa05b67edd' '66e0ae63183426b28c0ec0c7e10b5e16' 'ce6c81ad1ad1f8b333fd6077d47abdaf' '3dc88030a8f2f5a5f97266d99b149f77' - '39a5d2b3ff92c000dc93f9fa2efb2c45') + '4d745d474d07277daee24107239c8902') prepare() { cd ${_srcname} @@ -83,6 +89,9 @@ prepare() { patch -p1 < ../0006-drm-sun4i-Add-GEM-allocator.patch patch -p1 < ../0010-general-h6-add-dma-i2c-ir-spi-uart.patch patch -p1 < ../0011-dts-h6-tqc-a01-cpu-opp-2ghz.patch + patch -p1 < ../0012-arm64-h6-gpu-devfreq-enable.patch + patch -p1 < ../0040-wip-H6-deinterlace.patch + patch -p1 < ../0041-arm64-dts-h6-deinterlace.patch cat "${srcdir}/config" > ./.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.13.9-1 Kernel Configuration +# Linux/arm64 5.13.10-1 Kernel Configuration # CONFIG_CC_VERSION_TEXT="gcc (GCC) 10.2.0" CONFIG_CC_IS_GCC=y @@ -299,8 +299,8 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y CONFIG_ARCH_SUNXI=y # CONFIG_ARCH_ALPINE is not set # CONFIG_ARCH_APPLE is not set -CONFIG_ARCH_BCM2835=y -CONFIG_ARCH_BCM4908=y +# CONFIG_ARCH_BCM2835 is not set +# CONFIG_ARCH_BCM4908 is not set # CONFIG_ARCH_BCM_IPROC is not set # CONFIG_ARCH_BERLIN is not set # CONFIG_ARCH_BITMAIN is not set @@ -310,28 +310,28 @@ CONFIG_ARCH_BCM4908=y # CONFIG_ARCH_K3 is not set CONFIG_ARCH_LAYERSCAPE=y # CONFIG_ARCH_LG1K is not set -CONFIG_ARCH_HISI=y +# CONFIG_ARCH_HISI is not set # CONFIG_ARCH_KEEMBAY is not set -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MESON=y -CONFIG_ARCH_MVEBU=y -CONFIG_ARCH_MXC=y -CONFIG_ARCH_QCOM=y +# CONFIG_ARCH_MEDIATEK is not set +# CONFIG_ARCH_MESON is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_QCOM is not set # CONFIG_ARCH_REALTEK is not set # CONFIG_ARCH_RENESAS is not set -CONFIG_ARCH_ROCKCHIP=y +# CONFIG_ARCH_ROCKCHIP is not set # CONFIG_ARCH_S32 is not set -CONFIG_ARCH_SEATTLE=y +# CONFIG_ARCH_SEATTLE is not set # CONFIG_ARCH_INTEL_SOCFPGA is not set # CONFIG_ARCH_SYNQUACER is not set -CONFIG_ARCH_TEGRA=y +# CONFIG_ARCH_TEGRA is not set # CONFIG_ARCH_SPRD is not set # CONFIG_ARCH_THUNDER is not set # CONFIG_ARCH_THUNDER2 is not set # CONFIG_ARCH_UNIPHIER is not set CONFIG_ARCH_VEXPRESS=y # CONFIG_ARCH_VISCONTI is not set -CONFIG_ARCH_XGENE=y +# CONFIG_ARCH_XGENE is not set # CONFIG_ARCH_ZYNQMP is not set # end of Platform selection @@ -584,19 +584,8 @@ CONFIG_CPUFREQ_DT=y CONFIG_CPUFREQ_DT_PLATDEV=y CONFIG_ACPI_CPPC_CPUFREQ=y CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y -CONFIG_ARM_ARMADA_37XX_CPUFREQ=y -CONFIG_ARM_ARMADA_8K_CPUFREQ=y CONFIG_ARM_SCPI_CPUFREQ=y -CONFIG_ARM_IMX_CPUFREQ_DT=y -# CONFIG_ARM_MEDIATEK_CPUFREQ is not set -CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y -CONFIG_ARM_QCOM_CPUFREQ_HW=y -CONFIG_ARM_RASPBERRYPI_CPUFREQ=y CONFIG_ARM_SCMI_CPUFREQ=y -CONFIG_ARM_TEGRA20_CPUFREQ=y -CONFIG_ARM_TEGRA124_CPUFREQ=y -CONFIG_ARM_TEGRA186_CPUFREQ=y -CONFIG_ARM_TEGRA194_CPUFREQ=y CONFIG_QORIQ_CPUFREQ=m # end of CPU Frequency scaling # end of CPU Power Management @@ -613,11 +602,7 @@ CONFIG_ARM_SCPI_POWER_DOMAIN=y CONFIG_DMIID=y CONFIG_DMI_SYSFS=y # CONFIG_ISCSI_IBFT is not set -CONFIG_RASPBERRYPI_FIRMWARE=y # CONFIG_FW_CFG_SYSFS is not set -CONFIG_QCOM_SCM=y -# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set -# CONFIG_TURRIS_MOX_RWTM is not set # CONFIG_GOOGLE_FIRMWARE is not set # @@ -640,10 +625,6 @@ CONFIG_EFI_BOOTLOADER_CONTROL=y CONFIG_EFI_EARLYCON=y CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y -# CONFIG_IMX_DSP is not set -CONFIG_IMX_SCU=y -CONFIG_IMX_SCU_PD=y -CONFIG_MESON_SM=y CONFIG_ARM_PSCI_FW=y # CONFIG_ARM_PSCI_CHECKER is not set CONFIG_HAVE_ARM_SMCCC=y @@ -653,8 +634,6 @@ CONFIG_ARM_SMCCC_SOC_ID=y # # Tegra firmware driver # -CONFIG_TEGRA_IVC=y -CONFIG_TEGRA_BPMP=y # end of Tegra firmware driver # end of Firmware Drivers @@ -1925,7 +1904,6 @@ CONFIG_BT_MRVL_SDIO=m CONFIG_BT_ATH3K=m # CONFIG_BT_MTKSDIO is not set # CONFIG_BT_MTKUART is not set -CONFIG_BT_QCOMSMD=m CONFIG_BT_HCIRSI=m # CONFIG_BT_VIRTIO is not set # end of Bluetooth device drivers @@ -2032,7 +2010,6 @@ CONFIG_ETHTOOL_NETLINK=y # Device Drivers # CONFIG_ARM_AMBA=y -CONFIG_TEGRA_AHB=y CONFIG_HAVE_PCI=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y @@ -2060,7 +2037,6 @@ CONFIG_PCI_STUB=y # CONFIG_PCI_PF_STUB is not set CONFIG_PCI_ATS=y CONFIG_PCI_ECAM=y -CONFIG_PCI_BRIDGE_EMUL=y CONFIG_PCI_IOV=y CONFIG_PCI_PRI=y CONFIG_PCI_PASID=y @@ -2079,9 +2055,7 @@ CONFIG_HOTPLUG_PCI_ACPI=y # # PCI controller drivers # -CONFIG_PCI_AARDVARK=y # CONFIG_PCI_FTPCI100 is not set -CONFIG_PCI_TEGRA=y CONFIG_PCI_HOST_COMMON=y CONFIG_PCI_HOST_GENERIC=y # CONFIG_PCIE_XILINX is not set @@ -2090,11 +2064,6 @@ CONFIG_PCI_XGENE_MSI=y # CONFIG_PCIE_ALTERA is not set # CONFIG_PCI_HOST_THUNDER_PEM is not set # CONFIG_PCI_HOST_THUNDER_ECAM is not set -CONFIG_PCIE_ROCKCHIP=y -CONFIG_PCIE_ROCKCHIP_HOST=y -# CONFIG_PCIE_MEDIATEK is not set -# CONFIG_PCIE_MEDIATEK_GEN3 is not set -CONFIG_PCIE_BRCMSTB=m # CONFIG_PCIE_MICROCHIP_HOST is not set # @@ -2104,15 +2073,10 @@ CONFIG_PCIE_DW=y CONFIG_PCIE_DW_HOST=y CONFIG_PCIE_DW_PLAT=y CONFIG_PCIE_DW_PLAT_HOST=y -# CONFIG_PCI_IMX6 is not set CONFIG_PCI_LAYERSCAPE=y CONFIG_PCI_HISI=y -CONFIG_PCIE_QCOM=y -CONFIG_PCIE_ARMADA_8K=y # CONFIG_PCIE_KIRIN is not set -CONFIG_PCIE_HISI_STB=y CONFIG_PCI_MESON=y -# CONFIG_PCIE_TEGRA194_HOST is not set # CONFIG_PCIE_AL is not set # end of DesignWare PCI Core Support @@ -2196,14 +2160,9 @@ CONFIG_ARM_CCI=y CONFIG_ARM_CCI400_COMMON=y # CONFIG_BRCMSTB_GISB_ARB is not set # CONFIG_MOXTET is not set -# CONFIG_HISILICON_LPC is not set -# CONFIG_IMX_WEIM is not set -CONFIG_QCOM_EBI2=y CONFIG_SIMPLE_PM_BUS=y CONFIG_SUN50I_DE2_BUS=y CONFIG_SUNXI_RSB=y -CONFIG_TEGRA_ACONNECT=m -# CONFIG_TEGRA_GMI is not set CONFIG_VEXPRESS_CONFIG=y CONFIG_FSL_MC_BUS=y # CONFIG_FSL_MC_UAPI_SUPPORT is not set @@ -2226,11 +2185,8 @@ CONFIG_MTD=y # CONFIG_MTD_AR7_PARTS is not set # CONFIG_MTD_CMDLINE_PARTS is not set CONFIG_MTD_OF_PARTS=m -CONFIG_MTD_OF_PARTS_BCM4908=y -# CONFIG_MTD_OF_PARTS_LINKSYS_NS is not set # CONFIG_MTD_AFS_PARTS is not set # CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_QCOMSMEM_PARTS is not set # end of Partition parsers # @@ -2314,23 +2270,15 @@ CONFIG_MTD_RAW_NAND=y # CONFIG_MTD_NAND_DENALI_PCI is not set # CONFIG_MTD_NAND_DENALI_DT is not set # CONFIG_MTD_NAND_CAFE is not set -CONFIG_MTD_NAND_MARVELL=y # CONFIG_MTD_NAND_BRCMNAND is not set # CONFIG_MTD_NAND_FSL_IFC is not set -# CONFIG_MTD_NAND_MXC is not set # CONFIG_MTD_NAND_SUNXI is not set -# CONFIG_MTD_NAND_HISI504 is not set -CONFIG_MTD_NAND_QCOM=y -# CONFIG_MTD_NAND_MTK is not set # CONFIG_MTD_NAND_MXIC is not set -# CONFIG_MTD_NAND_TEGRA is not set -# CONFIG_MTD_NAND_MESON is not set # CONFIG_MTD_NAND_GPIO is not set # CONFIG_MTD_NAND_PLATFORM is not set # CONFIG_MTD_NAND_CADENCE is not set # CONFIG_MTD_NAND_ARASAN is not set # CONFIG_MTD_NAND_INTEL_LGM is not set -# CONFIG_MTD_NAND_ROCKCHIP is not set # # Misc @@ -2361,7 +2309,6 @@ CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y # CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y # CONFIG_MTD_SPI_NOR_SWP_KEEP is not set -CONFIG_SPI_HISI_SFC=m CONFIG_MTD_UBI=m CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MTD_UBI_BEB_LIMIT=20 @@ -2446,8 +2393,6 @@ CONFIG_TIFM_7XX1=m # CONFIG_ICS932S401 is not set CONFIG_ENCLOSURE_SERVICES=m # CONFIG_HP_ILO is not set -# CONFIG_QCOM_COINCELL is not set -# CONFIG_QCOM_FASTRPC is not set CONFIG_APDS9802ALS=m CONFIG_ISL29003=m CONFIG_ISL29020=m @@ -2577,9 +2522,6 @@ CONFIG_SCSI_UFSHCD_PCI=m CONFIG_SCSI_UFSHCD_PLATFORM=y # CONFIG_SCSI_UFS_CDNS_PLATFORM is not set # CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set -CONFIG_SCSI_UFS_QCOM=m -# CONFIG_SCSI_UFS_MEDIATEK is not set -CONFIG_SCSI_UFS_HISI=y # CONFIG_SCSI_UFS_BSG is not set CONFIG_SCSI_HPTIOP=m # CONFIG_SCSI_MYRB is not set @@ -2641,15 +2583,10 @@ CONFIG_SATA_PMP=y CONFIG_SATA_AHCI=y CONFIG_SATA_MOBILE_LPM_POLICY=0 CONFIG_SATA_AHCI_PLATFORM=y -# CONFIG_AHCI_IMX is not set # CONFIG_AHCI_CEVA is not set -# CONFIG_AHCI_MTK is not set -CONFIG_AHCI_MVEBU=y CONFIG_AHCI_SUNXI=y -# CONFIG_AHCI_TEGRA is not set CONFIG_AHCI_XGENE=y # CONFIG_AHCI_QORIQ is not set -CONFIG_SATA_AHCI_SEATTLE=y CONFIG_SATA_INIC162X=m CONFIG_SATA_ACARD_AHCI=m CONFIG_SATA_SIL24=y @@ -2694,7 +2631,6 @@ CONFIG_PATA_HPT37X=m CONFIG_PATA_HPT3X2N=m CONFIG_PATA_HPT3X3=m # CONFIG_PATA_HPT3X3_DMA is not set -# CONFIG_PATA_IMX is not set CONFIG_PATA_IT8213=m CONFIG_PATA_IT821X=m CONFIG_PATA_JMICRON=m @@ -2899,12 +2835,9 @@ CONFIG_AMD8111_ETH=m CONFIG_PCNET32=m CONFIG_AMD_XGBE=m # CONFIG_AMD_XGBE_DCB is not set -CONFIG_NET_XGENE=y -# CONFIG_NET_XGENE_V2 is not set CONFIG_NET_VENDOR_AQUANTIA=y CONFIG_AQTION=m CONFIG_NET_VENDOR_ARC=y -# CONFIG_EMAC_ROCKCHIP is not set CONFIG_NET_VENDOR_ATHEROS=y CONFIG_ATL2=m CONFIG_ATL1=m @@ -2916,7 +2849,6 @@ CONFIG_B44=m CONFIG_B44_PCI_AUTOSELECT=y CONFIG_B44_PCICORE_AUTOSELECT=y CONFIG_B44_PCI=y -CONFIG_BCM4908_ENET=y CONFIG_BCMGENET=m CONFIG_BNX2=m CONFIG_CNIC=m @@ -2945,7 +2877,6 @@ CONFIG_SUNDANCE=m # CONFIG_NET_VENDOR_EMULEX is not set # CONFIG_NET_VENDOR_EZCHIP is not set CONFIG_NET_VENDOR_FREESCALE=y -CONFIG_FEC=y CONFIG_FSL_FMAN=m CONFIG_DPAA_ERRATUM_A050385=y # CONFIG_FSL_PQ_MDIO is not set @@ -2998,9 +2929,6 @@ CONFIG_NET_VENDOR_MICROSOFT=y CONFIG_JME=m CONFIG_NET_VENDOR_MARVELL=y CONFIG_MVMDIO=m -CONFIG_MVNETA=m -CONFIG_MVPP2=m -# CONFIG_MVPP2_PTP is not set CONFIG_SKGE=m # CONFIG_SKGE_DEBUG is not set CONFIG_SKGE_GENESIS=y @@ -3009,9 +2937,6 @@ CONFIG_SKY2=m # CONFIG_OCTEONTX2_AF is not set # CONFIG_OCTEONTX2_PF is not set # CONFIG_PRESTERA is not set -CONFIG_NET_VENDOR_MEDIATEK=y -# CONFIG_NET_MEDIATEK_SOC is not set -# CONFIG_NET_MEDIATEK_STAR_EMAC is not set CONFIG_NET_VENDOR_MELLANOX=y CONFIG_MLX4_EN=m CONFIG_MLX4_EN_DCB=y @@ -3106,14 +3031,8 @@ CONFIG_STMMAC_ETH=m CONFIG_STMMAC_PLATFORM=m CONFIG_DWMAC_DWC_QOS_ETH=m CONFIG_DWMAC_GENERIC=m -CONFIG_DWMAC_IPQ806X=m -# CONFIG_DWMAC_MEDIATEK is not set -CONFIG_DWMAC_MESON=m -CONFIG_DWMAC_QCOM_ETHQOS=m -CONFIG_DWMAC_ROCKCHIP=m CONFIG_DWMAC_SUNXI=m CONFIG_DWMAC_SUN8I=m -CONFIG_DWMAC_IMX8=m # CONFIG_DWMAC_INTEL_PLAT is not set # CONFIG_STMMAC_PCI is not set # CONFIG_NET_VENDOR_SUN is not set @@ -3135,7 +3054,6 @@ CONFIG_NET_VENDOR_XILINX=y # CONFIG_XILINX_LL_TEMAC is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set -CONFIG_QCOM_IPA=m CONFIG_NET_SB1000=y CONFIG_PHYLINK=m CONFIG_PHYLIB=y @@ -3149,7 +3067,6 @@ CONFIG_SFP=m # CONFIG_AC200_PHY=y CONFIG_AMD_PHY=m -CONFIG_MESON_GXL_PHY=m # CONFIG_ADIN_PHY is not set # CONFIG_AQUANTIA_PHY is not set # CONFIG_AX88796B_PHY is not set @@ -3197,7 +3114,6 @@ CONFIG_MDIO_BUS=y CONFIG_OF_MDIO=y CONFIG_MDIO_DEVRES=y # CONFIG_MDIO_SUN4I is not set -CONFIG_MDIO_XGENE=y CONFIG_MDIO_BITBANG=m CONFIG_MDIO_BCM_UNIMAC=y # CONFIG_MDIO_GPIO is not set @@ -3214,7 +3130,6 @@ CONFIG_MDIO_I2C=m # MDIO Multiplexers # CONFIG_MDIO_BUS_MUX=m -CONFIG_MDIO_BUS_MUX_MESON_G12A=m CONFIG_MDIO_BUS_MUX_GPIO=m # CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set CONFIG_MDIO_BUS_MUX_MMIOREG=m @@ -3335,7 +3250,6 @@ CONFIG_ATH10K_PCI=m # CONFIG_ATH10K_AHB is not set # CONFIG_ATH10K_SDIO is not set # CONFIG_ATH10K_USB is not set -CONFIG_ATH10K_SNOC=m # CONFIG_ATH10K_DEBUG is not set CONFIG_ATH10K_DEBUGFS=y # CONFIG_ATH10K_SPECTRAL is not set @@ -3476,7 +3390,6 @@ CONFIG_MT76x2U=m CONFIG_MT7603E=m CONFIG_MT7615_COMMON=m CONFIG_MT7615E=m -CONFIG_MT7622_WMAC=y # CONFIG_MT7663U is not set # CONFIG_MT7663S is not set # CONFIG_MT7915E is not set @@ -3636,11 +3549,7 @@ CONFIG_KEYBOARD_GPIO_POLLED=m # CONFIG_KEYBOARD_MAX7359 is not set # CONFIG_KEYBOARD_MCS is not set # CONFIG_KEYBOARD_MPR121 is not set -CONFIG_KEYBOARD_SNVS_PWRKEY=m -# CONFIG_KEYBOARD_IMX is not set -CONFIG_KEYBOARD_IMX_SC_KEY=m # CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_TEGRA is not set # CONFIG_KEYBOARD_OPENCORES is not set # CONFIG_KEYBOARD_SAMSUNG is not set # CONFIG_KEYBOARD_STOWAWAY is not set @@ -3762,7 +3671,6 @@ CONFIG_TOUCHSCREEN_INEXIO=m CONFIG_TOUCHSCREEN_MK712=m CONFIG_TOUCHSCREEN_PENMOUNT=m CONFIG_TOUCHSCREEN_EDT_FT5X06=m -CONFIG_TOUCHSCREEN_RASPBERRYPI_FW=m CONFIG_TOUCHSCREEN_TOUCHRIGHT=m CONFIG_TOUCHSCREEN_TOUCHWIN=m CONFIG_TOUCHSCREEN_PIXCIR=m @@ -3814,8 +3722,6 @@ CONFIG_INPUT_MISC=y # CONFIG_INPUT_ATMEL_CAPTOUCH is not set # CONFIG_INPUT_BMA150 is not set CONFIG_INPUT_E3X0_BUTTON=m -CONFIG_INPUT_PM8941_PWRKEY=y -CONFIG_INPUT_PM8XXX_VIBRATOR=m CONFIG_INPUT_MMA8450=m # CONFIG_INPUT_GPIO_BEEPER is not set # CONFIG_INPUT_GPIO_DECODER is not set @@ -3845,7 +3751,6 @@ CONFIG_INPUT_CMA3000_I2C=m # CONFIG_INPUT_DRV260X_HAPTICS is not set # CONFIG_INPUT_DRV2665_HAPTICS is not set # CONFIG_INPUT_DRV2667_HAPTICS is not set -CONFIG_INPUT_HISI_POWERKEY=y CONFIG_RMI4_CORE=m # CONFIG_RMI4_I2C is not set # CONFIG_RMI4_SPI is not set @@ -3917,12 +3822,9 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y # CONFIG_SERIAL_8250_DETECT_IRQ is not set CONFIG_SERIAL_8250_RSA=y CONFIG_SERIAL_8250_DWLIB=y -CONFIG_SERIAL_8250_BCM2835AUX=y CONFIG_SERIAL_8250_FSL=y CONFIG_SERIAL_8250_DW=y # CONFIG_SERIAL_8250_RT288X is not set -# CONFIG_SERIAL_8250_MT6577 is not set -CONFIG_SERIAL_8250_TEGRA=y CONFIG_SERIAL_OF_PLATFORM=y # @@ -3933,23 +3835,13 @@ CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST=y # CONFIG_SERIAL_KGDB_NMI is not set -CONFIG_SERIAL_MESON=y -CONFIG_SERIAL_MESON_CONSOLE=y -CONFIG_SERIAL_TEGRA=y -# CONFIG_SERIAL_TEGRA_TCU is not set # CONFIG_SERIAL_MAX3100 is not set # CONFIG_SERIAL_MAX310X is not set -CONFIG_SERIAL_IMX=y -CONFIG_SERIAL_IMX_CONSOLE=y -# CONFIG_SERIAL_IMX_EARLYCON is not set # CONFIG_SERIAL_UARTLITE is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_CONSOLE_POLL=y CONFIG_SERIAL_JSM=m -CONFIG_SERIAL_MSM=y -CONFIG_SERIAL_MSM_CONSOLE=y -# CONFIG_SERIAL_QCOM_GENI is not set # CONFIG_SERIAL_SIFIVE is not set # CONFIG_SERIAL_SCCNXP is not set # CONFIG_SERIAL_SC16IS7XX is not set @@ -3966,8 +3858,6 @@ CONFIG_SERIAL_FSL_LINFLEXUART=y CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y # CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set # CONFIG_SERIAL_SPRD is not set -CONFIG_SERIAL_MVEBU_UART=y -CONFIG_SERIAL_MVEBU_CONSOLE=y # end of Serial drivers CONFIG_SERIAL_MCTRL_GPIO=y @@ -3998,15 +3888,8 @@ CONFIG_IPMI_POWEROFF=m CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_TIMERIOMEM=m # CONFIG_HW_RANDOM_BA431 is not set -CONFIG_HW_RANDOM_BCM2835=y -CONFIG_HW_RANDOM_IPROC_RNG200=y -CONFIG_HW_RANDOM_OMAP=y CONFIG_HW_RANDOM_VIRTIO=m -CONFIG_HW_RANDOM_HISI=y -CONFIG_HW_RANDOM_XGENE=m -CONFIG_HW_RANDOM_MESON=y CONFIG_HW_RANDOM_CAVIUM=y -CONFIG_HW_RANDOM_MTK=y # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set # CONFIG_APPLICOM is not set @@ -4077,7 +3960,6 @@ CONFIG_I2C_ALGOPCA=m # CONFIG_I2C_AMD756 is not set # CONFIG_I2C_AMD8111 is not set # CONFIG_I2C_AMD_MP2 is not set -# CONFIG_I2C_HIX5HD2 is not set # CONFIG_I2C_I801 is not set # CONFIG_I2C_ISCH is not set # CONFIG_I2C_PIIX4 is not set @@ -4097,8 +3979,6 @@ CONFIG_I2C_SCMI=y # # I2C system bus drivers (mostly embedded / system-on-chip) # -CONFIG_I2C_BCM2835=m -CONFIG_I2C_BRCMSTB=m # CONFIG_I2C_CADENCE is not set # CONFIG_I2C_CBUS_GPIO is not set CONFIG_I2C_DESIGNWARE_CORE=y @@ -4110,22 +3990,12 @@ CONFIG_I2C_GPIO=m # CONFIG_I2C_GPIO_FAULT_INJECTOR is not set # CONFIG_I2C_HISI is not set CONFIG_I2C_IMX=y -CONFIG_I2C_IMX_LPI2C=y -CONFIG_I2C_MESON=y -CONFIG_I2C_MT65XX=y CONFIG_I2C_MV64XXX=y # CONFIG_I2C_NOMADIK is not set # CONFIG_I2C_OCORES is not set CONFIG_I2C_PCA_PLATFORM=m -CONFIG_I2C_PXA=y -# CONFIG_I2C_PXA_SLAVE is not set -CONFIG_I2C_QCOM_CCI=m -CONFIG_I2C_QCOM_GENI=m -CONFIG_I2C_QUP=y CONFIG_I2C_RK3X=y CONFIG_I2C_SIMTEC=m -CONFIG_I2C_TEGRA=m -CONFIG_I2C_TEGRA_BPMP=m CONFIG_I2C_VERSATILE=m # CONFIG_I2C_THUNDERX is not set # CONFIG_I2C_XILINX is not set @@ -4144,7 +4014,6 @@ CONFIG_I2C_VIPERBOARD=m # Other I2C/SMBus bus drivers # CONFIG_I2C_CROS_EC_TUNNEL=y -CONFIG_I2C_XGENE_SLIMPRO=m # end of I2C Hardware Bus support CONFIG_I2C_STUB=m @@ -4166,44 +4035,27 @@ CONFIG_SPI_MEM=y # SPI Master Controller Drivers # # CONFIG_SPI_ALTERA is not set -CONFIG_SPI_ARMADA_3700=y # CONFIG_SPI_AXI_SPI_ENGINE is not set -CONFIG_SPI_BCM2835=m -CONFIG_SPI_BCM2835AUX=m CONFIG_SPI_BITBANG=y # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_SPI_DESIGNWARE is not set -# CONFIG_SPI_FSL_LPSPI is not set # CONFIG_SPI_FSL_QUADSPI is not set # CONFIG_SPI_HISI_KUNPENG is not set # CONFIG_SPI_HISI_SFC_V3XX is not set CONFIG_SPI_NXP_FLEXSPI=y CONFIG_SPI_GPIO=y -CONFIG_SPI_IMX=m # CONFIG_SPI_FSL_SPI is not set # CONFIG_SPI_FSL_DSPI is not set -CONFIG_SPI_MESON_SPICC=m -CONFIG_SPI_MESON_SPIFC=m -CONFIG_SPI_MT65XX=y -# CONFIG_SPI_MTK_NOR is not set # CONFIG_SPI_OC_TINY is not set -CONFIG_SPI_ORION=y CONFIG_SPI_PL022=y # CONFIG_SPI_PXA2XX is not set CONFIG_SPI_ROCKCHIP=y -CONFIG_SPI_QCOM_QSPI=m -CONFIG_SPI_QUP=y -CONFIG_SPI_QCOM_GENI=m # CONFIG_SPI_SC18IS602 is not set # CONFIG_SPI_SIFIVE is not set # CONFIG_SPI_SUN4I is not set CONFIG_SPI_SUN6I=y # CONFIG_SPI_MXIC is not set -# CONFIG_SPI_TEGRA210_QUAD is not set -# CONFIG_SPI_TEGRA114 is not set -# CONFIG_SPI_TEGRA20_SFLASH is not set -# CONFIG_SPI_TEGRA20_SLINK is not set # CONFIG_SPI_THUNDERX is not set # CONFIG_SPI_XCOMM is not set # CONFIG_SPI_XILINX is not set @@ -4224,7 +4076,6 @@ CONFIG_SPI_SPIDEV=m # CONFIG_SPI_SLAVE is not set CONFIG_SPI_DYNAMIC=y CONFIG_SPMI=y -CONFIG_SPMI_MSM_PMIC_ARB=y # CONFIG_HSI is not set CONFIG_PPS=y # CONFIG_PPS_DEBUG is not set @@ -4263,7 +4114,6 @@ CONFIG_GENERIC_PINCONF=y CONFIG_PINCTRL_AXP209=y CONFIG_PINCTRL_AMD=y # CONFIG_PINCTRL_MCP23S08 is not set -CONFIG_PINCTRL_ROCKCHIP=y CONFIG_PINCTRL_SINGLE=y # CONFIG_PINCTRL_SX150X is not set # CONFIG_PINCTRL_STMFX is not set @@ -4271,52 +4121,6 @@ CONFIG_PINCTRL_MAX77620=y CONFIG_PINCTRL_RK805=y # CONFIG_PINCTRL_OCELOT is not set # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set -CONFIG_PINCTRL_BCM2835=y -CONFIG_PINCTRL_IMX=y -CONFIG_PINCTRL_IMX_SCU=y -CONFIG_PINCTRL_IMX8MM=y -CONFIG_PINCTRL_IMX8MN=y -CONFIG_PINCTRL_IMX8MP=y -CONFIG_PINCTRL_IMX8MQ=y -# CONFIG_PINCTRL_IMX8QM is not set -CONFIG_PINCTRL_IMX8QXP=y -CONFIG_PINCTRL_IMX8DXL=y -CONFIG_PINCTRL_MVEBU=y -CONFIG_PINCTRL_ARMADA_AP806=y -CONFIG_PINCTRL_ARMADA_CP110=y -CONFIG_PINCTRL_ARMADA_37XX=y -CONFIG_PINCTRL_MSM=y -CONFIG_PINCTRL_APQ8064=y -# CONFIG_PINCTRL_APQ8084 is not set -# CONFIG_PINCTRL_IPQ4019 is not set -# CONFIG_PINCTRL_IPQ8064 is not set -# CONFIG_PINCTRL_IPQ8074 is not set -CONFIG_PINCTRL_IPQ6018=y -# CONFIG_PINCTRL_MSM8226 is not set -# CONFIG_PINCTRL_MSM8660 is not set -# CONFIG_PINCTRL_MSM8960 is not set -# CONFIG_PINCTRL_MDM9615 is not set -# CONFIG_PINCTRL_MSM8X74 is not set -CONFIG_PINCTRL_MSM8916=y -# CONFIG_PINCTRL_MSM8953 is not set -# CONFIG_PINCTRL_MSM8976 is not set -CONFIG_PINCTRL_MSM8994=y -CONFIG_PINCTRL_MSM8996=y -# CONFIG_PINCTRL_MSM8998 is not set -# CONFIG_PINCTRL_QCS404 is not set -# CONFIG_PINCTRL_QDF2XXX is not set -CONFIG_PINCTRL_QCOM_SPMI_PMIC=y -CONFIG_PINCTRL_QCOM_SSBI_PMIC=y -CONFIG_PINCTRL_SC7180=y -# CONFIG_PINCTRL_SC7280 is not set -# CONFIG_PINCTRL_SC8180X is not set -# CONFIG_PINCTRL_SDM660 is not set -CONFIG_PINCTRL_SDM845=y -# CONFIG_PINCTRL_SDX55 is not set -CONFIG_PINCTRL_SM8150=y -CONFIG_PINCTRL_SM8250=y -# CONFIG_PINCTRL_SM8350 is not set -# CONFIG_PINCTRL_LPASS_LPI is not set # # Renesas pinctrl drivers @@ -4347,41 +4151,6 @@ CONFIG_PINCTRL_SUN50I_H6=y CONFIG_PINCTRL_SUN50I_H6_R=y CONFIG_PINCTRL_SUN50I_H616=y CONFIG_PINCTRL_SUN50I_H616_R=y -CONFIG_PINCTRL_TEGRA=y -CONFIG_PINCTRL_TEGRA124=y -CONFIG_PINCTRL_TEGRA210=y -CONFIG_PINCTRL_TEGRA194=y -CONFIG_PINCTRL_TEGRA_XUSB=y - -# -# MediaTek pinctrl drivers -# -CONFIG_EINT_MTK=y -CONFIG_PINCTRL_MTK=y -CONFIG_PINCTRL_MTK_V2=y -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_PARIS=y -CONFIG_PINCTRL_MT2712=y -CONFIG_PINCTRL_MT6765=y -CONFIG_PINCTRL_MT6779=y -CONFIG_PINCTRL_MT6797=y -CONFIG_PINCTRL_MT7622=y -CONFIG_PINCTRL_MT8167=y -CONFIG_PINCTRL_MT8173=y -CONFIG_PINCTRL_MT8183=y -CONFIG_PINCTRL_MT8192=y -# CONFIG_PINCTRL_MT8195 is not set -CONFIG_PINCTRL_MT8516=y -# end of MediaTek pinctrl drivers - -CONFIG_PINCTRL_MESON=y -CONFIG_PINCTRL_MESON_GXBB=y -CONFIG_PINCTRL_MESON_GXL=y -CONFIG_PINCTRL_MESON8_PMX=y -CONFIG_PINCTRL_MESON_AXG=y -CONFIG_PINCTRL_MESON_AXG_PMX=y -CONFIG_PINCTRL_MESON_G12A=y -CONFIG_PINCTRL_MESON_A1=y CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y @@ -4400,7 +4169,6 @@ CONFIG_GPIO_REGMAP=m # CONFIG_GPIO_74XX_MMIO is not set # CONFIG_GPIO_ALTERA is not set # CONFIG_GPIO_AMDPT is not set -CONFIG_GPIO_RASPBERRYPI_EXP=y # CONFIG_GPIO_CADENCE is not set CONFIG_GPIO_DWAPB=y # CONFIG_GPIO_EXAR is not set @@ -4412,17 +4180,12 @@ CONFIG_GPIO_GENERIC_PLATFORM=y # CONFIG_GPIO_LOGICVC is not set # CONFIG_GPIO_MB86S7X is not set CONFIG_GPIO_MPC8XXX=y -CONFIG_GPIO_MVEBU=y -CONFIG_GPIO_MXC=y CONFIG_GPIO_PL061=y # CONFIG_GPIO_SAMA5D2_PIOBU is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SYSCON=y -CONFIG_GPIO_TEGRA=y -CONFIG_GPIO_TEGRA186=y CONFIG_GPIO_WCD934X=m CONFIG_GPIO_XGENE=y -CONFIG_GPIO_XGENE_SB=m # CONFIG_GPIO_XILINX is not set # CONFIG_GPIO_AMD_FCH is not set # end of Memory mapped GPIO drivers @@ -4491,7 +4254,6 @@ CONFIG_W1_CON=y # CONFIG_W1_MASTER_MATROX is not set CONFIG_W1_MASTER_DS2490=m CONFIG_W1_MASTER_DS2482=m -# CONFIG_W1_MASTER_MXC is not set CONFIG_W1_MASTER_DS1WM=m # CONFIG_W1_MASTER_GPIO is not set # CONFIG_W1_MASTER_SGI is not set @@ -4525,10 +4287,6 @@ CONFIG_POWER_RESET=y # CONFIG_POWER_RESET_BRCMSTB is not set CONFIG_POWER_RESET_GPIO=y CONFIG_POWER_RESET_GPIO_RESTART=y -CONFIG_POWER_RESET_HISI=y -# CONFIG_POWER_RESET_LINKSTATION is not set -CONFIG_POWER_RESET_MSM=y -CONFIG_POWER_RESET_QCOM_PON=m # CONFIG_POWER_RESET_LTC2952 is not set # CONFIG_POWER_RESET_REGULATOR is not set CONFIG_POWER_RESET_RESTART=y @@ -4570,7 +4328,6 @@ CONFIG_BATTERY_MAX17042=m # CONFIG_CHARGER_LT3651 is not set # CONFIG_CHARGER_LTC4162L is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set -CONFIG_CHARGER_QCOM_SMBB=m # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_BQ24190 is not set # CONFIG_CHARGER_BQ24257 is not set @@ -4737,7 +4494,6 @@ CONFIG_SENSORS_UCD9200=m # CONFIG_SENSORS_XDPE122 is not set CONFIG_SENSORS_ZL6100=m CONFIG_SENSORS_PWM_FAN=m -CONFIG_SENSORS_RASPBERRYPI_HWMON=m CONFIG_SENSORS_SL28CPLD=m # CONFIG_SENSORS_SBTSI is not set CONFIG_SENSORS_SHT15=m @@ -4814,42 +4570,10 @@ CONFIG_CPU_FREQ_THERMAL=y CONFIG_DEVFREQ_THERMAL=y CONFIG_THERMAL_EMULATION=y # CONFIG_THERMAL_MMIO is not set -CONFIG_HISI_THERMAL=m -# CONFIG_IMX_THERMAL is not set -CONFIG_IMX_SC_THERMAL=m -CONFIG_IMX8MM_THERMAL=m CONFIG_MAX77620_THERMAL=m # CONFIG_QORIQ_THERMAL is not set CONFIG_SUN8I_THERMAL=m -CONFIG_ROCKCHIP_THERMAL=m -CONFIG_ARMADA_THERMAL=m -CONFIG_MTK_THERMAL=m -CONFIG_AMLOGIC_THERMAL=y - -# -# Broadcom thermal drivers -# -CONFIG_BCM2711_THERMAL=m -CONFIG_BCM2835_THERMAL=m -# end of Broadcom thermal drivers - -# -# NVIDIA Tegra thermal drivers -# -CONFIG_TEGRA_SOCTHERM=m -CONFIG_TEGRA_BPMP_THERMAL=m -# end of NVIDIA Tegra thermal drivers - CONFIG_GENERIC_ADC_THERMAL=m - -# -# Qualcomm thermal drivers -# -CONFIG_QCOM_TSENS=m -# CONFIG_QCOM_SPMI_ADC_TM5 is not set -CONFIG_QCOM_SPMI_TEMP_ALARM=m -# end of Qualcomm thermal drivers - CONFIG_WATCHDOG=y CONFIG_WATCHDOG_CORE=y # CONFIG_WATCHDOG_NOWAYOUT is not set @@ -4873,25 +4597,15 @@ CONFIG_GPIO_WATCHDOG=m CONFIG_SL28CPLD_WATCHDOG=m CONFIG_ARM_SP805_WATCHDOG=m CONFIG_ARM_SBSA_WATCHDOG=m -CONFIG_ARMADA_37XX_WATCHDOG=m # CONFIG_CADENCE_WATCHDOG is not set CONFIG_DW_WATCHDOG=m CONFIG_SUNXI_WATCHDOG=m # CONFIG_MAX63XX_WATCHDOG is not set CONFIG_MAX77620_WATCHDOG=m CONFIG_IMX2_WDT=m -CONFIG_IMX_SC_WDT=m -# CONFIG_IMX7ULP_WDT is not set -# CONFIG_TEGRA_WATCHDOG is not set -CONFIG_QCOM_WDT=m -CONFIG_MESON_GXBB_WATCHDOG=m -CONFIG_MESON_WATCHDOG=m -CONFIG_MEDIATEK_WATCHDOG=m CONFIG_ARM_SMC_WATCHDOG=y -# CONFIG_PM8916_WATCHDOG is not set CONFIG_ALIM7101_WDT=m CONFIG_I6300ESB_WDT=m -CONFIG_BCM2835_WDT=m # CONFIG_MEN_A21_WDT is not set # @@ -4961,7 +4675,6 @@ CONFIG_MFD_CROS_EC_DEV=y # CONFIG_MFD_MC13XXX_I2C is not set # CONFIG_MFD_MP2629 is not set # CONFIG_MFD_HI6421_PMIC is not set -CONFIG_MFD_HI655X_PMIC=y # CONFIG_HTC_PASIC3 is not set # CONFIG_HTC_I2CPLD is not set # CONFIG_LPC_ICH is not set @@ -4993,8 +4706,6 @@ CONFIG_MFD_VIPERBOARD=m # CONFIG_MFD_RETU is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_UCB1400_CORE is not set -CONFIG_MFD_QCOM_RPM=y -CONFIG_MFD_SPMI_PMIC=y # CONFIG_MFD_RDC321X is not set # CONFIG_MFD_RT5033 is not set # CONFIG_MFD_RC5T583 is not set @@ -5053,7 +4764,6 @@ CONFIG_MFD_ROHM_BD718XX=y # CONFIG_MFD_STMFX is not set CONFIG_MFD_WCD934X=m # CONFIG_MFD_ATC260X_I2C is not set -# CONFIG_MFD_KHADAS_MCU is not set CONFIG_MFD_VEXPRESS_SYSREG=y # CONFIG_RAVE_SP_CORE is not set # CONFIG_MFD_INTEL_M10_BMC is not set @@ -5067,7 +4777,6 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_88PG86X is not set # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set -# CONFIG_REGULATOR_ANATOP is not set # CONFIG_REGULATOR_ARM_SCMI is not set CONFIG_REGULATOR_AXP20X=y CONFIG_REGULATOR_BD718XX=y @@ -5078,7 +4787,6 @@ CONFIG_REGULATOR_BD718XX=y CONFIG_REGULATOR_FAN53555=y # CONFIG_REGULATOR_FAN53880 is not set CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_HI655X=y # CONFIG_REGULATOR_ISL9305 is not set # CONFIG_REGULATOR_ISL6271A is not set # CONFIG_REGULATOR_LP3971 is not set @@ -5101,7 +4809,6 @@ CONFIG_REGULATOR_MAX77620=y # CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_MT6315 is not set -# CONFIG_REGULATOR_MT6380 is not set CONFIG_REGULATOR_PCA9450=y # CONFIG_REGULATOR_PF8X00 is not set CONFIG_REGULATOR_PFUZE100=y @@ -5109,9 +4816,6 @@ CONFIG_REGULATOR_PFUZE100=y # CONFIG_REGULATOR_PV88080 is not set # CONFIG_REGULATOR_PV88090 is not set CONFIG_REGULATOR_PWM=y -CONFIG_REGULATOR_QCOM_RPM=y -# CONFIG_REGULATOR_QCOM_RPMH is not set -CONFIG_REGULATOR_QCOM_SMD_RPM=y CONFIG_REGULATOR_QCOM_SPMI=y # CONFIG_REGULATOR_QCOM_USB_VBUS is not set # CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set @@ -5134,7 +4838,6 @@ CONFIG_REGULATOR_TPS65132=m # CONFIG_REGULATOR_TPS6524X is not set CONFIG_REGULATOR_VCTRL=y CONFIG_REGULATOR_VEXPRESS=y -# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set # CONFIG_REGULATOR_QCOM_LABIBB is not set CONFIG_RC_CORE=m CONFIG_RC_MAP=m @@ -5160,8 +4863,6 @@ CONFIG_IR_IMON_RAW=m CONFIG_IR_MCEUSB=m CONFIG_IR_ITE_CIR=m CONFIG_IR_FINTEK=m -CONFIG_IR_MESON=m -CONFIG_IR_MTK=m CONFIG_IR_NUVOTON=m CONFIG_IR_REDRAT3=m CONFIG_IR_SPI=m @@ -5187,9 +4888,6 @@ CONFIG_MEDIA_CEC_RC=y CONFIG_MEDIA_CEC_SUPPORT=y CONFIG_CEC_CH7322=m CONFIG_CEC_CROS_EC=m -CONFIG_CEC_MESON_AO=m -CONFIG_CEC_MESON_G12A_AO=m -CONFIG_CEC_TEGRA=m CONFIG_USB_PULSE8_CEC=m CONFIG_USB_RAINSHADOW_CEC=m CONFIG_MEDIA_SUPPORT=m @@ -5225,7 +4923,6 @@ CONFIG_VIDEO_V4L2_SUBDEV_API=y # CONFIG_VIDEO_ADV_DEBUG is not set # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_VIDEO_TUNER=m -CONFIG_V4L2_H264=m CONFIG_V4L2_MEM2MEM_DEV=m # CONFIG_V4L2_FLASH_LED_CLASS is not set CONFIG_V4L2_FWNODE=m @@ -5541,24 +5238,12 @@ CONFIG_V4L_PLATFORM_DRIVERS=y # CONFIG_VIDEO_CADENCE is not set # CONFIG_VIDEO_ASPEED is not set # CONFIG_VIDEO_MUX is not set -CONFIG_VIDEO_QCOM_CAMSS=m -CONFIG_VIDEO_ROCKCHIP_ISP1=m # CONFIG_VIDEO_XILINX is not set # CONFIG_VIDEO_SUN4I_CSI is not set CONFIG_VIDEO_SUN6I_CSI=m CONFIG_V4L_MEM2MEM_DRIVERS=y -# CONFIG_VIDEO_CODA is not set -# CONFIG_VIDEO_IMX_PXP is not set -# CONFIG_VIDEO_IMX8_JPEG is not set -# CONFIG_VIDEO_MEDIATEK_JPEG is not set -CONFIG_VIDEO_MEDIATEK_VPU=m -CONFIG_VIDEO_MEDIATEK_MDP=m -CONFIG_VIDEO_MEDIATEK_VCODEC=m -CONFIG_VIDEO_MEDIATEK_VCODEC_VPU=y # CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set -# CONFIG_VIDEO_MESON_GE2D is not set -CONFIG_VIDEO_ROCKCHIP_RGA=m -CONFIG_VIDEO_QCOM_VENUS=m +CONFIG_VIDEO_SUN50I_DEINTERLACE=m CONFIG_VIDEO_SUN8I_DEINTERLACE=m # CONFIG_VIDEO_SUN8I_ROTATE is not set # CONFIG_DVB_PLATFORM_DRIVERS is not set @@ -5997,8 +5682,6 @@ CONFIG_DVB_DUMMY_FE=m # CONFIG_VGA_ARB=y CONFIG_VGA_ARB_MAX_GPUS=16 -CONFIG_TEGRA_HOST1X=m -CONFIG_TEGRA_HOST1X_FIREWALL=y CONFIG_DRM=m CONFIG_DRM_MIPI_DSI=y # CONFIG_DRM_DP_AUX_CHARDEV is not set @@ -6039,46 +5722,10 @@ CONFIG_DRM_MALI_DISPLAY=m CONFIG_DRM_RADEON=m CONFIG_DRM_RADEON_USERPTR=y -CONFIG_DRM_AMDGPU=m -# CONFIG_DRM_AMDGPU_SI is not set -# CONFIG_DRM_AMDGPU_CIK is not set -# CONFIG_DRM_AMDGPU_USERPTR is not set - -# -# ACP (Audio CoProcessor) Configuration -# -# CONFIG_DRM_AMD_ACP is not set -# end of ACP (Audio CoProcessor) Configuration - -# -# Display Engine Configuration -# -CONFIG_DRM_AMD_DC=y -# CONFIG_DRM_AMD_DC_HDCP is not set -# CONFIG_DRM_AMD_DC_SI is not set -# CONFIG_DEBUG_KERNEL_DC is not set -# end of Display Engine Configuration - -# CONFIG_HSA_AMD is not set -CONFIG_DRM_NOUVEAU=m -CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT=y -CONFIG_NOUVEAU_PLATFORM_DRIVER=y -CONFIG_NOUVEAU_DEBUG=5 -CONFIG_NOUVEAU_DEBUG_DEFAULT=3 -# CONFIG_NOUVEAU_DEBUG_MMU is not set -# CONFIG_NOUVEAU_DEBUG_PUSH is not set -CONFIG_DRM_NOUVEAU_BACKLIGHT=y +# CONFIG_DRM_AMDGPU is not set +# CONFIG_DRM_NOUVEAU is not set CONFIG_DRM_VGEM=m # CONFIG_DRM_VKMS is not set -CONFIG_DRM_ROCKCHIP=m -CONFIG_ROCKCHIP_ANALOGIX_DP=y -CONFIG_ROCKCHIP_CDN_DP=y -CONFIG_ROCKCHIP_DW_HDMI=y -CONFIG_ROCKCHIP_DW_MIPI_DSI=y -CONFIG_ROCKCHIP_INNO_HDMI=y -CONFIG_ROCKCHIP_LVDS=y -CONFIG_ROCKCHIP_RGB=y -# CONFIG_ROCKCHIP_RK3066_HDMI is not set CONFIG_DRM_UDL=m CONFIG_DRM_AST=m CONFIG_DRM_MGAG200=m @@ -6095,22 +5742,6 @@ CONFIG_DRM_SUN8I_TCON_TOP=m CONFIG_DRM_QXL=m CONFIG_DRM_BOCHS=m CONFIG_DRM_VIRTIO_GPU=m -CONFIG_DRM_MSM=m -CONFIG_DRM_MSM_GPU_STATE=y -# CONFIG_DRM_MSM_REGISTER_LOGGING is not set -# CONFIG_DRM_MSM_GPU_SUDO is not set -CONFIG_DRM_MSM_HDMI_HDCP=y -CONFIG_DRM_MSM_DP=y -CONFIG_DRM_MSM_DSI=y -CONFIG_DRM_MSM_DSI_28NM_PHY=y -CONFIG_DRM_MSM_DSI_20NM_PHY=y -CONFIG_DRM_MSM_DSI_28NM_8960_PHY=y -CONFIG_DRM_MSM_DSI_14NM_PHY=y -CONFIG_DRM_MSM_DSI_10NM_PHY=y -CONFIG_DRM_MSM_DSI_7NM_PHY=y -CONFIG_DRM_TEGRA=m -# CONFIG_DRM_TEGRA_DEBUG is not set -CONFIG_DRM_TEGRA_STAGING=y CONFIG_DRM_PANEL=y # @@ -6220,22 +5851,14 @@ CONFIG_DRM_DW_HDMI=m # CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set CONFIG_DRM_DW_HDMI_I2S_AUDIO=m CONFIG_DRM_DW_HDMI_CEC=m -CONFIG_DRM_DW_MIPI_DSI=m # end of Display Interface Bridges -CONFIG_DRM_IMX_DCSS=m -CONFIG_DRM_VC4=m -CONFIG_DRM_VC4_HDMI_CEC=y CONFIG_DRM_ETNAVIV=m CONFIG_DRM_ETNAVIV_THERMAL=y # CONFIG_DRM_HISI_HIBMC is not set -CONFIG_DRM_HISI_KIRIN=m -CONFIG_DRM_MEDIATEK=m -CONFIG_DRM_MEDIATEK_HDMI=m +# CONFIG_DRM_HISI_KIRIN is not set CONFIG_DRM_MXS=y CONFIG_DRM_MXSFB=m -CONFIG_DRM_MESON=m -CONFIG_DRM_MESON_DW_HDMI=m # CONFIG_DRM_ARCPGU is not set CONFIG_DRM_CIRRUS_QEMU=m # CONFIG_DRM_GM12U320 is not set @@ -6286,7 +5909,6 @@ CONFIG_FB_TILEBLITTING=y # CONFIG_FB_CIRRUS is not set # CONFIG_FB_PM2 is not set # CONFIG_FB_ARMCLCD is not set -# CONFIG_FB_IMX is not set # CONFIG_FB_CYBER2000 is not set # CONFIG_FB_ASILIANT is not set # CONFIG_FB_IMSTT is not set @@ -6320,7 +5942,6 @@ CONFIG_FB_UDL=m CONFIG_FB_VIRTUAL=m # CONFIG_FB_METRONOME is not set # CONFIG_FB_MB862XX is not set -CONFIG_FB_MX3=y CONFIG_FB_SIMPLE=y CONFIG_FB_SSD1307=m # CONFIG_FB_SM712 is not set @@ -6391,7 +6012,6 @@ CONFIG_SND_DMAENGINE_PCM=y CONFIG_SND_HWDEP=m CONFIG_SND_SEQ_DEVICE=m CONFIG_SND_RAWMIDI=m -CONFIG_SND_COMPRESS_OFFLOAD=y CONFIG_SND_JACK=y CONFIG_SND_JACK_INPUT_DEV=y CONFIG_SND_OSSEMUL=y @@ -6505,7 +6125,6 @@ CONFIG_SND_YMFPCI=m CONFIG_SND_HDA=m CONFIG_SND_HDA_GENERIC_LEDS=y CONFIG_SND_HDA_INTEL=m -CONFIG_SND_HDA_TEGRA=m CONFIG_SND_HDA_HWDEP=y CONFIG_SND_HDA_RECONFIG=y CONFIG_SND_HDA_INPUT_BEEP=y @@ -6530,8 +6149,6 @@ CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0 CONFIG_SND_HDA_CORE=m CONFIG_SND_HDA_DSP_LOADER=y -CONFIG_SND_HDA_ALIGNED_MMIO=y -CONFIG_SND_HDA_COMPONENT=y CONFIG_SND_HDA_PREALLOC_SIZE=4096 CONFIG_SND_INTEL_NHLT=y CONFIG_SND_INTEL_DSP_CONFIG=m @@ -6553,13 +6170,11 @@ CONFIG_SND_USB_TONEPORT=m CONFIG_SND_USB_VARIAX=m CONFIG_SND_SOC=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y -CONFIG_SND_SOC_COMPRESS=y # CONFIG_SND_SOC_ADI is not set CONFIG_SND_SOC_AMD_ACP=m # CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH is not set # CONFIG_SND_SOC_AMD_CZ_RT5645_MACH is not set # CONFIG_SND_ATMEL_SOC is not set -CONFIG_SND_BCM2835_SOC_I2S=m # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set # CONFIG_SND_DESIGNWARE_I2S is not set @@ -6580,90 +6195,13 @@ CONFIG_SND_SOC_FSL_SPDIF=m CONFIG_SND_SOC_FSL_MICFIL=m CONFIG_SND_SOC_FSL_EASRC=m # CONFIG_SND_SOC_FSL_XCVR is not set -# CONFIG_SND_SOC_FSL_AUD2HTX is not set # CONFIG_SND_SOC_FSL_RPMSG is not set -CONFIG_SND_SOC_IMX_PCM_DMA=m # CONFIG_SND_SOC_IMX_AUDMUX is not set -CONFIG_SND_IMX_SOC=m - -# -# SoC Audio support for Freescale i.MX boards: -# -# CONFIG_SND_SOC_IMX_ES8328 is not set -# CONFIG_SND_SOC_IMX_SGTL5000 is not set -CONFIG_SND_SOC_IMX_SPDIF=m -# CONFIG_SND_SOC_FSL_ASOC_CARD is not set -CONFIG_SND_SOC_IMX_AUDMIX=m -# CONFIG_SND_SOC_IMX_HDMI is not set -# CONFIG_SND_SOC_IMX_RPMSG is not set # end of SoC Audio for Freescale CPUs CONFIG_SND_I2S_HI6210_I2S=m -# CONFIG_SND_KIRKWOOD_SOC is not set # CONFIG_SND_SOC_IMG is not set -CONFIG_SND_SOC_MEDIATEK=m -# CONFIG_SND_SOC_MT2701 is not set -# CONFIG_SND_SOC_MT6797 is not set -CONFIG_SND_SOC_MT8173=m -CONFIG_SND_SOC_MT8173_MAX98090=m -CONFIG_SND_SOC_MT8173_RT5650=m -CONFIG_SND_SOC_MT8173_RT5650_RT5514=m -CONFIG_SND_SOC_MT8173_RT5650_RT5676=m -# CONFIG_SND_SOC_MT8183 is not set # CONFIG_SND_SOC_MTK_BTCVSD is not set -# CONFIG_SND_SOC_MT8192 is not set - -# -# ASoC support for Amlogic platforms -# -CONFIG_SND_MESON_AIU=m -# CONFIG_SND_MESON_AXG_FRDDR is not set -# CONFIG_SND_MESON_AXG_TODDR is not set -CONFIG_SND_MESON_AXG_TDM_FORMATTER=m -CONFIG_SND_MESON_AXG_TDM_INTERFACE=m -# CONFIG_SND_MESON_AXG_TDMIN is not set -# CONFIG_SND_MESON_AXG_TDMOUT is not set -CONFIG_SND_MESON_AXG_SOUND_CARD=m -# CONFIG_SND_MESON_AXG_SPDIFOUT is not set -# CONFIG_SND_MESON_AXG_SPDIFIN is not set -# CONFIG_SND_MESON_AXG_PDM is not set -CONFIG_SND_MESON_CARD_UTILS=m -CONFIG_SND_MESON_CODEC_GLUE=m -CONFIG_SND_MESON_GX_SOUND_CARD=m -# CONFIG_SND_MESON_G12A_TOACODEC is not set -CONFIG_SND_MESON_G12A_TOHDMITX=m -CONFIG_SND_SOC_MESON_T9015=m -# end of ASoC support for Amlogic platforms - -CONFIG_SND_SOC_QCOM=m -CONFIG_SND_SOC_LPASS_CPU=m -CONFIG_SND_SOC_LPASS_PLATFORM=m -CONFIG_SND_SOC_LPASS_APQ8016=m -# CONFIG_SND_SOC_STORM is not set -CONFIG_SND_SOC_APQ8016_SBC=m -CONFIG_SND_SOC_QCOM_COMMON=m -CONFIG_SND_SOC_QDSP6_COMMON=m -CONFIG_SND_SOC_QDSP6_CORE=m -CONFIG_SND_SOC_QDSP6_AFE=m -CONFIG_SND_SOC_QDSP6_AFE_DAI=m -CONFIG_SND_SOC_QDSP6_AFE_CLOCKS=m -CONFIG_SND_SOC_QDSP6_ADM=m -CONFIG_SND_SOC_QDSP6_ROUTING=m -CONFIG_SND_SOC_QDSP6_ASM=m -CONFIG_SND_SOC_QDSP6_ASM_DAI=m -CONFIG_SND_SOC_QDSP6=m -CONFIG_SND_SOC_MSM8996=m -CONFIG_SND_SOC_SDM845=m -# CONFIG_SND_SOC_SM8250 is not set -# CONFIG_SND_SOC_SC7180 is not set -CONFIG_SND_SOC_ROCKCHIP=m -CONFIG_SND_SOC_ROCKCHIP_I2S=m -CONFIG_SND_SOC_ROCKCHIP_PDM=m -CONFIG_SND_SOC_ROCKCHIP_SPDIF=m -CONFIG_SND_SOC_ROCKCHIP_MAX98090=m -CONFIG_SND_SOC_ROCKCHIP_RT5645=m -CONFIG_SND_SOC_RK3288_HDMI_ANALOG=m -CONFIG_SND_SOC_RK3399_GRU_SOUND=m # CONFIG_SND_SOC_SOF_TOPLEVEL is not set # @@ -6683,28 +6221,6 @@ CONFIG_SND_SUN4I_SPDIF=m CONFIG_SND_SUN8I_ADDA_PR_REGMAP=m # end of Allwinner SoC Audio support -CONFIG_SND_SOC_TEGRA=m -# CONFIG_SND_SOC_TEGRA20_AC97 is not set -# CONFIG_SND_SOC_TEGRA20_DAS is not set -# CONFIG_SND_SOC_TEGRA20_I2S is not set -# CONFIG_SND_SOC_TEGRA20_SPDIF is not set -# CONFIG_SND_SOC_TEGRA30_AHUB is not set -# CONFIG_SND_SOC_TEGRA30_I2S is not set -CONFIG_SND_SOC_TEGRA210_AHUB=m -CONFIG_SND_SOC_TEGRA210_DMIC=m -CONFIG_SND_SOC_TEGRA210_I2S=m -CONFIG_SND_SOC_TEGRA186_DSPK=m -CONFIG_SND_SOC_TEGRA210_ADMAIF=m -# CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD is not set -# CONFIG_SND_SOC_TEGRA_RT5640 is not set -# CONFIG_SND_SOC_TEGRA_WM8753 is not set -# CONFIG_SND_SOC_TEGRA_WM8903 is not set -# CONFIG_SND_SOC_TEGRA_WM9712 is not set -# CONFIG_SND_SOC_TEGRA_TRIMSLICE is not set -# CONFIG_SND_SOC_TEGRA_ALC5632 is not set -# CONFIG_SND_SOC_TEGRA_MAX98090 is not set -# CONFIG_SND_SOC_TEGRA_RT5677 is not set -# CONFIG_SND_SOC_TEGRA_SGTL5000 is not set # CONFIG_SND_SOC_XILINX_I2S is not set # CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set # CONFIG_SND_SOC_XILINX_SPDIF is not set @@ -6757,7 +6273,6 @@ CONFIG_SND_SOC_CROS_EC_CODEC=m # CONFIG_SND_SOC_CS53L30 is not set # CONFIG_SND_SOC_CX2072X is not set # CONFIG_SND_SOC_DA7213 is not set -CONFIG_SND_SOC_DA7219=m CONFIG_SND_SOC_DMIC=m CONFIG_SND_SOC_HDMI_CODEC=m # CONFIG_SND_SOC_ES7134 is not set @@ -6769,7 +6284,6 @@ CONFIG_SND_SOC_ES8328_SPI=m # CONFIG_SND_SOC_GTM601 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set -CONFIG_SND_SOC_MAX98090=m CONFIG_SND_SOC_MAX98357A=m # CONFIG_SND_SOC_MAX98504 is not set # CONFIG_SND_SOC_MAX9867 is not set @@ -6795,18 +6309,11 @@ CONFIG_SND_SOC_PCM3168A_I2C=m # CONFIG_SND_SOC_PCM512x_I2C is not set # CONFIG_SND_SOC_PCM512x_SPI is not set CONFIG_SND_SOC_RK3328=m -CONFIG_SND_SOC_RL6231=m # CONFIG_SND_SOC_RT1308_SDW is not set # CONFIG_SND_SOC_RT1316_SDW is not set -CONFIG_SND_SOC_RT5514=m -CONFIG_SND_SOC_RT5514_SPI=m # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set -CONFIG_SND_SOC_RT5645=m # CONFIG_SND_SOC_RT5659 is not set -CONFIG_SND_SOC_RT5663=m -CONFIG_SND_SOC_RT5677=m -CONFIG_SND_SOC_RT5677_SPI=m # CONFIG_SND_SOC_RT5682_SDW is not set # CONFIG_SND_SOC_RT700_SDW is not set # CONFIG_SND_SOC_RT711_SDW is not set @@ -6877,8 +6384,6 @@ CONFIG_SND_SOC_WSA881X=m # CONFIG_SND_SOC_MAX9759 is not set # CONFIG_SND_SOC_MT6351 is not set # CONFIG_SND_SOC_MT6358 is not set -# CONFIG_SND_SOC_MT6359 is not set -# CONFIG_SND_SOC_MT6359_ACCDET is not set # CONFIG_SND_SOC_MT6660 is not set # CONFIG_SND_SOC_NAU8315 is not set # CONFIG_SND_SOC_NAU8540 is not set @@ -7077,17 +6582,11 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y # CONFIG_USB_XHCI_PCI_RENESAS is not set CONFIG_USB_XHCI_PLATFORM=y -# CONFIG_USB_XHCI_HISTB is not set -CONFIG_USB_XHCI_MTK=y -CONFIG_USB_XHCI_MVEBU=y -CONFIG_USB_XHCI_TEGRA=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_TT_NEWSCHED=y CONFIG_USB_EHCI_PCI=y # CONFIG_USB_EHCI_FSL is not set -CONFIG_USB_EHCI_HCD_ORION=y -CONFIG_USB_EHCI_TEGRA=y CONFIG_USB_EHCI_HCD_PLATFORM=y # CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set @@ -7151,7 +6650,6 @@ CONFIG_USBIP_HOST=m CONFIG_USBIP_VUDC=m # CONFIG_USBIP_DEBUG is not set # CONFIG_USB_CDNS_SUPPORT is not set -# CONFIG_USB_MTU3 is not set CONFIG_USB_MUSB_HDRC=y # CONFIG_USB_MUSB_HOST is not set # CONFIG_USB_MUSB_GADGET is not set @@ -7161,7 +6659,6 @@ CONFIG_USB_MUSB_DUAL_ROLE=y # Platform Glue Layer # CONFIG_USB_MUSB_SUNXI=y -# CONFIG_USB_MUSB_MEDIATEK is not set # # MUSB DMA mode @@ -7178,10 +6675,7 @@ CONFIG_USB_DWC3_DUAL_ROLE=y # CONFIG_USB_DWC3_PCI=y CONFIG_USB_DWC3_HAPS=y -CONFIG_USB_DWC3_MESON_G12A=y CONFIG_USB_DWC3_OF_SIMPLE=y -CONFIG_USB_DWC3_QCOM=y -CONFIG_USB_DWC3_IMX8MP=y CONFIG_USB_DWC2=y # CONFIG_USB_DWC2_HOST is not set @@ -7310,8 +6804,6 @@ CONFIG_USB_PHY=y CONFIG_NOP_USB_XCEIV=y CONFIG_USB_GPIO_VBUS=y CONFIG_USB_ISP1301=y -# CONFIG_USB_MXS_PHY is not set -CONFIG_USB_TEGRA_PHY=y CONFIG_USB_ULPI=y CONFIG_USB_ULPI_VIEWPORT=y # end of USB Physical Layer drivers @@ -7343,7 +6835,6 @@ CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 # CONFIG_USB_EG20T is not set # CONFIG_USB_GADGET_XILINX is not set # CONFIG_USB_MAX3420_UDC is not set -CONFIG_USB_TEGRA_XUDC=m # CONFIG_USB_DUMMY_HCD is not set # end of USB Peripheral Controller @@ -7432,7 +6923,6 @@ CONFIG_TYPEC_FUSB302=y CONFIG_TYPEC_TPS6598X=m CONFIG_TYPEC_HD3SS3220=m # CONFIG_TYPEC_STUSB160X is not set -# CONFIG_TYPEC_QCOM_PMIC is not set # # USB Type-C Multiplexer/DeMultiplexer Switch support @@ -7461,7 +6951,6 @@ CONFIG_SDIO_UART=m # # CONFIG_MMC_DEBUG is not set CONFIG_MMC_ARMMMCI=y -CONFIG_MMC_QCOM_DML=y # CONFIG_MMC_STM32_SDMMC is not set CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_IO_ACCESSORS=y @@ -7475,16 +6964,8 @@ CONFIG_MMC_SDHCI_OF_AT91=y # CONFIG_MMC_SDHCI_OF_ESDHC is not set # CONFIG_MMC_SDHCI_OF_DWCMSHC is not set CONFIG_MMC_SDHCI_CADENCE=y -CONFIG_MMC_SDHCI_ESDHC_IMX=y -CONFIG_MMC_SDHCI_TEGRA=y -CONFIG_MMC_SDHCI_PXAV3=y CONFIG_MMC_SDHCI_F_SDH30=y # CONFIG_MMC_SDHCI_MILBEAUT is not set -CONFIG_MMC_SDHCI_IPROC=y -CONFIG_MMC_MESON_GX=y -# CONFIG_MMC_MESON_MX_SDIO is not set -CONFIG_MMC_SDHCI_MSM=y -# CONFIG_MMC_MXC is not set CONFIG_MMC_TIFM_SD=y CONFIG_MMC_SPI=y CONFIG_MMC_CB710=y @@ -7496,7 +6977,6 @@ CONFIG_MMC_DW_EXYNOS=y # CONFIG_MMC_DW_HI3798CV200 is not set CONFIG_MMC_DW_K3=y CONFIG_MMC_DW_PCI=y -CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_VUB300=m CONFIG_MMC_USHC=m CONFIG_MMC_USDHI6ROL0=y @@ -7504,7 +6984,6 @@ CONFIG_MMC_SUNXI=y CONFIG_MMC_CQHCI=y # CONFIG_MMC_HSQ is not set CONFIG_MMC_TOSHIBA_PCI=y -CONFIG_MMC_BCM2835=y CONFIG_MMC_MTK=y CONFIG_MMC_SDHCI_XENON=y # CONFIG_MMC_SDHCI_OMAP is not set @@ -7744,25 +7223,12 @@ CONFIG_RTC_DRV_CROS_EC=y # # on-CPU RTC drivers # -# CONFIG_RTC_DRV_IMXDI is not set CONFIG_RTC_DRV_FSL_FTM_ALARM=m -CONFIG_RTC_DRV_MESON_VRTC=m # CONFIG_RTC_DRV_PL030 is not set CONFIG_RTC_DRV_PL031=y CONFIG_RTC_DRV_SUN6I=y -# CONFIG_RTC_DRV_MV is not set -CONFIG_RTC_DRV_ARMADA38X=y # CONFIG_RTC_DRV_CADENCE is not set # CONFIG_RTC_DRV_FTRTC010 is not set -CONFIG_RTC_DRV_PM8XXX=y -# CONFIG_RTC_DRV_TEGRA is not set -# CONFIG_RTC_DRV_MXC is not set -# CONFIG_RTC_DRV_MXC_V2 is not set -CONFIG_RTC_DRV_SNVS=m -CONFIG_RTC_DRV_IMX_SC=y -# CONFIG_RTC_DRV_MT2712 is not set -CONFIG_RTC_DRV_MT7622=y -CONFIG_RTC_DRV_XGENE=m # CONFIG_RTC_DRV_R7301 is not set # @@ -7784,33 +7250,18 @@ CONFIG_DMA_OF=y # CONFIG_ALTERA_MSGDMA is not set # CONFIG_AMBA_PL08X is not set # CONFIG_BCM_SBA_RAID is not set -CONFIG_DMA_BCM2835=y CONFIG_DMA_SUN6I=y # CONFIG_DW_AXI_DMAC is not set # CONFIG_FSL_EDMA is not set # CONFIG_FSL_QDMA is not set # CONFIG_HISI_DMA is not set -# CONFIG_IMX_DMA is not set -CONFIG_IMX_SDMA=y # CONFIG_INTEL_IDMA64 is not set -# CONFIG_K3_DMA is not set -CONFIG_MV_XOR=y CONFIG_MV_XOR_V2=y -# CONFIG_MXS_DMA is not set -CONFIG_MX3_IPU=y -CONFIG_MX3_IPU_IRQS=4 CONFIG_PL330_DMA=y # CONFIG_PLX_DMA is not set -CONFIG_TEGRA20_APB_DMA=y -CONFIG_TEGRA210_ADMA=m -CONFIG_XGENE_DMA=m # CONFIG_XILINX_DMA is not set # CONFIG_XILINX_ZYNQMP_DMA is not set # CONFIG_XILINX_ZYNQMP_DPDMA is not set -# CONFIG_MTK_HSDMA is not set -# CONFIG_MTK_CQDMA is not set -CONFIG_QCOM_BAM_DMA=y -# CONFIG_QCOM_GPI_DMA is not set CONFIG_QCOM_HIDMA_MGMT=y CONFIG_QCOM_HIDMA=y CONFIG_DW_DMAC_CORE=m @@ -7976,19 +7427,10 @@ CONFIG_AD2S1210=m # end of IIO staging drivers # CONFIG_FB_SM750 is not set -# CONFIG_MFD_NVEC is not set CONFIG_STAGING_MEDIA=y -CONFIG_VIDEO_HANTRO=m -CONFIG_VIDEO_HANTRO_IMX8M=y -CONFIG_VIDEO_HANTRO_ROCKCHIP=y -# CONFIG_VIDEO_IMX_MEDIA is not set -CONFIG_VIDEO_MESON_VDEC=m -CONFIG_VIDEO_ROCKCHIP_VDEC=m CONFIG_VIDEO_SUNXI=y CONFIG_VIDEO_SUNXI_CEDRUS=m -# CONFIG_TEGRA_VDE is not set # CONFIG_VIDEO_ZORAN is not set -# CONFIG_VIDEO_TEGRA is not set # # Android @@ -8033,18 +7475,12 @@ CONFIG_FB_TFT_UC1701=m CONFIG_FB_TFT_UPD161704=m CONFIG_FB_TFT_WATTEROTT=m # CONFIG_KS7010 is not set -CONFIG_BCM_VIDEOCORE=y -CONFIG_BCM2835_VCHIQ=y -CONFIG_SND_BCM2835=m -CONFIG_VIDEO_BCM2835=m -CONFIG_BCM2835_VCHIQ_MMAL=m # CONFIG_PI433 is not set # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set # CONFIG_KPC2000 is not set # CONFIG_QLGE is not set # CONFIG_WFX is not set -# CONFIG_PHY_HI3670_USB is not set # CONFIG_SPMI_HISI3670 is not set # CONFIG_MFD_HI6421_SPMI is not set # CONFIG_GOLDFISH is not set @@ -8083,7 +7519,6 @@ CONFIG_CLK_VEXPRESS_OSC=y # CONFIG_COMMON_CLK_MAX77686 is not set # CONFIG_COMMON_CLK_MAX9485 is not set CONFIG_COMMON_CLK_RK808=y -# CONFIG_COMMON_CLK_HI655X is not set CONFIG_COMMON_CLK_SCMI=y CONFIG_COMMON_CLK_SCPI=y # CONFIG_COMMON_CLK_SI5341 is not set @@ -8105,193 +7540,6 @@ CONFIG_COMMON_CLK_PWM=y # CONFIG_COMMON_CLK_VC5 is not set CONFIG_COMMON_CLK_BD718XX=m # CONFIG_COMMON_CLK_FIXED_MMIO is not set -CONFIG_CLK_BCM2711_DVP=y -CONFIG_CLK_BCM2835=y -CONFIG_CLK_RASPBERRYPI=y -CONFIG_COMMON_CLK_HI3516CV300=y -CONFIG_COMMON_CLK_HI3519=y -CONFIG_COMMON_CLK_HI3660=y -CONFIG_COMMON_CLK_HI3670=y -CONFIG_COMMON_CLK_HI3798CV200=y -CONFIG_COMMON_CLK_HI6220=y -CONFIG_RESET_HISI=y -CONFIG_STUB_CLK_HI6220=y -# CONFIG_STUB_CLK_HI3660 is not set -CONFIG_MXC_CLK=y -CONFIG_MXC_CLK_SCU=y -CONFIG_CLK_IMX8MM=y -CONFIG_CLK_IMX8MN=y -CONFIG_CLK_IMX8MP=y -CONFIG_CLK_IMX8MQ=y -CONFIG_CLK_IMX8QXP=y - -# -# Clock driver for MediaTek SoC -# -CONFIG_COMMON_CLK_MEDIATEK=y -CONFIG_COMMON_CLK_MT2712=y -# CONFIG_COMMON_CLK_MT2712_BDPSYS is not set -# CONFIG_COMMON_CLK_MT2712_IMGSYS is not set -# CONFIG_COMMON_CLK_MT2712_JPGDECSYS is not set -# CONFIG_COMMON_CLK_MT2712_MFGCFG is not set -# CONFIG_COMMON_CLK_MT2712_MMSYS is not set -# CONFIG_COMMON_CLK_MT2712_VDECSYS is not set -# CONFIG_COMMON_CLK_MT2712_VENCSYS is not set -CONFIG_COMMON_CLK_MT6765=y -# CONFIG_COMMON_CLK_MT6765_AUDIOSYS is not set -# CONFIG_COMMON_CLK_MT6765_CAMSYS is not set -# CONFIG_COMMON_CLK_MT6765_GCESYS is not set -# CONFIG_COMMON_CLK_MT6765_MMSYS is not set -# CONFIG_COMMON_CLK_MT6765_IMGSYS is not set -# CONFIG_COMMON_CLK_MT6765_VCODECSYS is not set -# CONFIG_COMMON_CLK_MT6765_MFGSYS is not set -# CONFIG_COMMON_CLK_MT6765_MIPI0ASYS is not set -# CONFIG_COMMON_CLK_MT6765_MIPI0BSYS is not set -# CONFIG_COMMON_CLK_MT6765_MIPI1ASYS is not set -# CONFIG_COMMON_CLK_MT6765_MIPI1BSYS is not set -# CONFIG_COMMON_CLK_MT6765_MIPI2ASYS is not set -# CONFIG_COMMON_CLK_MT6765_MIPI2BSYS is not set -CONFIG_COMMON_CLK_MT6779=y -# CONFIG_COMMON_CLK_MT6779_MMSYS is not set -# CONFIG_COMMON_CLK_MT6779_IMGSYS is not set -# CONFIG_COMMON_CLK_MT6779_IPESYS is not set -# CONFIG_COMMON_CLK_MT6779_CAMSYS is not set -# CONFIG_COMMON_CLK_MT6779_VDECSYS is not set -# CONFIG_COMMON_CLK_MT6779_VENCSYS is not set -# CONFIG_COMMON_CLK_MT6779_MFGCFG is not set -# CONFIG_COMMON_CLK_MT6779_AUDSYS is not set -CONFIG_COMMON_CLK_MT6797=y -# CONFIG_COMMON_CLK_MT6797_MMSYS is not set -# CONFIG_COMMON_CLK_MT6797_IMGSYS is not set -# CONFIG_COMMON_CLK_MT6797_VDECSYS is not set -# CONFIG_COMMON_CLK_MT6797_VENCSYS is not set -CONFIG_COMMON_CLK_MT7622=y -# CONFIG_COMMON_CLK_MT7622_ETHSYS is not set -# CONFIG_COMMON_CLK_MT7622_HIFSYS is not set -# CONFIG_COMMON_CLK_MT7622_AUDSYS is not set -CONFIG_COMMON_CLK_MT8167=y -CONFIG_COMMON_CLK_MT8167_AUDSYS=y -CONFIG_COMMON_CLK_MT8167_IMGSYS=y -CONFIG_COMMON_CLK_MT8167_MFGCFG=y -CONFIG_COMMON_CLK_MT8167_MMSYS=y -CONFIG_COMMON_CLK_MT8167_VDECSYS=y -CONFIG_COMMON_CLK_MT8173=y -CONFIG_COMMON_CLK_MT8173_MMSYS=y -CONFIG_COMMON_CLK_MT8183=y -# CONFIG_COMMON_CLK_MT8183_AUDIOSYS is not set -# CONFIG_COMMON_CLK_MT8183_CAMSYS is not set -# CONFIG_COMMON_CLK_MT8183_IMGSYS is not set -# CONFIG_COMMON_CLK_MT8183_IPU_CORE0 is not set -# CONFIG_COMMON_CLK_MT8183_IPU_CORE1 is not set -# CONFIG_COMMON_CLK_MT8183_IPU_ADL is not set -# CONFIG_COMMON_CLK_MT8183_IPU_CONN is not set -# CONFIG_COMMON_CLK_MT8183_MFGCFG is not set -# CONFIG_COMMON_CLK_MT8183_MMSYS is not set -# CONFIG_COMMON_CLK_MT8183_VDECSYS is not set -# CONFIG_COMMON_CLK_MT8183_VENCSYS is not set -CONFIG_COMMON_CLK_MT8516=y -# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set -# end of Clock driver for MediaTek SoC - -# -# Clock support for Amlogic platforms -# -CONFIG_COMMON_CLK_MESON_REGMAP=y -CONFIG_COMMON_CLK_MESON_DUALDIV=y -CONFIG_COMMON_CLK_MESON_MPLL=y -CONFIG_COMMON_CLK_MESON_PLL=y -CONFIG_COMMON_CLK_MESON_VID_PLL_DIV=y -CONFIG_COMMON_CLK_MESON_AO_CLKC=y -CONFIG_COMMON_CLK_MESON_EE_CLKC=y -CONFIG_COMMON_CLK_MESON_CPU_DYNDIV=y -CONFIG_COMMON_CLK_GXBB=y -CONFIG_COMMON_CLK_AXG=y -# CONFIG_COMMON_CLK_AXG_AUDIO is not set -CONFIG_COMMON_CLK_G12A=y -# end of Clock support for Amlogic platforms - -CONFIG_ARMADA_AP_CP_HELPER=y -CONFIG_ARMADA_37XX_CLK=y -CONFIG_ARMADA_AP806_SYSCON=y -CONFIG_ARMADA_AP_CPU_CLK=y -CONFIG_ARMADA_CP110_SYSCON=y -CONFIG_QCOM_GDSC=y -CONFIG_QCOM_RPMCC=y -CONFIG_COMMON_CLK_QCOM=y -CONFIG_QCOM_A53PLL=y -# CONFIG_QCOM_A7PLL is not set -CONFIG_QCOM_CLK_APCS_MSM8916=y -# CONFIG_QCOM_CLK_APCC_MSM8996 is not set -# CONFIG_QCOM_CLK_APCS_SDX55 is not set -CONFIG_QCOM_CLK_RPM=y -CONFIG_QCOM_CLK_SMD_RPM=y -# CONFIG_QCOM_CLK_RPMH is not set -# CONFIG_APQ_GCC_8084 is not set -# CONFIG_APQ_MMCC_8084 is not set -# CONFIG_IPQ_APSS_PLL is not set -# CONFIG_IPQ_APSS_6018 is not set -# CONFIG_IPQ_GCC_4019 is not set -CONFIG_IPQ_GCC_6018=y -# CONFIG_IPQ_GCC_806X is not set -# CONFIG_IPQ_LCC_806X is not set -# CONFIG_IPQ_GCC_8074 is not set -# CONFIG_MSM_GCC_8660 is not set -CONFIG_MSM_GCC_8916=y -# CONFIG_MSM_GCC_8939 is not set -CONFIG_MSM_GCC_8960=y -CONFIG_MSM_LCC_8960=y -# CONFIG_MDM_GCC_9615 is not set -# CONFIG_MDM_LCC_9615 is not set -# CONFIG_MSM_MMCC_8960 is not set -# CONFIG_MSM_GCC_8974 is not set -# CONFIG_MSM_MMCC_8974 is not set -CONFIG_MSM_GCC_8994=y -CONFIG_MSM_GCC_8996=y -CONFIG_MSM_MMCC_8996=y -# CONFIG_MSM_GCC_8998 is not set -# CONFIG_MSM_GPUCC_8998 is not set -# CONFIG_MSM_MMCC_8998 is not set -# CONFIG_QCS_GCC_404 is not set -# CONFIG_SC_CAMCC_7180 is not set -# CONFIG_SC_DISPCC_7180 is not set -CONFIG_SC_GCC_7180=y -# CONFIG_SC_GCC_7280 is not set -# CONFIG_SC_GCC_8180X is not set -# CONFIG_SC_LPASS_CORECC_7180 is not set -# CONFIG_SC_GPUCC_7180 is not set -# CONFIG_SC_MSS_7180 is not set -# CONFIG_SC_VIDEOCC_7180 is not set -CONFIG_SDM_CAMCC_845=m -# CONFIG_SDM_GCC_660 is not set -# CONFIG_SDM_MMCC_660 is not set -# CONFIG_SDM_GPUCC_660 is not set -# CONFIG_QCS_TURING_404 is not set -# CONFIG_QCS_Q6SSTOP_404 is not set -CONFIG_SDM_GCC_845=y -CONFIG_SDM_GPUCC_845=y -CONFIG_SDM_VIDEOCC_845=y -CONFIG_SDM_DISPCC_845=y -# CONFIG_SDM_LPASSCC_845 is not set -# CONFIG_SDX_GCC_55 is not set -# CONFIG_SM_DISPCC_8250 is not set -CONFIG_SM_GCC_8150=y -CONFIG_SM_GCC_8250=y -# CONFIG_SM_GCC_8350 is not set -CONFIG_SM_GPUCC_8150=y -CONFIG_SM_GPUCC_8250=y -# CONFIG_SM_VIDEOCC_8150 is not set -# CONFIG_SM_VIDEOCC_8250 is not set -CONFIG_SPMI_PMIC_CLKDIV=y -CONFIG_QCOM_HFPLL=y -# CONFIG_KPSS_XCC is not set -# CONFIG_CLK_GFM_LPASS_SM8250 is not set -CONFIG_COMMON_CLK_ROCKCHIP=y -CONFIG_CLK_PX30=y -CONFIG_CLK_RK3308=y -CONFIG_CLK_RK3328=y -CONFIG_CLK_RK3368=y -CONFIG_CLK_RK3399=y -# CONFIG_CLK_RK3568 is not set CONFIG_CLK_SUNXI=y CONFIG_CLK_SUNXI_CLOCKS=y CONFIG_CLK_SUNXI_PRCM_SUN6I=y @@ -8308,11 +7556,8 @@ CONFIG_SUN50I_H6_R_CCU=y CONFIG_SUN8I_H3_CCU=y CONFIG_SUN8I_DE2_CCU=y CONFIG_SUN8I_R_CCU=y -CONFIG_CLK_TEGRA_BPMP=y -CONFIG_TEGRA_CLK_DFLL=y # CONFIG_XILINX_VCU is not set CONFIG_HWSPINLOCK=y -CONFIG_HWSPINLOCK_QCOM=y # # Clock Source drivers @@ -8320,9 +7565,6 @@ CONFIG_HWSPINLOCK_QCOM=y CONFIG_TIMER_OF=y CONFIG_TIMER_ACPI=y CONFIG_TIMER_PROBE=y -CONFIG_CLKSRC_MMIO=y -CONFIG_ROCKCHIP_TIMER=y -CONFIG_TEGRA_TIMER=y CONFIG_ARM_ARCH_TIMER=y CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y @@ -8330,32 +7572,18 @@ CONFIG_FSL_ERRATUM_A008585=y CONFIG_HISILICON_ERRATUM_161010101=y CONFIG_ARM64_ERRATUM_858921=y CONFIG_SUN50I_ERRATUM_UNKNOWN1=y -CONFIG_ARM_TIMER_SP804=y -CONFIG_MTK_TIMER=y -CONFIG_TIMER_IMX_SYS_CTR=y # CONFIG_MICROCHIP_PIT64B is not set # end of Clock Source drivers CONFIG_MAILBOX=y CONFIG_ARM_MHU=y # CONFIG_ARM_MHU_V2 is not set -CONFIG_IMX_MBOX=y CONFIG_PLATFORM_MHU=y # CONFIG_PL320_MBOX is not set -CONFIG_ARMADA_37XX_RWTM_MBOX=y -CONFIG_ROCKCHIP_MBOX=y CONFIG_PCC=y # CONFIG_ALTERA_MBOX is not set -CONFIG_BCM2835_MBOX=y -CONFIG_HI3660_MBOX=y -CONFIG_HI6220_MBOX=y # CONFIG_MAILBOX_TEST is not set -CONFIG_QCOM_APCS_IPC=y -CONFIG_TEGRA_HSP_MBOX=y -# CONFIG_XGENE_SLIMPRO_MBOX is not set -# CONFIG_MTK_CMDQ_MBOX is not set CONFIG_SUN6I_MSGBOX=y -CONFIG_QCOM_IPCC=y CONFIG_IOMMU_IOVA=y CONFIG_IOMMU_API=y CONFIG_IOMMU_SUPPORT=y @@ -8374,16 +7602,12 @@ CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set CONFIG_OF_IOMMU=y CONFIG_IOMMU_DMA=y -CONFIG_ROCKCHIP_IOMMU=y # CONFIG_SUN50I_IOMMU is not set -CONFIG_TEGRA_IOMMU_SMMU=y CONFIG_ARM_SMMU=y # CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y CONFIG_ARM_SMMU_V3=y # CONFIG_ARM_SMMU_V3_SVA is not set -CONFIG_MTK_IOMMU=y -CONFIG_QCOM_IOMMU=y # CONFIG_VIRTIO_IOMMU is not set # @@ -8391,17 +7615,6 @@ CONFIG_QCOM_IOMMU=y # CONFIG_REMOTEPROC=y # CONFIG_REMOTEPROC_CDEV is not set -# CONFIG_IMX_REMOTEPROC is not set -# CONFIG_MTK_SCP is not set -CONFIG_QCOM_PIL_INFO=m -CONFIG_QCOM_RPROC_COMMON=m -CONFIG_QCOM_Q6V5_COMMON=m -# CONFIG_QCOM_Q6V5_ADSP is not set -CONFIG_QCOM_Q6V5_MSS=m -CONFIG_QCOM_Q6V5_PAS=m -# CONFIG_QCOM_Q6V5_WCSS is not set -CONFIG_QCOM_SYSMON=m -CONFIG_QCOM_WCNSS_PIL=m # end of Remoteproc drivers # @@ -8412,8 +7625,6 @@ CONFIG_RPMSG_CHAR=y # CONFIG_RPMSG_NS is not set CONFIG_RPMSG_QCOM_GLINK=y CONFIG_RPMSG_QCOM_GLINK_RPM=y -CONFIG_RPMSG_QCOM_GLINK_SMEM=y -CONFIG_RPMSG_QCOM_SMD=y # CONFIG_RPMSG_VIRTIO is not set # end of Rpmsg drivers @@ -8432,21 +7643,12 @@ CONFIG_SOUNDWIRE_QCOM=m # # Amlogic SoC drivers # -CONFIG_MESON_CANVAS=m -CONFIG_MESON_CLK_MEASURE=y -CONFIG_MESON_GX_SOCINFO=y -CONFIG_MESON_GX_PM_DOMAINS=y -CONFIG_MESON_EE_PM_DOMAINS=y -CONFIG_MESON_SECURE_PM_DOMAINS=y # end of Amlogic SoC drivers # # Broadcom SoC drivers # -CONFIG_BCM2835_POWER=y -CONFIG_RASPBERRYPI_POWER=y # CONFIG_SOC_BRCMSTB is not set -CONFIG_BCM_PMB=y # end of Broadcom SoC drivers # @@ -8465,8 +7667,6 @@ CONFIG_DPAA2_CONSOLE=m # # i.MX SoC drivers # -CONFIG_IMX_GPCV2_PM_DOMAINS=y -CONFIG_SOC_IMX8M=y # end of i.MX SoC drivers # @@ -8476,59 +7676,12 @@ CONFIG_SOC_IMX8M=y # end of Enable LiteX SoC Builder specific drivers # -# MediaTek SoC drivers -# -# CONFIG_MTK_CMDQ is not set -# CONFIG_MTK_DEVAPC is not set -CONFIG_MTK_INFRACFG=y -CONFIG_MTK_PMIC_WRAP=y -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SCPSYS_PM_DOMAINS=y -CONFIG_MTK_MMSYS=y -# end of MediaTek SoC drivers - -# # Qualcomm SoC drivers # -CONFIG_QCOM_AOSS_QMP=y -CONFIG_QCOM_COMMAND_DB=y -CONFIG_QCOM_CPR=y -CONFIG_QCOM_GENI_SE=m -CONFIG_QCOM_GSBI=y -# CONFIG_QCOM_LLCC is not set -CONFIG_QCOM_KRYO_L2_ACCESSORS=y -CONFIG_QCOM_MDT_LOADER=m -# CONFIG_QCOM_OCMEM is not set -CONFIG_QCOM_PDR_HELPERS=m -CONFIG_QCOM_QMI_HELPERS=m -CONFIG_QCOM_RMTFS_MEM=y -CONFIG_QCOM_RPMH=y -CONFIG_QCOM_RPMHPD=y -CONFIG_QCOM_RPMPD=y -CONFIG_QCOM_SMEM=y -CONFIG_QCOM_SMD_RPM=y -CONFIG_QCOM_SMEM_STATE=y -CONFIG_QCOM_SMP2P=y -CONFIG_QCOM_SMSM=y -CONFIG_QCOM_SOCINFO=m -CONFIG_QCOM_WCNSS_CTRL=y -CONFIG_QCOM_APR=m # end of Qualcomm SoC drivers -CONFIG_ROCKCHIP_GRF=y -CONFIG_ROCKCHIP_IODOMAIN=y -CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_SUNXI_MBUS=y CONFIG_SUNXI_SRAM=y -CONFIG_ARCH_TEGRA_132_SOC=y -CONFIG_ARCH_TEGRA_210_SOC=y -CONFIG_ARCH_TEGRA_186_SOC=y -CONFIG_ARCH_TEGRA_194_SOC=y -CONFIG_ARCH_TEGRA_234_SOC=y -CONFIG_SOC_TEGRA_FUSE=y -CONFIG_SOC_TEGRA_FLOWCTRL=y -CONFIG_SOC_TEGRA_PMC=y -CONFIG_SOC_TEGRA_POWERGATE_BPMP=y # CONFIG_SOC_TI is not set # @@ -8543,20 +7696,15 @@ CONFIG_PM_DEVFREQ=y # DEVFREQ Governors # CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y -# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set -# CONFIG_DEVFREQ_GOV_POWERSAVE is not set -# CONFIG_DEVFREQ_GOV_USERSPACE is not set -# CONFIG_DEVFREQ_GOV_PASSIVE is not set +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_DEVFREQ_GOV_PASSIVE=y # # DEVFREQ Drivers # -# CONFIG_ARM_IMX_BUS_DEVFREQ is not set -# CONFIG_ARM_IMX8M_DDRC_DEVFREQ is not set -# CONFIG_ARM_TEGRA_DEVFREQ is not set -CONFIG_ARM_RK3399_DMC_DEVFREQ=y CONFIG_PM_DEVFREQ_EVENT=y -CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y CONFIG_EXTCON=y # @@ -8567,7 +7715,6 @@ CONFIG_EXTCON_ADC_JACK=m CONFIG_EXTCON_GPIO=y # CONFIG_EXTCON_MAX3355 is not set # CONFIG_EXTCON_PTN5150 is not set -CONFIG_EXTCON_QCOM_SPMI_MISC=y # CONFIG_EXTCON_RT8973A is not set # CONFIG_EXTCON_SM5502 is not set CONFIG_EXTCON_USB_GPIO=y @@ -8575,9 +7722,6 @@ CONFIG_EXTCON_USBC_CROS_EC=y # CONFIG_EXTCON_USBC_TUSB320 is not set CONFIG_MEMORY=y # CONFIG_ARM_PL172_MPMC is not set -CONFIG_MTK_SMI=y -CONFIG_TEGRA_MC=y -# CONFIG_TEGRA210_EMC is not set CONFIG_IIO=y CONFIG_IIO_BUFFER=y CONFIG_IIO_BUFFER_CB=y @@ -8676,7 +7820,6 @@ CONFIG_ENVELOPE_DETECTOR=m CONFIG_HI8435=m CONFIG_HX711=m CONFIG_INA2XX_ADC=m -CONFIG_IMX7D_ADC=m CONFIG_LTC2471=m CONFIG_LTC2485=m CONFIG_LTC2496=m @@ -8690,14 +7833,11 @@ CONFIG_MAX9611=m CONFIG_MCP320X=m CONFIG_MCP3422=m CONFIG_MCP3911=m -CONFIG_MEDIATEK_MT6577_AUXADC=m -CONFIG_MESON_SARADC=y CONFIG_NAU7802=m CONFIG_QCOM_VADC_COMMON=y CONFIG_QCOM_SPMI_IADC=m CONFIG_QCOM_SPMI_VADC=y CONFIG_QCOM_SPMI_ADC5=m -CONFIG_ROCKCHIP_SARADC=m CONFIG_SD_ADC_MODULATOR=m CONFIG_TI_ADC081C=m CONFIG_TI_ADC0832=m @@ -9144,30 +8284,18 @@ CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_ATMEL_TCB is not set -CONFIG_PWM_BCM2835=m CONFIG_PWM_CROS_EC=m # CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set -# CONFIG_PWM_HIBVT is not set -# CONFIG_PWM_IMX1 is not set -# CONFIG_PWM_IMX27 is not set -# CONFIG_PWM_IMX_TPM is not set -CONFIG_PWM_MESON=y -CONFIG_PWM_MTK_DISP=m -CONFIG_PWM_MEDIATEK=m # CONFIG_PWM_PCA9685 is not set -# CONFIG_PWM_RASPBERRYPI_POE is not set -CONFIG_PWM_ROCKCHIP=y CONFIG_PWM_SL28CPLD=m CONFIG_PWM_SUN4I=y -# CONFIG_PWM_TEGRA is not set # # IRQ chip support # CONFIG_IRQCHIP=y CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_PM=y CONFIG_ARM_GIC_MAX_NR=1 CONFIG_ARM_GIC_V2M=y CONFIG_ARM_GIC_V3=y @@ -9175,41 +8303,18 @@ CONFIG_ARM_GIC_V3_ITS=y CONFIG_ARM_GIC_V3_ITS_PCI=y CONFIG_ARM_GIC_V3_ITS_FSL_MC=y # CONFIG_AL_FIC is not set -CONFIG_BRCMSTB_L2_IRQ=y -CONFIG_HISILICON_IRQ_MBIGEN=y -CONFIG_IMX_GPCV2=y -CONFIG_MVEBU_GICP=y -CONFIG_MVEBU_ICU=y -CONFIG_MVEBU_ODMI=y -CONFIG_MVEBU_PIC=y -CONFIG_MVEBU_SEI=y CONFIG_LS_EXTIRQ=y CONFIG_LS_SCFG_MSI=y CONFIG_PARTITION_PERCPU=y -CONFIG_QCOM_IRQ_COMBINER=y -CONFIG_MESON_IRQ_GPIO=y -CONFIG_QCOM_PDC=y -CONFIG_IMX_IRQSTEER=y -CONFIG_IMX_INTMUX=y -CONFIG_MST_IRQ=y # end of IRQ chip support # CONFIG_IPACK_BUS is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_IMX7=y -CONFIG_RESET_MESON=y -# CONFIG_RESET_MESON_AUDIO_ARB is not set -CONFIG_RESET_QCOM_AOSS=y -CONFIG_RESET_QCOM_PDC=m -CONFIG_RESET_RASPBERRYPI=y CONFIG_RESET_SCMI=y CONFIG_RESET_SIMPLE=y CONFIG_RESET_SUNXI=y # CONFIG_RESET_TI_SYSCON is not set -CONFIG_COMMON_RESET_HI3660=y -CONFIG_COMMON_RESET_HI6220=y -CONFIG_RESET_TEGRA_BPMP=y # # PHY Subsystem @@ -9221,64 +8326,21 @@ CONFIG_PHY_SUN4I_USB=y CONFIG_PHY_SUN6I_MIPI_DPHY=m # CONFIG_PHY_SUN9I_USB is not set CONFIG_PHY_SUN50I_USB3=y -CONFIG_PHY_MESON8B_USB2=y -CONFIG_PHY_MESON_GXL_USB2=y -CONFIG_PHY_MESON_G12A_USB2=y -CONFIG_PHY_MESON_G12A_USB3_PCIE=y -CONFIG_PHY_MESON_AXG_PCIE=y -CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG=y -CONFIG_PHY_MESON_AXG_MIPI_DPHY=y # CONFIG_BCM_KONA_USB2_PHY is not set -CONFIG_PHY_BRCM_USB=y # CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CADENCE_DPHY is not set # CONFIG_PHY_CADENCE_SIERRA is not set # CONFIG_PHY_CADENCE_SALVO is not set # CONFIG_PHY_FSL_IMX8MQ_USB is not set CONFIG_PHY_MIXEL_MIPI_DPHY=m -CONFIG_PHY_HI6220_USB=y -# CONFIG_PHY_HI3660_USB is not set -# CONFIG_PHY_HISTB_COMBPHY is not set -# CONFIG_PHY_HISI_INNO_USB2 is not set -CONFIG_PHY_MVEBU_A3700_COMPHY=y -CONFIG_PHY_MVEBU_A3700_UTMI=y -# CONFIG_PHY_MVEBU_A38X_COMPHY is not set -CONFIG_PHY_MVEBU_CP110_COMPHY=y -# CONFIG_PHY_MVEBU_CP110_UTMI is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set -# CONFIG_PHY_MTK_TPHY is not set -# CONFIG_PHY_MTK_UFS is not set -# CONFIG_PHY_MTK_XSPHY is not set -CONFIG_PHY_MTK_HDMI=m -CONFIG_PHY_MTK_MIPI_DSI=m # CONFIG_PHY_CPCAP_USB is not set # CONFIG_PHY_MAPPHONE_MDM6600 is not set # CONFIG_PHY_OCELOT_SERDES is not set -# CONFIG_PHY_QCOM_APQ8064_SATA is not set -# CONFIG_PHY_QCOM_IPQ4019_USB is not set -# CONFIG_PHY_QCOM_IPQ806X_SATA is not set -# CONFIG_PHY_QCOM_PCIE2 is not set -CONFIG_PHY_QCOM_QMP=y -CONFIG_PHY_QCOM_QUSB2=y CONFIG_PHY_QCOM_USB_HS=y -CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y CONFIG_PHY_QCOM_USB_HSIC=y -# CONFIG_PHY_QCOM_USB_HS_28NM is not set -# CONFIG_PHY_QCOM_USB_SS is not set -# CONFIG_PHY_QCOM_IPQ806X_USB is not set -CONFIG_PHY_ROCKCHIP_DP=y -CONFIG_PHY_ROCKCHIP_DPHY_RX0=m -CONFIG_PHY_ROCKCHIP_EMMC=y -CONFIG_PHY_ROCKCHIP_INNO_HDMI=y -CONFIG_PHY_ROCKCHIP_INNO_USB2=y -CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m -CONFIG_PHY_ROCKCHIP_PCIE=y -CONFIG_PHY_ROCKCHIP_TYPEC=y -# CONFIG_PHY_ROCKCHIP_USB is not set # CONFIG_PHY_SAMSUNG_USB2 is not set -CONFIG_PHY_TEGRA_XUSB=y -# CONFIG_PHY_TEGRA194_P2U is not set # CONFIG_PHY_TUSB1210 is not set # end of PHY Subsystem @@ -9299,10 +8361,6 @@ CONFIG_ARM_PMU=y CONFIG_ARM_PMU_ACPI=y # CONFIG_ARM_SMMU_V3_PMU is not set # CONFIG_ARM_DSU_PMU is not set -CONFIG_FSL_IMX8_DDR_PMU=m -CONFIG_QCOM_L2_PMU=y -CONFIG_QCOM_L3_PMU=y -# CONFIG_XGENE_PMU is not set # CONFIG_ARM_SPE_PMU is not set # CONFIG_ARM_DMC620_PMU is not set CONFIG_HISI_PMU=y @@ -9329,18 +8387,8 @@ CONFIG_DAX_DRIVER=y CONFIG_DAX=y CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y -# CONFIG_NVMEM_IMX_IIM is not set -CONFIG_NVMEM_IMX_OCOTP=y -CONFIG_NVMEM_IMX_OCOTP_SCU=y -CONFIG_MTK_EFUSE=m -CONFIG_QCOM_QFPROM=y # CONFIG_NVMEM_SPMI_SDAM is not set -CONFIG_ROCKCHIP_EFUSE=y -# CONFIG_ROCKCHIP_OTP is not set CONFIG_NVMEM_SUNXI_SID=y -CONFIG_MESON_EFUSE=m -# CONFIG_MESON_MX_EFUSE is not set -# CONFIG_NVMEM_SNVS_LPGPR is not set # CONFIG_NVMEM_RMEM is not set # @@ -9368,26 +8416,7 @@ CONFIG_PM_OPP=y # CONFIG_SIOX is not set CONFIG_SLIMBUS=m CONFIG_SLIM_QCOM_CTRL=m -CONFIG_SLIM_QCOM_NGD_CTRL=m CONFIG_INTERCONNECT=y -# CONFIG_INTERCONNECT_IMX is not set -CONFIG_INTERCONNECT_QCOM=y -CONFIG_INTERCONNECT_QCOM_BCM_VOTER=m -CONFIG_INTERCONNECT_QCOM_MSM8916=m -# CONFIG_INTERCONNECT_QCOM_MSM8939 is not set -# CONFIG_INTERCONNECT_QCOM_MSM8974 is not set -CONFIG_INTERCONNECT_QCOM_OSM_L3=m -# CONFIG_INTERCONNECT_QCOM_QCS404 is not set -CONFIG_INTERCONNECT_QCOM_RPMH_POSSIBLE=y -CONFIG_INTERCONNECT_QCOM_RPMH=m -# CONFIG_INTERCONNECT_QCOM_SC7180 is not set -# CONFIG_INTERCONNECT_QCOM_SDM660 is not set -CONFIG_INTERCONNECT_QCOM_SDM845=m -# CONFIG_INTERCONNECT_QCOM_SDX55 is not set -CONFIG_INTERCONNECT_QCOM_SM8150=m -CONFIG_INTERCONNECT_QCOM_SM8250=m -# CONFIG_INTERCONNECT_QCOM_SM8350 is not set -CONFIG_INTERCONNECT_QCOM_SMD_RPM=m # CONFIG_COUNTER is not set # CONFIG_MOST is not set # end of Device Drivers @@ -10005,7 +9034,6 @@ CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m -# CONFIG_CRYPTO_DEV_SAHARA is not set # CONFIG_CRYPTO_DEV_ATMEL_ECC is not set # CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set CONFIG_CRYPTO_DEV_CCP=y @@ -10013,20 +9041,8 @@ CONFIG_CRYPTO_DEV_CCP_DD=m CONFIG_CRYPTO_DEV_SP_CCP=y CONFIG_CRYPTO_DEV_CCP_CRYPTO=m # CONFIG_CRYPTO_DEV_CCP_DEBUGFS is not set -# CONFIG_CRYPTO_DEV_MXS_DCP is not set # CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set -CONFIG_CRYPTO_DEV_MARVELL=m -CONFIG_CRYPTO_DEV_MARVELL_CESA=m # CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set -CONFIG_CRYPTO_DEV_QCE=m -CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y -CONFIG_CRYPTO_DEV_QCE_SHA=y -CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL=y -# CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER is not set -# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set -CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512 -CONFIG_CRYPTO_DEV_QCOM_RNG=m -CONFIG_CRYPTO_DEV_ROCKCHIP=m CONFIG_CRYPTO_DEV_VIRTIO=m CONFIG_CRYPTO_DEV_SAFEXCEL=m CONFIG_CRYPTO_DEV_CCREE=m |