diff options
Diffstat (limited to 'fast_cppc.patch')
| -rw-r--r-- | fast_cppc.patch | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/fast_cppc.patch b/fast_cppc.patch new file mode 100644 index 000000000000..ff8fc5c14b03 --- /dev/null +++ b/fast_cppc.patch @@ -0,0 +1,64 @@ +From 2416f3b172dd3ac0d1c7a6371f6a14da8d5f5ed6 Mon Sep 17 00:00:00 2001 +From: Eggz <egnappah@gmail.com> +Date: Mon, 29 Apr 2024 10:36:29 +0200 +Subject: [PATCH 1/1] Enable Fast CPPC + +Signed-off-by: Eggz <egnappah@gmail.com> +--- + arch/x86/include/asm/cpufeatures.h | 1 + + arch/x86/kernel/cpu/scattered.c | 1 + + drivers/cpufreq/amd-pstate.c | 7 ++++++- + 3 files changed, 8 insertions(+), 1 deletion(-) + +diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h +index 76b3b00ff102..653d13b06ea3 100644 +--- a/arch/x86/include/asm/cpufeatures.h ++++ b/arch/x86/include/asm/cpufeatures.h +@@ -466,6 +466,7 @@ + #define X86_FEATURE_BHI_CTRL (21*32+ 2) /* "" BHI_DIS_S HW control available */ + #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* "" BHI_DIS_S HW control enabled */ + #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* "" Clear branch history at vmexit using SW loop */ ++#define X86_FEATURE_FAST_CPPC (21*32 + 5) /* "" AMD Fast CPPC */ + + /* + * BUG word(s) +diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c +index 0ebca40dfd74..cc66cca52b17 100644 +--- a/arch/x86/kernel/cpu/scattered.c ++++ b/arch/x86/kernel/cpu/scattered.c +@@ -50,6 +50,7 @@ static const struct cpuid_bit cpuid_bits[] = { + { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, + { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, + { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, ++ { X86_FEATURE_FAST_CPPC, CPUID_EDX, 15, 0x80000007, 0 }, + { 0, 0, 0, 0, 0 } + }; + +diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c +index 07f341995439..01897e81e3dc 100644 +--- a/drivers/cpufreq/amd-pstate.c ++++ b/drivers/cpufreq/amd-pstate.c +@@ -49,6 +49,7 @@ + + #define AMD_PSTATE_TRANSITION_LATENCY 20000 + #define AMD_PSTATE_TRANSITION_DELAY 1000 ++#define AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY 600 + + /* + * TODO: We need more time to fine tune processors with shared memory solution +@@ -744,7 +745,11 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) + } + + policy->cpuinfo.transition_latency = AMD_PSTATE_TRANSITION_LATENCY; +- policy->transition_delay_us = AMD_PSTATE_TRANSITION_DELAY; ++ ++ if (cpu_feature_enabled(X86_FEATURE_FAST_CPPC)) ++ policy->transition_delay_us = AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY; ++ else ++ policy->transition_delay_us = AMD_PSTATE_TRANSITION_DELAY; + + policy->min = min_freq; + policy->max = max_freq; +-- +2.44.0 + |