From 881d35ea0b43bea05c1c612d5378163fdff8e41c Mon Sep 17 00:00:00 2001 From: Scott B Date: Fri, 14 Jan 2022 17:48:48 -0800 Subject: [PATCH] v5.15.11 s0ix patch 2021-12-22 Squashed commit of the following: commit fd70b1bcaec8a63ed364a8689167a74412986161 Author: Sanket Goswami Date: Tue Nov 30 16:53:18 2021 +0530 platform/x86: amd-pmc: Add support for AMD Smart Trace Buffer (v6) STB (Smart Trace Buffer), is a debug trace buffer that isolates the failures by analyzing the last running feature of a system. This non-intrusive way always runs in the background and stores the trace into the SoC. This patch enables the STB feature by passing module param "enable_stb=1" while loading the driver and provides mechanism to access the STB buffer using the read and write routines. Co-developed-by: Shyam Sundar S K Signed-off-by: Shyam Sundar S K Signed-off-by: Sanket Goswami commit 91be893efd4e2d3ea2e649f0ff28c30695d9afb4 Author: Sanket Goswami Date: Tue Nov 30 16:53:17 2021 +0530 platform/x86: amd-pmc: Simplify error handling and store the pci_dev in amd_pmc_dev structure Handle error-exits in the amd_pmc_probe() to avoid duplication and store the root port information in amd_pmc_probe() so that the information can be used across multiple routines. Suggested-by: Hans de Goede Signed-off-by: Sanket Goswami commit 41a96f89aaafd0fbed12cbb90b24a8d19a108af5 Author: Julian Sikorski Date: Fri Nov 19 17:52:36 2021 +0100 GFXOFF check patch by Lijo Lazar commit a86597f89a17b44ac53c1487527e62ad8e65baf7 Author: Hans de Goede Date: Tue Nov 2 16:32:56 2021 +0100 platform/x86: amd-pmc: Make CONFIG_AMD_PMC depend on RTC_CLASS Since the "Add special handling for timer based S0i3 wakeup" changes the amd-pmc code now relies on symbols from the RTC-class code, add a dependency for this to Kconfig. Fixes: 59348401ebed ("platform/x86: amd-pmc: Add special handling for timer based S0i3 wakeup") Cc: Mario Limonciello Reported-by: Randy Dunlap Signed-off-by: Hans de Goede Acked-by: Mario Limonciello commit dca08ec9373a0064e3009e82e69e484567ae473e Author: Mario Limonciello Date: Tue Oct 26 12:14:43 2021 -0500 platform/x86: amd-pmc: Drop check for valid alarm time This is already checked when calling rtc_read_alarm. Suggested-by: Alexandre Belloni Signed-off-by: Mario Limonciello commit dbe74285fde124bef34cfa22bb7df72707477b48 Author: Mario Limonciello Date: Tue Oct 26 12:14:42 2021 -0500 platform/x86: amd-pmc: Downgrade dev_info message to dev_dbg For the majority of users this information will not be informative as they've chosen to program the RTC before going to sleep. Suggested-by: Alexandre Belloni Signed-off-by: Mario Limonciello commit c61fde9a485b24401aaf6c08c6637e067599647c Author: Mario Limonciello Date: Tue Oct 26 12:14:41 2021 -0500 platform/x86: amd-pmc: fix compilation without CONFIG_RTC_SYSTOHC_DEVICE If the configuration hasn't specified this parameter the rest of the new RTC functionality should just be ignored. Cc: Alexandre Belloni Suggested-by: Hans de Goede Fixes: 59348401ebed ("platform/x86: amd-pmc: Add special handling for timer based S0i3 wakeup") Signed-off-by: Mario Limonciello commit 8d04fcfd9653bce9f1370c149e8908ea00a6d2ea Author: Mario Limonciello Date: Wed Oct 20 11:29:46 2021 -0500 platform/x86: amd-pmc: Add special handling for timer based S0i3 wakeup RTC based wakeup from s0i3 doesn't work properly on some Green Sardine platforms. Because of this, a newer SMU for Green Sardine has the ability to pass wakeup time as argument of the upper 16 bits of OS_HINT message. With older firmware setting the timer value in OS_HINT will cause firmware to reject the hint, so only run this path on: 1) Green Sardine 2) Minimum SMU FW 3) RTC alarm armed during s0i3 entry Using this method has some limitations that the s0i3 wakeup will need to be between 4 seconds and 18 hours, so check those boundary conditions as well and abort the suspend if RTC is armed for too short or too long of a duration. Signed-off-by: Mario Limonciello commit 47fedf9500e3ef4a1ee3f5fee03f566b9f6679fc Author: Mario Limonciello Date: Wed Oct 20 11:29:45 2021 -0500 platform/x86: amd-pmc: adjust arguments for `amd_pmc_send_cmd` Currently the "argument" for the "message" is listed as a boolean value. This works well for the commands used currently, but an additional upcoming command will pass more data in the message. Expand it to be a full 32 bit value. Signed-off-by: Mario Limonciello commit d820e222d6a7f657846484de1c232b238bf09e89 Author: Hans de Goede Date: Tue Sep 28 16:21:22 2021 +0200 platform/x86: amd-pmc: Fix compilation when CONFIG_DEBUGFS is disabled The amd_pmc_get_smu_version() and amd_pmc_idlemask_read() functions are used in the probe / suspend/resume code, so they are also used when CONFIG_DEBUGFS is disabled, move them outside of the #ifdef CONFIG_DEBUGFS block. Note this purely moves the code to above the #ifdef CONFIG_DEBUGFS, the code is completely unchanged. Cc: Shyam Sundar S K Cc: Sanket Goswami Reported-by: Nathan Chancellor Signed-off-by: Hans de Goede commit 1782879c1e13733976efba11c6e5595dca2afd15 Author: Mario Limonciello Date: Fri Sep 24 12:32:06 2021 -0500 ACPI: PM: s2idle: Don't report missing devices as failing constraints ACPI tables may have entries for devices that are not physically present but that can be connected. These devices shouldn't cause constraints checking to fail. Signed-off-by: Mario Limonciello Change-Id: I34f5ca978aab69ff0a0906191eec21649b19fe27 commit b2e8f09951ab7eecf8d73dd651abc755c5dd2d1d Author: Sanket Goswami Date: Tue Sep 21 17:30:20 2021 +0530 platform/x86: amd-pmc: Add a message to print resume time info Add a message to print the resume time information obtained from the smu_metrics structure. Signed-off-by: Shyam Sundar S K Signed-off-by: Sanket Goswami commit 6f6be68720fa830cf6b3e517f56474a030ce40c0 Author: Sanket Goswami Date: Tue Sep 21 17:29:10 2021 +0530 platform/x86: amd-pmc: Send command to dump data after clearing OS_HINT It was reported that the resume stats received from the firmware are always zero. This happens because the SMU expects the driver to send the command to dump the log data after clearing the OS_HINT. Adjust the order of the commands sent to SMU. Signed-off-by: Shyam Sundar S K Signed-off-by: Sanket Goswami commit 72f25bc8b73f5c1c6908b15b47211e62c205bfdc Author: Sanket Goswami Date: Thu Sep 16 18:11:30 2021 +0530 platform/x86: amd-pmc: Check s0i3 cycle status As the PM firmware returns the status of the last s0i3 in the smu_metrics structure, the existing name "s0i3_cyclecount" seems to be a misnomer. Change it accordingly to "s0i3_last_entry_status". Signed-off-by: Sanket Goswami Acked-by: Shyam Sundar S K commit 8d59e38fd582e18deb6d90fdb6450f686ecc1de2 Author: Sanket Goswami Date: Thu Sep 16 18:10:02 2021 +0530 platform/x86: amd-pmc: Export Idlemask values based on the APU IdleMask is the metric used by the PM firmware to know the status of each of the Hardware IP blocks monitored by the PM firmware. Knowing this value is key to get the information of s2idle suspend/resume status. This value is mapped to PMC scratch registers, retrieve them accordingly based on the CPU family and the underlying firmware support. Co-developed-by: Shyam Sundar S K Signed-off-by: Shyam Sundar S K Signed-off-by: Sanket Goswami Acked-by: Shyam Sundar S K Reviewed-by: Mario Limonciello commit 5fa5ab085e4c348a6feb4319b07c9289954b821e Author: Mario Limonciello Date: Wed Sep 15 16:52:16 2021 -0500 ACPI: processor idle: Allow playing dead in C3 commit 1a022e3f1be1 ("idle, x86: Allow off-lined CPU to enter deeper C states") originally allowed offlined CPUs to play dead up to ACPI C2. Although this improves power consumption of offlined CPUs, it does not allow the CPUs to get into the deepest state on AMD platforms blocking s0i3 entry. BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1708 Signed-off-by: Mario Limonciello --- drivers/acpi/processor_idle.c | 3 +- drivers/acpi/x86/s2idle.c | 6 + drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 5 +- drivers/platform/x86/Kconfig | 2 +- drivers/platform/x86/amd-pmc.c | 324 ++++++++++++++++++++-- 5 files changed, 313 insertions(+), 27 deletions(-) diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c index f37fba9e5ba0..9d378dc9e928 100644 --- a/drivers/acpi/processor_idle.c +++ b/drivers/acpi/processor_idle.c @@ -789,7 +789,8 @@ static int acpi_processor_setup_cstates(struct acpi_processor *pr) state->enter = acpi_idle_enter; state->flags = 0; - if (cx->type == ACPI_STATE_C1 || cx->type == ACPI_STATE_C2) { + if (cx->type == ACPI_STATE_C1 || cx->type == ACPI_STATE_C2 + || cx->type == ACPI_STATE_C3) { state->enter_dead = acpi_idle_play_dead; drv->safe_state_index = count; } diff --git a/drivers/acpi/x86/s2idle.c b/drivers/acpi/x86/s2idle.c index 1c48358b43ba..0b65d4623214 100644 --- a/drivers/acpi/x86/s2idle.c +++ b/drivers/acpi/x86/s2idle.c @@ -309,6 +309,12 @@ static void lpi_check_constraints(void) continue; } + if (!acpi_get_first_physical_node(adev)) { + acpi_handle_debug(handle, "LPI: Device is not physically present\n"); + lpi_constraints_table[i].handle = NULL; + continue; + } + if (adev->power.state < lpi_constraints_table[i].min_dstate) acpi_handle_info(handle, "LPI: Constraint not met; min power state:%s current power state:%s\n", diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 04863a797115..8c54041e6c6b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -277,8 +277,11 @@ static int smu_dpm_set_power_gate(void *handle, struct smu_context *smu = handle; int ret = 0; - if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) + if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { + WARN(true, "SMU uninitialized but power %s requested for %u!\n", + gate ? "gate" : "ungate", block_type); return -EOPNOTSUPP; + } switch (block_type) { /* diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig index e21ea3d23e6f..4cc2782635ec 100644 --- a/drivers/platform/x86/Kconfig +++ b/drivers/platform/x86/Kconfig @@ -170,7 +170,7 @@ config ACER_WMI config AMD_PMC tristate "AMD SoC PMC driver" - depends on ACPI && PCI + depends on ACPI && PCI && RTC_CLASS help The driver provides support for AMD Power Management Controller primarily responsible for S2Idle transactions that are driven from diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c index 54b88bedecdf..2f55439e0f66 100644 --- a/drivers/platform/x86/amd-pmc.c +++ b/drivers/platform/x86/amd-pmc.c @@ -17,9 +17,11 @@ #include #include #include +#include #include #include #include +#include #include #include #include @@ -29,6 +31,16 @@ #define AMD_PMC_REGISTER_RESPONSE 0x980 #define AMD_PMC_REGISTER_ARGUMENT 0x9BC +/* PMC Scratch Registers */ +#define AMD_PMC_SCRATCH_REG_CZN 0x94 +#define AMD_PMC_SCRATCH_REG_YC 0xD14 + +/* STB Registers */ +#define AMD_PMC_STB_INDEX_ADDRESS 0xF8 +#define AMD_PMC_STB_INDEX_DATA 0xFC +#define AMD_PMC_STB_PMI_0 0x03E30600 +#define AMD_PMC_STB_PREDEF 0xC6000001 + /* Base address of SMU for mapping physical address to virtual address */ #define AMD_PMC_SMU_INDEX_ADDRESS 0xB8 #define AMD_PMC_SMU_INDEX_DATA 0xBC @@ -76,6 +88,7 @@ #define SOC_SUBSYSTEM_IP_MAX 12 #define DELAY_MIN_US 2000 #define DELAY_MAX_US 3000 +#define FIFO_SIZE 4096 enum amd_pmc_def { MSG_TEST = 0x01, MSG_OS_HINT_PCO, @@ -110,15 +123,26 @@ struct amd_pmc_dev { u32 base_addr; u32 cpu_id; u32 active_ips; +/* SMU version information */ + u16 major; + u16 minor; + u16 rev; struct device *dev; + struct pci_dev *rdev; struct mutex lock; /* generic mutex lock */ #if IS_ENABLED(CONFIG_DEBUG_FS) struct dentry *dbgfs_dir; #endif /* CONFIG_DEBUG_FS */ }; +static bool enable_stb; +module_param(enable_stb, bool, 0644); +MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism"); + static struct amd_pmc_dev pmc; -static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set, u32 *data, u8 msg, bool ret); +static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret); +static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data); +static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf); static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset) { @@ -133,7 +157,7 @@ static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u3 struct smu_metrics { u32 table_version; u32 hint_count; - u32 s0i3_cyclecount; + u32 s0i3_last_entry_status; u32 timein_s0i2; u64 timeentering_s0i3_lastcapture; u64 timeentering_s0i3_totaltime; @@ -147,6 +171,93 @@ struct smu_metrics { u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX]; } __packed; +static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev) +{ + int rc; + u32 val; + + rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, 1); + if (rc) + return rc; + + dev->major = (val >> 16) & GENMASK(15, 0); + dev->minor = (val >> 8) & GENMASK(7, 0); + dev->rev = (val >> 0) & GENMASK(7, 0); + + dev_dbg(dev->dev, "SMU version is %u.%u.%u\n", dev->major, dev->minor, dev->rev); + + return 0; +} + +static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp) +{ + struct amd_pmc_dev *dev = filp->f_inode->i_private; + u32 size = FIFO_SIZE * sizeof(u32); + u32 *buf; + int rc; + + buf = kzalloc(size, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + rc = amd_pmc_read_stb(dev, buf); + if (rc) { + kfree(buf); + return rc; + } + + filp->private_data = buf; + return rc; +} + +static ssize_t amd_pmc_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, + loff_t *pos) +{ + if (!filp->private_data) + return -EINVAL; + + return simple_read_from_buffer(buf, size, pos, filp->private_data, + FIFO_SIZE * sizeof(u32)); +} + +static int amd_pmc_stb_debugfs_release(struct inode *inode, struct file *filp) +{ + kfree(filp->private_data); + return 0; +} + +const struct file_operations amd_pmc_stb_debugfs_fops = { + .owner = THIS_MODULE, + .open = amd_pmc_stb_debugfs_open, + .read = amd_pmc_stb_debugfs_read, + .release = amd_pmc_stb_debugfs_release, +}; + +static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev, + struct seq_file *s) +{ + u32 val; + + switch (pdev->cpu_id) { + case AMD_CPU_ID_CZN: + val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN); + break; + case AMD_CPU_ID_YC: + val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC); + break; + default: + return -EINVAL; + } + + if (dev) + dev_dbg(pdev->dev, "SMU idlemask s0i3: 0x%x\n", val); + + if (s) + seq_printf(s, "SMU idlemask : 0x%x\n", val); + + return 0; +} + #ifdef CONFIG_DEBUG_FS static int smu_fw_info_show(struct seq_file *s, void *unused) { @@ -162,9 +273,12 @@ static int smu_fw_info_show(struct seq_file *s, void *unused) seq_puts(s, "\n=== SMU Statistics ===\n"); seq_printf(s, "Table Version: %d\n", table.table_version); seq_printf(s, "Hint Count: %d\n", table.hint_count); - seq_printf(s, "S0i3 Cycle Count: %d\n", table.s0i3_cyclecount); + seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" : + "Unknown/Fail"); seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture); seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture); + seq_printf(s, "Time (in us) to resume from S0i3: %lld\n", + table.timeto_resume_to_os_lastcapture); seq_puts(s, "\n=== Active time (in us) ===\n"); for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) { @@ -201,6 +315,23 @@ static int s0ix_stats_show(struct seq_file *s, void *unused) } DEFINE_SHOW_ATTRIBUTE(s0ix_stats); +static int amd_pmc_idlemask_show(struct seq_file *s, void *unused) +{ + struct amd_pmc_dev *dev = s->private; + int rc; + + if (dev->major > 56 || (dev->major >= 55 && dev->minor >= 37)) { + rc = amd_pmc_idlemask_read(dev, NULL, s); + if (rc) + return rc; + } else { + seq_puts(s, "Unsupported SMU version for Idlemask\n"); + } + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask); + static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev) { debugfs_remove_recursive(dev->dbgfs_dir); @@ -213,6 +344,12 @@ static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev) &smu_fw_info_fops); debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev, &s0ix_stats_fops); + debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev, + &amd_pmc_idlemask_fops); + /* Enable STB only when the module_param is set */ + if (enable_stb) + debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev, + &amd_pmc_stb_debugfs_fops); } #else static inline void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev) @@ -264,7 +401,7 @@ static void amd_pmc_dump_registers(struct amd_pmc_dev *dev) dev_dbg(dev->dev, "AMD_PMC_REGISTER_MESSAGE:%x\n", value); } -static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set, u32 *data, u8 msg, bool ret) +static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret) { int rc; u32 val; @@ -283,7 +420,7 @@ static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, bool set, u32 *data, u8 msg amd_pmc_reg_write(dev, AMD_PMC_REGISTER_RESPONSE, 0); /* Write argument into response register */ - amd_pmc_reg_write(dev, AMD_PMC_REGISTER_ARGUMENT, set); + amd_pmc_reg_write(dev, AMD_PMC_REGISTER_ARGUMENT, arg); /* Write message ID to message ID register */ amd_pmc_reg_write(dev, AMD_PMC_REGISTER_MESSAGE, msg); @@ -339,21 +476,83 @@ static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev) return -EINVAL; } +static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg) +{ + struct rtc_device *rtc_device; + time64_t then, now, duration; + struct rtc_wkalrm alarm; + struct rtc_time tm; + int rc; + + if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53)) + return 0; + + rtc_device = rtc_class_open("rtc0"); + if (!rtc_device) + return 0; + rc = rtc_read_alarm(rtc_device, &alarm); + if (rc) + return rc; + if (!alarm.enabled) { + dev_dbg(pdev->dev, "alarm not enabled\n"); + return 0; + } + rc = rtc_read_time(rtc_device, &tm); + if (rc) + return rc; + then = rtc_tm_to_time64(&alarm.time); + now = rtc_tm_to_time64(&tm); + duration = then-now; + + /* in the past */ + if (then < now) + return 0; + + /* will be stored in upper 16 bits of s0i3 hint argument, + * so timer wakeup from s0i3 is limited to ~18 hours or less + */ + if (duration <= 4 || duration > U16_MAX) + return -EINVAL; + + *arg |= (duration << 16); + rc = rtc_alarm_irq_enable(rtc_device, 0); + dev_dbg(pdev->dev, "wakeup timer programmed for %lld seconds\n", duration); + + return rc; +} + static int __maybe_unused amd_pmc_suspend(struct device *dev) { struct amd_pmc_dev *pdev = dev_get_drvdata(dev); int rc; u8 msg; + u32 arg = 1; /* Reset and Start SMU logging - to monitor the s0i3 stats */ amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_RESET, 0); amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_START, 0); + /* Activate CZN specific RTC functionality */ + if (pdev->cpu_id == AMD_CPU_ID_CZN) { + rc = amd_pmc_verify_czn_rtc(pdev, &arg); + if (rc < 0) + return rc; + } + + /* Dump the IdleMask before we send hint to SMU */ + amd_pmc_idlemask_read(pdev, dev, NULL); msg = amd_pmc_get_os_hint(pdev); - rc = amd_pmc_send_cmd(pdev, 1, NULL, msg, 0); + rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, 0); if (rc) dev_err(pdev->dev, "suspend failed\n"); + if (enable_stb) + rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_PREDEF); + if (rc) { + dev_err(pdev->dev, "error writing to STB\n"); + return rc; + } + return rc; } @@ -363,14 +562,25 @@ static int __maybe_unused amd_pmc_resume(struct device *dev) int rc; u8 msg; - /* Let SMU know that we are looking for stats */ - amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, 0); - msg = amd_pmc_get_os_hint(pdev); rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, 0); if (rc) dev_err(pdev->dev, "resume failed\n"); + /* Let SMU know that we are looking for stats */ + amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, 0); + + /* Dump the IdleMask to see the blockers */ + amd_pmc_idlemask_read(pdev, dev, NULL); + + /* Write data incremented by 1 to distinguish in stb_read */ + if (enable_stb) + rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_PREDEF + 1); + if (rc) { + dev_err(pdev->dev, "error writing to STB\n"); + return rc; + } + return 0; } @@ -387,6 +597,62 @@ static const struct pci_device_id pmc_pci_ids[] = { { } }; +static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data) +{ + int err; + + err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0); + if (err) { + dev_err(dev->dev, "failed to write addr in stb: 0x%X\n", + AMD_PMC_STB_INDEX_ADDRESS); + err = pcibios_err_to_errno(err); + goto err_pci_dev_put; + } + + err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, data); + if (err) { + dev_err(dev->dev, "failed to write data in stb: 0x%X\n", + AMD_PMC_STB_INDEX_DATA); + err = pcibios_err_to_errno(err); + goto err_pci_dev_put; + } + + return 0; + +err_pci_dev_put: + pci_dev_put(dev->rdev); + return err; +} + +static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf) +{ + int i, err; + + err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0); + if (err) { + dev_err(dev->dev, "error writing addr to stb: 0x%X\n", + AMD_PMC_STB_INDEX_ADDRESS); + err = pcibios_err_to_errno(err); + goto err_pci_dev_put; + } + + for (i = 0; i < FIFO_SIZE; i++) { + err = pci_read_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, buf++); + if (err) { + dev_err(dev->dev, "error reading data from stb: 0x%X\n", + AMD_PMC_STB_INDEX_DATA); + err = pcibios_err_to_errno(err); + goto err_pci_dev_put; + } + } + + return 0; + +err_pci_dev_put: + pci_dev_put(dev->rdev); + return err; +} + static int amd_pmc_probe(struct platform_device *pdev) { struct amd_pmc_dev *dev = &pmc; @@ -400,22 +666,23 @@ static int amd_pmc_probe(struct platform_device *pdev) rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0)); if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) { - pci_dev_put(rdev); - return -ENODEV; + err = -ENODEV; + goto err_pci_dev_put; } dev->cpu_id = rdev->device; + dev->rdev = rdev; err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_LO); if (err) { dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS); - pci_dev_put(rdev); - return pcibios_err_to_errno(err); + err = pcibios_err_to_errno(err); + goto err_pci_dev_put; } err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val); if (err) { - pci_dev_put(rdev); - return pcibios_err_to_errno(err); + err = pcibios_err_to_errno(err); + goto err_pci_dev_put; } base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK; @@ -423,24 +690,25 @@ static int amd_pmc_probe(struct platform_device *pdev) err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_HI); if (err) { dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS); - pci_dev_put(rdev); - return pcibios_err_to_errno(err); + err = pcibios_err_to_errno(err); + goto err_pci_dev_put; } err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val); if (err) { - pci_dev_put(rdev); - return pcibios_err_to_errno(err); + err = pcibios_err_to_errno(err); + goto err_pci_dev_put; } base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK; - pci_dev_put(rdev); base_addr = ((u64)base_addr_hi << 32 | base_addr_lo); dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET, AMD_PMC_MAPPING_SIZE); - if (!dev->regbase) - return -ENOMEM; + if (!dev->regbase) { + err = -ENOMEM; + goto err_pci_dev_put; + } mutex_init(&dev->lock); @@ -449,17 +717,24 @@ static int amd_pmc_probe(struct platform_device *pdev) base_addr_hi = FCH_BASE_PHY_ADDR_HIGH; fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo); dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE); - if (!dev->fch_virt_addr) - return -ENOMEM; + if (!dev->fch_virt_addr) { + err = -ENOMEM; + goto err_pci_dev_put; + } /* Use SMU to get the s0i3 debug stats */ err = amd_pmc_setup_smu_logging(dev); if (err) dev_err(dev->dev, "SMU debugging info not supported on this platform\n"); + amd_pmc_get_smu_version(dev); platform_set_drvdata(pdev, dev); amd_pmc_dbgfs_register(dev); return 0; + +err_pci_dev_put: + pci_dev_put(rdev); + return err; } static int amd_pmc_remove(struct platform_device *pdev) @@ -467,6 +742,7 @@ static int amd_pmc_remove(struct platform_device *pdev) struct amd_pmc_dev *dev = platform_get_drvdata(pdev); amd_pmc_dbgfs_unregister(dev); + pci_dev_put(dev->rdev); mutex_destroy(&dev->lock); return 0; } -- 2.34.1