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pkgbase = python-fusesoc
pkgdesc = Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
pkgver = 1.10
pkgrel = 0
url = http://github.com/olofk/fusesoc/
arch = any
license = GPLv3
makedepends = python-setuptools
depends = python
depends = python-edalize
optdepends = iverilog: for simulating verilog designs
optdepends = ghdl: for simulating VHDL designs
provides = python-fusesoc
conflicts = python-fusesoc
options = !emptydirs
source = git+https://github.com/olofk/fusesoc#tag=1.10
md5sums = SKIP
pkgname = python-fusesoc
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