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From: Antheas Kapenekakis <lkml@antheas.dev>
Subject: [PATCH] drm/amdgpu/vpe: increase VPE_IDLE_TIMEOUT to fix hang on Strix Halo
On Strix Halo, around 8% of suspend resumes result in a soft lock
shortly after the screen turns on. After resume, the delayed init work
runs the VPE ring test, which ungates VPE; VPE_IDLE_TIMEOUT later the
idle work handler tries to power gate it while the SMU is still busy
with the post-resume backlog. The PowerDownVpe message then hangs the
SMU ("SMU: No response msg_reg: 32"), and every subsequent SMU command
(JPEG/VCN gating, DMCUB/DCN programming) serializes through ~4s
timeouts, freezing presentation for tens of seconds.
Increasing the idle timeout from 1s to 2s moves the gate request past
the post-resume SMU rush. Reported to improve a 12s-sleep/8s-resume
stress cycle from 4-25 suspends before hang to 200+.
Upstream submission (not merged, debated as possible SMU firmware
issue): https://lists.freedesktop.org/archives/dri-devel/2025-August/521069.html
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
@@ -34,8 +34,9 @@
/* VPE CSA resides in the 4th page of CSA */
#define AMDGPU_CSA_VPE_OFFSET (4096 * 3)
-/* 1 second timeout */
-#define VPE_IDLE_TIMEOUT msecs_to_jiffies(1000)
+/* 2 second timeout: gating VPE ~1s after the post-resume ring test
+ * races a still-busy SMU on Strix Halo and hangs it (see patch header) */
+#define VPE_IDLE_TIMEOUT msecs_to_jiffies(2000)
#define VPE_MAX_DPM_LEVEL 4
#define FIXED1_8_BITS_PER_FRACTIONAL_PART 8
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