| riscv-openocd-git |
v20180629.r1233.gc116dc50b-1 |
1 |
0.09 |
Fork of OpenOCD that has RISC-V support |
Sequencer
|
| riscv64-unknown-elf-gdb |
10.1-1 |
1 |
0.00 |
The GNU Debugger for the 32bit and 64bit RISC-V bare-metal target |
ryansuchocki
|
| riscv64-unknown-elf-gcc |
9.2.0-2 |
3 |
0.00 |
The GNU Compiler Collection - cross compiler for 32bit and 64bit RISC-V bare-metal |
esmil
|
| riscv64-unknown-elf-binutils |
2.34-1 |
4 |
0.00 |
Assemble and manipulate binary and object files for 32bit and 64bit RISC-V |
esmil
|
| riscv-pk |
1.0.0-2 |
1 |
0.00 |
RISC-V proxy kernel and boot loader |
orphan
|
| riscv64-unknown-elf-picolibc |
1.5.1-1 |
0 |
0.00 |
Fork of newlib with stdio bits from avrlibc |
xiretza
|
| riscv64-unknown-elf-newlib |
3.3.0-1 |
0 |
0.00 |
A C standard library implementation intended for use on embedded systems (microcontrollers) |
esmil
|
| riscv64-linux-gnu-pkg-config |
0.29.2-1 |
0 |
0.00 |
pkg-config that only looks in /usr/riscv64-linux-gnu/lib/pkgconfig and not in /usr/lib/pkgconfig |
1ace
|
| riscv-tests-git |
1-1 |
0 |
0.00 |
Hosts unit tests for RISC-V processors. |
Sequencer
|
| riscv-sifive-elf-newlib |
3.1.0-1 |
0 |
0.00 |
A C standard library implementation intended for use on embedded systems (RISC-V bare metal) |
Sequencer
|
| riscv-sifive-elf-gdb |
8.3-1 |
0 |
0.00 |
The GNU Debugger for the RISC-V (bare-metal) target |
Sequencer
|
| riscv-sifive-elf-gcc-stage1 |
9.1.0-1 |
0 |
0.00 |
Cross compiler for 32-bit and 64-bit RISC-V |
Sequencer
|
| riscv-sifive-elf-gcc |
9.1.0-1 |
0 |
0.00 |
Cross compiler for 32-bit and 64-bit RISC-V |
Sequencer
|
| riscv-sifive-elf-binutils |
2.32-1 |
0 |
0.00 |
A set of programs to assemble and manipulate binary and object files for the RISC-V (bare-metal) target |
Sequencer
|
| riscv-pk-git |
1-1 |
0 |
0.00 |
RISC-V proxy kernel and boot loader |
Sequencer
|
| riscv-isa-sim-git |
r496.785762c-1 |
3 |
0.00 |
Spike, a RISC-V ISA Simulator |
pmatos
|
| riscv-fesvr-git |
r181.0f34d7a-1 |
2 |
0.00 |
RISC-V Frontend Server |
orphan
|
| python-pythondata-cpu-vexriscv-git |
2020.08.r1.g2962f4a-1 |
0 |
0.00 |
Python module containing verilog files for vexriscv cpu (for use with LiteX) |
xiretza
|
| meson-cross-riscv64-linux-gnu |
1-1 |
0 |
0.00 |
Meson cross file for riscv64 |
1ace
|
| hifive1-sdk-git |
r159.261668c-1 |
6 |
0.00 |
The Official SDK of the RISC-V-based HiFive1 Board (and Arty) |
NonerKao
|