verible-bin
|
0.0.3622-1 |
2 |
0.65
|
SystemVerilog parser, linter, formatter and etc from Google |
ildus
|
2024-03-23 07:09 (UTC) |
veridian-bin
|
0.0.0-5 |
1 |
0.03
|
A SystemVerilog Language Server |
kalex
|
2024-03-21 08:30 (UTC) |
svls
|
0.2.11-1 |
4 |
0.02
|
SystemVerilog language server |
otreblan
|
2024-02-11 20:30 (UTC) |
python-vunit_hdl
|
4.7.0-1 |
2 |
0.01
|
Unit Testing Framework for VHDL/SystemVerilog |
smallAndSimple
|
2023-05-14 09:40 (UTC) |
slang-verilog
|
5.0-1 |
3 |
0.00
|
SystemVerilog Language Services |
jrudess
|
2024-03-10 20:36 (UTC) |
yosys-uhdm-plugin
|
924fe98-1 |
0 |
0.00
|
UDHM plugin for Yosys (SystemVerilog support) |
ildus
|
2023-01-19 11:43 (UTC) |
vim-systemverilog-git
|
r17.27d89e8-1 |
0 |
0.00
|
SystemVerilog support for vim |
anatolik
|
2015-11-30 22:46 (UTC) |
verible-git
|
0.0.r558.7fbda6835f-2 |
2 |
0.00
|
SystemVerilog parser, style-linter, and formatter |
accuminium
|
2023-11-11 21:04 (UTC) |
verible
|
0.0r2037.g4cccc6b2-1 |
1 |
0.00
|
SystemVerilog(Verilog) Parser, Style-Linter, and Formatter from Google |
nullik
|
2022-03-19 11:44 (UTC) |
uvm-python-git
|
r1174.26acd2b-1 |
0 |
0.00
|
Port of SystemVerilog Universal Verification Methodology (UVM) 1.2 to Python and cocotb |
mox
|
2021-03-06 11:44 (UTC) |
uhdm-git
|
r2067.496bb31-1 |
0 |
0.00
|
A complete modeling of the IEEE SystemVerilog Object Model |
xiretza
|
2023-09-24 19:59 (UTC) |
tree-sitter-verilog-git
|
0.0.r316.g9020313-1 |
0 |
0.00
|
SystemVerilog grammar for tree-sitter |
Chocobo1
|
2024-01-28 09:11 (UTC) |
svlint
|
0.8.0-1 |
0 |
0.00
|
SystemVerilog linter compliant with IEEE1800-2017 |
Freed
|
2023-07-17 19:34 (UTC) |
svlangserver
|
0.4.0-1 |
0 |
0.00
|
A language server for systemverilog |
h313
|
2022-05-03 06:05 (UTC) |
sv2v-git
|
0.0.r1.g4c3dcf5-1 |
0 |
0.00
|
SystemVerilog to Verilog conversion |
b1f6c1c4
|
2022-01-07 08:51 (UTC) |
sv2v
|
0.0.11-1 |
1 |
0.00
|
SystemVerilog to Verilog conversion |
yrlf
|
2023-12-04 00:00 (UTC) |
surelog-git
|
1.75.r1.ge83d01f-1 |
0 |
0.00
|
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. |
xiretza
|
2023-09-24 20:37 (UTC) |
sigasi
|
5.5.0-1 |
5 |
0.00
|
Eclipse-based commercial VHDL, Verilog and SystemVerilog IDE |
fredericva
|
2024-03-27 20:27 (UTC) |
python-pyuvm
|
2.9.1-1 |
0 |
0.00
|
pyuvm is the Universal Verification Methodology implemented in Python instead of SystemVerilog. pyuvm uses cocotb to interact with the simulator and schedule simulation events. |
m42uko
|
2023-10-13 11:59 (UTC) |