ghdl-gcc-git
|
5.0.0dev.r9326.gec7cd5909-1 |
7 |
0.58
|
VHDL simulator - GCC back-end |
marzoul
|
2024-03-16 11:31 (UTC) |
ghdl-gcc
|
4.1.0-1 |
1 |
0.49
|
VHDL simulator - GCC back-end |
smallAndSimple
|
2024-04-15 16:11 (UTC) |
ghdl-mcode-git
|
4.0.0dev.r8602.g97df73f72-1 |
2 |
0.42
|
VHDL simulator - mcode back-end |
marzoul
|
2023-05-09 19:48 (UTC) |
python-vunit_hdl
|
4.7.0-1 |
2 |
0.01
|
Unit Testing Framework for VHDL/SystemVerilog |
smallAndSimple
|
2023-05-14 09:40 (UTC) |
nvc
|
1.12.0-1 |
2 |
0.00
|
VHDL compiler and simulator |
aperez
|
2024-04-10 22:42 (UTC) |
vhdl-simili
|
3.1b16-5 |
5 |
0.00
|
A low-cost VHDL development system designed for the serious hardware designer. |
robertfoster
|
2018-10-11 14:34 (UTC) |
vhd2vl-git
|
2.5-1 |
1 |
0.00
|
Translate synthesizable VHDL into Verilog 2001 |
marzoul
|
2021-02-06 17:15 (UTC) |
sigasi
|
5.5.0-1 |
5 |
0.00
|
Eclipse-based commercial VHDL, Verilog and SystemVerilog IDE |
fredericva
|
2024-03-27 20:27 (UTC) |
python-vsg-git
|
r1251.960fc7d-1 |
0 |
0.00
|
VHDL style guide: coding style enforcement for VHDL |
orphan
|
2020-06-12 10:23 (UTC) |
python-vsg
|
3.14.0-1 |
0 |
0.00
|
VHDL style guide: coding style enforcement for VHDL |
orphan
|
2023-02-14 08:05 (UTC) |
python-pyvhdlmodel-git
|
0.25.1.r0.g3776f27-2 |
0 |
0.00
|
An abstract VHDL language model written in Python |
xiretza
|
2023-05-07 16:10 (UTC) |
python-pythondata-cpu-microwatt-git
|
2020.08.r219.gd695ff9-1 |
0 |
0.00
|
Python module containing vhdl files for microwatt cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:52 (UTC) |
python-hdlparse-git
|
r20.be7cdab-1 |
0 |
0.00
|
Simple parser for extracting VHDL documentation |
joposter
|
2020-06-02 14:44 (UTC) |
python-cocotb-git
|
r3638.13a4c949-1 |
1 |
0.00
|
Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python |
m42uko
|
2023-10-16 08:53 (UTC) |
python-cocotb-bus-git
|
r3101.a3e22f78-1 |
0 |
0.00
|
Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python |
orphan
|
2021-06-03 10:58 (UTC) |
python-cocotb
|
1.8.1-1 |
3 |
0.00
|
Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python |
m42uko
|
2023-10-16 08:44 (UTC) |
parvaj-bin
|
0.5.2-1 |
0 |
0.00
|
Easy and fast (both in the sense of performance and development speed) VHDL simulation tool, integrating GHDL and GTKWave. |
mkoushan
|
2023-11-23 17:35 (UTC) |
nvc-git
|
r1.11.0.r36.gc1abb4b-1 |
1 |
0.00
|
VHDL compiler and simulator |
m42uko
|
2024-01-11 17:21 (UTC) |
ghdl-yosys-plugin-git
|
r219.5b64ccf-2 |
1 |
0.00
|
VHDL synthesis (based on ghdl and yosys) |
xiretza
|
2023-06-11 08:56 (UTC) |
ghdl-llvm-git
|
4.0.0dev.r8602.g97df73f72-1 |
3 |
0.00
|
VHDL simulator - LLVM back-end |
marzoul
|
2023-05-09 19:49 (UTC) |