Synthesis command does nothing except writing to log file, for example:
GowinSynthesis start
Running parser ...
Analyzing Verilog file '/ramdisk/fpga_project_1/src/main.v'
Analyzing Verilog file '/ramdisk/fpga_project_1/src/sinyalureteci.v'
Analyzing Verilog file '/ramdisk/fpga_project_1/src/uart.v'
GowinSynthesis finish
But no output file at all. It works well with the windows version with wine, but no luck with linux version. Any clue? I am not sure what information I have to provide if anybody would try to understand the situation.
Pinned Comments
yjun commented on 2023-04-15 10:59 (UTC)
open source fpga programmer, as a replacement to Gowin Programmer
https://aur.archlinux.org/packages/openfpgaloader-bin
added as optional dependency in PKGBUILD.