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Package Details: oss-cvc-git r11.d01c4ab-2
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| Git Clone URL: | https://aur.archlinux.org/oss-cvc-git.git (read-only, click to copy) |
|---|---|
| Package Base: | oss-cvc-git |
| Description: | a full IEEE 1364 2005 compliant Verilog Hardware Description Language (HDL) simulator |
| Upstream URL: | https://github.com/cambridgehackers/open-src-cvc |
| Licenses: | custom |
| Conflicts: | oss-cvc |
| Provides: | oss-cvc |
| Submitter: | tequa |
| Maintainer: | tequa |
| Last Packager: | tequa |
| Votes: | 0 |
| Popularity: | 0.000000 |
| First Submitted: | 2020-07-26 15:54 (UTC) |
| Last Updated: | 2020-07-27 12:39 (UTC) |