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Package Details: python-fusesoc-git r1200.ed63efa-1
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| Git Clone URL: | https://aur.archlinux.org/python-fusesoc-git.git (read-only, click to copy) |
|---|---|
| Package Base: | python-fusesoc-git |
| Description: | Package manager and build abstraction tool for FPGA/ASIC development. |
| Upstream URL: | https://github.com/olofk/fusesoc |
| Licenses: | GPLv3 |
| Conflicts: | python-fusesoc |
| Provides: | python-fusesoc-git |
| Submitter: | csantosb |
| Maintainer: | None |
| Last Packager: | csantosb |
| Votes: | 0 |
| Popularity: | 0.000000 |
| First Submitted: | 2020-03-08 18:40 (UTC) |
| Last Updated: | 2020-05-01 15:42 (UTC) |
Dependencies (10)
- python (nogil-python, python36, python32, python39, python38, python37, python312, python310)
- python-edalize-git (python-edalize-git)
- python-jsonschema (python-jsonschema26)
- python-pyaml
- python-setuptools
- git (git-vfs, git-run-command-patch-git, git-git, git-fc) (make)
- python-pip (make)
- ghdl (ghdl-gcc-git, ghdl-mcode-git, ghdl-llvm-git) (optional) – for simulating VHDL designs
- gtkwave (gtkwave-gtk3-tcl, gtkwave-gtk3, gtkwave-tcl) (optional) – for visualizing waveforms
- iverilog (iverilog-git) (optional) – for simulating verilog designs