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Package Details: python-litex-git 2020.04.r867.g5097b7ae-1
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Git Clone URL: | https://aur.archlinux.org/python-litex-git.git (read-only, click to copy) |
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Package Base: | python-litex-git |
Description: | A Migen/MiSoC based Core/SoC builder |
Upstream URL: | https://github.com/enjoy-digital/litex |
Licenses: | MIT |
Conflicts: | python-litex |
Provides: | python-litex |
Replaces: | litex-git |
Submitter: | xiretza |
Maintainer: | xiretza (cbjamo) |
Last Packager: | xiretza |
Votes: | 0 |
Popularity: | 0.000000 |
First Submitted: | 2020-11-17 11:41 (UTC) |
Last Updated: | 2020-11-17 11:41 (UTC) |
Dependencies (8)
- python (python37AUR, python311AUR, python310AUR)
- python-litex (python-litex-gitAUR)
- python-migen (python-migen-gitAUR)
- python-pyserial
- python-pythondata-software-compiler_rt
- python-requests
- git (git-gitAUR, git-glAUR) (make)
- python-setuptools (make)
Required by (11)
- python-litedram-git (requires python-litex)
- python-liteeth-git (requires python-litex)
- python-liteiclink-git (requires python-litex)
- python-litejesd204b-git (requires python-litex)
- python-litepcie-git (requires python-litex)
- python-litesata-git (requires python-litex)
- python-litescope-git (requires python-litex)
- python-litesdcard-git (requires python-litex)
- python-litevideo-git (requires python-litex)
- python-litex-boards-git (requires python-litex)
- python-litex-git (requires python-litex)
Latest Comments
xiretza commented on 2020-11-09 12:44 (UTC)
To avoid problems with the packages in the official repos, all
lite*-git
packages must set (e.g.)provides=(python-litex)
as well asconflicts=(python-litex)
. They should also be be renamed topython-lite*-git
.xiretza commented on 2020-02-03 21:47 (UTC) (edited on 2020-02-03 22:35 (UTC) by xiretza)
Needs
makedepends=('git' 'python-setuptools')
, same for all the otherlite*-git
packages as far as I can tell.cbjamo commented on 2019-03-28 12:21 (UTC)
It looks like those python errors are unrelated to the vexriscv core's missing verilog. They are are from some python2 submodules in upstream. And can safely be ignored.
I'm not sure why those verilog files aren't being copied over. For now I'm manually copying them into the package. When I've got some more time I'll take another look, or if you have any ideas let me know. In any case, the package now installs the verilog correctly.
andres commented on 2019-03-25 20:02 (UTC) (edited on 2019-03-25 20:03 (UTC) by andres)
This PKGBUILD generates multiple errors and silently ignores them, resulting in /usr/lib/python3.7/site-packages/litex/soc/cores/cpu/vexriscv missing verilog files. It looks like some confusion between python2 and python3. https://paste.sr.ht/~andres/f933bc23e1a2640740a2a176c97619a5dc21fa86