|
svls
|
0.2.9-1 |
4 |
0.37
|
SystemVerilog language server |
otreblan
|
2023-07-04 16:23 (UTC) |
|
verible-bin
|
0.0.3424-1 |
1 |
0.01
|
SystemVerilog parser, linter, formatter and etc from Google |
ildus
|
2023-10-22 12:14 (UTC) |
|
iverilog-git
|
s20150603.r1490.g0a86773c5-1 |
2 |
0.00
|
Icarus Verilog simulation and synthesis tool |
gilcu3
|
2022-05-02 09:06 (UTC) |
|
verilogx
|
0.1-1 |
0 |
0.00
|
A simple, easy, and fast Verilog simulator. |
rafiibrahim8
|
2022-04-24 17:37 (UTC) |
|
verible
|
0.0r2037.g4cccc6b2-1 |
1 |
0.00
|
SystemVerilog(Verilog) Parser, Style-Linter, and Formatter from Google |
nullik
|
2022-03-19 11:44 (UTC) |
|
sigasi
|
5.3.0-2 |
5 |
0.00
|
Eclipse-based commercial VHDL, Verilog and SystemVerilog IDE |
fredericva
|
2023-09-29 12:49 (UTC) |
|
questasim
|
2022.4-1 |
0 |
0.00
|
The Questa advanced simulator is the core simulation and debug engine of the Questa verification solution. |
m42uko
|
2023-08-25 09:32 (UTC) |
|
issie-bin
|
3.0.11-3 |
0 |
0.00
|
An intuitive cross-platform hardware design application. |
zxp19821005
|
2023-10-24 10:08 (UTC) |